Wolfgang Denk
17 years ago
commit
7a68389a23
@ -0,0 +1,68 @@ |
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/*
|
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* Copyright (C) 2005-2008 Atmel Corporation |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/clk.h> |
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#include <asm/arch/memory-map.h> |
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#include "sm.h" |
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void clk_init(void) |
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{ |
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uint32_t cksel; |
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|
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/* in case of soft resets, disable watchdog */ |
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sm_writel(WDT_CTRL, SM_BF(KEY, 0x55)); |
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sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa)); |
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|
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#ifdef CONFIG_PLL |
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/* Initialize the PLL */ |
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sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES) |
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| SM_BF(PLLMUL, CFG_PLL0_MUL - 1) |
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| SM_BF(PLLDIV, CFG_PLL0_DIV - 1) |
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| SM_BF(PLLOPT, CFG_PLL0_OPT) |
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| SM_BF(PLLOSC, 0) |
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| SM_BIT(PLLEN))); |
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|
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/* Wait for lock */ |
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while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ; |
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#endif |
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/* Set up clocks for the CPU and all peripheral buses */ |
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cksel = 0; |
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if (CFG_CLKDIV_CPU) |
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cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1); |
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if (CFG_CLKDIV_HSB) |
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cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1); |
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if (CFG_CLKDIV_PBA) |
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cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1); |
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if (CFG_CLKDIV_PBB) |
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cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1); |
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sm_writel(PM_CKSEL, cksel); |
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|
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#ifdef CONFIG_PLL |
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/* Use PLL0 as main clock */ |
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sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); |
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#endif |
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} |
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@ -1,64 +0,0 @@ |
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/* |
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* Copyright (C) 2004-2006 Atmel Corporation |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <asm/sysreg.h> |
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#include <asm/ptrace.h> |
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.section .text.exception,"ax" |
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.global _evba
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.type _evba,@function
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.align 10
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_evba: |
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.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 |
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.align 2
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rjmp unknown_exception |
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.endr |
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.global timer_interrupt_handler
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.type timer_interrupt_handler,@function
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.align 2
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timer_interrupt_handler: |
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/* |
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* Increment timer_overflow and re-write COMPARE with 0xffffffff. |
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* |
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* We're running at interrupt level 3, so we don't need to save |
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* r8-r12 or lr to the stack. |
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*/ |
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lda.w r8, timer_overflow |
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ld.w r9, r8[0] |
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mov r10, -1 |
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mtsr SYSREG_COMPARE, r10 |
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sub r9, -1 |
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st.w r8[0], r9 |
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rete |
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.type unknown_exception, @function
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unknown_exception: |
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pushm r0-r12 |
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sub r8, sp, REG_R12 - REG_R0 - 4 |
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mov r9, lr |
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mfsr r10, SYSREG_RAR_EX |
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mfsr r11, SYSREG_RSR_EX |
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pushm r8-r11 |
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mfsr r12, SYSREG_ECR |
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mov r11, sp |
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rcall do_unknown_exception |
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1: rjmp 1b |
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@ -1,42 +0,0 @@ |
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/*
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* Copyright (C) 2006 Atmel Corporation |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#ifdef CFG_POWER_MANAGER |
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#include <asm/errno.h> |
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#include <asm/io.h> |
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#include <asm/arch/memory-map.h> |
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#include "sm.h" |
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#ifdef CONFIG_PLL |
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#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) |
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#else |
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#define MAIN_CLK_RATE (CFG_OSC0_HZ) |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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#endif /* CFG_POWER_MANAGER */ |
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@ -0,0 +1,61 @@ |
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/*
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* Copyright (C) 2008 Atmel Corporation |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ASM_AVR32_ARCH_HMATRIX_H__ |
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#define __ASM_AVR32_ARCH_HMATRIX_H__ |
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#include <asm/hmatrix-common.h> |
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/* Bitfields in SFR4 (EBI) */ |
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#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET 1 |
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#define HMATRIX_EBI_SDRAM_ENABLE_SIZE 1 |
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#define HMATRIX_EBI_NAND_ENABLE_OFFSET 3 |
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#define HMATRIX_EBI_NAND_ENABLE_SIZE 1 |
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#define HMATRIX_EBI_CF0_ENABLE_OFFSET 4 |
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#define HMATRIX_EBI_CF0_ENABLE_SIZE 1 |
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#define HMATRIX_EBI_CF1_ENABLE_OFFSET 5 |
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#define HMATRIX_EBI_CF1_ENABLE_SIZE 1 |
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#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET 8 |
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#define HMATRIX_EBI_PULLUP_DISABLE_SIZE 1 |
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/* HSB masters */ |
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#define HMATRIX_MASTER_CPU_DCACHE 0 |
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#define HMATRIX_MASTER_CPU_ICACHE 1 |
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#define HMATRIX_MASTER_PDC 2 |
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#define HMATRIX_MASTER_ISI 3 |
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#define HMATRIX_MASTER_USBA 4 |
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#define HMATRIX_MASTER_LCDC 5 |
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#define HMATRIX_MASTER_MACB0 6 |
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#define HMATRIX_MASTER_MACB1 7 |
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#define HMATRIX_MASTER_DMACA_M0 8 |
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#define HMATRIX_MASTER_DMACA_M1 9 |
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/* HSB slaves */ |
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#define HMATRIX_SLAVE_SRAM0 0 |
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#define HMATRIX_SLAVE_SRAM1 1 |
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#define HMATRIX_SLAVE_PBA 2 |
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#define HMATRIX_SLAVE_PBB 3 |
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#define HMATRIX_SLAVE_EBI 4 |
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#define HMATRIX_SLAVE_USBA 5 |
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#define HMATRIX_SLAVE_LCDC 6 |
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#define HMATRIX_SLAVE_DMACA 7 |
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#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */ |
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@ -1,232 +0,0 @@ |
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/*
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* Register definition for the High-speed Bus Matrix |
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*/ |
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#ifndef __ASM_AVR32_HMATRIX2_H__ |
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#define __ASM_AVR32_HMATRIX2_H__ |
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/* HMATRIX2 register offsets */ |
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#define HMATRIX2_MCFG0 0x0000 |
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#define HMATRIX2_MCFG1 0x0004 |
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#define HMATRIX2_MCFG2 0x0008 |
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#define HMATRIX2_MCFG3 0x000c |
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#define HMATRIX2_MCFG4 0x0010 |
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#define HMATRIX2_MCFG5 0x0014 |
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#define HMATRIX2_MCFG6 0x0018 |
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#define HMATRIX2_MCFG7 0x001c |
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#define HMATRIX2_MCFG8 0x0020 |
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#define HMATRIX2_MCFG9 0x0024 |
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#define HMATRIX2_MCFG10 0x0028 |
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#define HMATRIX2_MCFG11 0x002c |
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#define HMATRIX2_MCFG12 0x0030 |
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#define HMATRIX2_MCFG13 0x0034 |
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#define HMATRIX2_MCFG14 0x0038 |
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#define HMATRIX2_MCFG15 0x003c |
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#define HMATRIX2_SCFG0 0x0040 |
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#define HMATRIX2_SCFG1 0x0044 |
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#define HMATRIX2_SCFG2 0x0048 |
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#define HMATRIX2_SCFG3 0x004c |
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#define HMATRIX2_SCFG4 0x0050 |
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#define HMATRIX2_SCFG5 0x0054 |
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#define HMATRIX2_SCFG6 0x0058 |
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#define HMATRIX2_SCFG7 0x005c |
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#define HMATRIX2_SCFG8 0x0060 |
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#define HMATRIX2_SCFG9 0x0064 |
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#define HMATRIX2_SCFG10 0x0068 |
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#define HMATRIX2_SCFG11 0x006c |
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#define HMATRIX2_SCFG12 0x0070 |
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#define HMATRIX2_SCFG13 0x0074 |
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#define HMATRIX2_SCFG14 0x0078 |
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#define HMATRIX2_SCFG15 0x007c |
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#define HMATRIX2_PRAS0 0x0080 |
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#define HMATRIX2_PRBS0 0x0084 |
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#define HMATRIX2_PRAS1 0x0088 |
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#define HMATRIX2_PRBS1 0x008c |
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#define HMATRIX2_PRAS2 0x0090 |
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#define HMATRIX2_PRBS2 0x0094 |
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#define HMATRIX2_PRAS3 0x0098 |
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#define HMATRIX2_PRBS3 0x009c |
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#define HMATRIX2_PRAS4 0x00a0 |
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#define HMATRIX2_PRBS4 0x00a4 |
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#define HMATRIX2_PRAS5 0x00a8 |
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#define HMATRIX2_PRBS5 0x00ac |
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#define HMATRIX2_PRAS6 0x00b0 |
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#define HMATRIX2_PRBS6 0x00b4 |
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#define HMATRIX2_PRAS7 0x00b8 |
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#define HMATRIX2_PRBS7 0x00bc |
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#define HMATRIX2_PRAS8 0x00c0 |
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#define HMATRIX2_PRBS8 0x00c4 |
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#define HMATRIX2_PRAS9 0x00c8 |
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#define HMATRIX2_PRBS9 0x00cc |
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#define HMATRIX2_PRAS10 0x00d0 |
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#define HMATRIX2_PRBS10 0x00d4 |
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#define HMATRIX2_PRAS11 0x00d8 |
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#define HMATRIX2_PRBS11 0x00dc |
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#define HMATRIX2_PRAS12 0x00e0 |
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#define HMATRIX2_PRBS12 0x00e4 |
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#define HMATRIX2_PRAS13 0x00e8 |
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#define HMATRIX2_PRBS13 0x00ec |
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#define HMATRIX2_PRAS14 0x00f0 |
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#define HMATRIX2_PRBS14 0x00f4 |
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#define HMATRIX2_PRAS15 0x00f8 |
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#define HMATRIX2_PRBS15 0x00fc |
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#define HMATRIX2_MRCR 0x0100 |
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#define HMATRIX2_SFR0 0x0110 |
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#define HMATRIX2_SFR1 0x0114 |
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#define HMATRIX2_SFR2 0x0118 |
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#define HMATRIX2_SFR3 0x011c |
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#define HMATRIX2_SFR4 0x0120 |
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#define HMATRIX2_SFR5 0x0124 |
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#define HMATRIX2_SFR6 0x0128 |
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#define HMATRIX2_SFR7 0x012c |
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#define HMATRIX2_SFR8 0x0130 |
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#define HMATRIX2_SFR9 0x0134 |
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#define HMATRIX2_SFR10 0x0138 |
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#define HMATRIX2_SFR11 0x013c |
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#define HMATRIX2_SFR12 0x0140 |
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#define HMATRIX2_SFR13 0x0144 |
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#define HMATRIX2_SFR14 0x0148 |
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#define HMATRIX2_SFR15 0x014c |
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#define HMATRIX2_VERSION 0x01fc |
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|
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/* Bitfields in MCFG0 */ |
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#define HMATRIX2_ULBT_OFFSET 0 |
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#define HMATRIX2_ULBT_SIZE 3 |
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|
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/* Bitfields in SCFG0 */ |
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#define HMATRIX2_SLOT_CYCLE_OFFSET 0 |
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#define HMATRIX2_SLOT_CYCLE_SIZE 8 |
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#define HMATRIX2_DEFMSTR_TYPE_OFFSET 16 |
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#define HMATRIX2_DEFMSTR_TYPE_SIZE 2 |
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#define HMATRIX2_FIXED_DEFMSTR_OFFSET 18 |
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#define HMATRIX2_FIXED_DEFMSTR_SIZE 4 |
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#define HMATRIX2_ARBT_OFFSET 24 |
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#define HMATRIX2_ARBT_SIZE 2 |
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|
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/* Bitfields in PRAS0 */ |
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#define HMATRIX2_M0PR_OFFSET 0 |
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#define HMATRIX2_M0PR_SIZE 4 |
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#define HMATRIX2_M1PR_OFFSET 4 |
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#define HMATRIX2_M1PR_SIZE 4 |
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#define HMATRIX2_M2PR_OFFSET 8 |
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#define HMATRIX2_M2PR_SIZE 4 |
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#define HMATRIX2_M3PR_OFFSET 12 |
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#define HMATRIX2_M3PR_SIZE 4 |
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#define HMATRIX2_M4PR_OFFSET 16 |
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#define HMATRIX2_M4PR_SIZE 4 |
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#define HMATRIX2_M5PR_OFFSET 20 |
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#define HMATRIX2_M5PR_SIZE 4 |
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#define HMATRIX2_M6PR_OFFSET 24 |
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#define HMATRIX2_M6PR_SIZE 4 |
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#define HMATRIX2_M7PR_OFFSET 28 |
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#define HMATRIX2_M7PR_SIZE 4 |
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|
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/* Bitfields in PRBS0 */ |
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#define HMATRIX2_M8PR_OFFSET 0 |
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#define HMATRIX2_M8PR_SIZE 4 |
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#define HMATRIX2_M9PR_OFFSET 4 |
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#define HMATRIX2_M9PR_SIZE 4 |
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#define HMATRIX2_M10PR_OFFSET 8 |
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#define HMATRIX2_M10PR_SIZE 4 |
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#define HMATRIX2_M11PR_OFFSET 12 |
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#define HMATRIX2_M11PR_SIZE 4 |
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#define HMATRIX2_M12PR_OFFSET 16 |
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#define HMATRIX2_M12PR_SIZE 4 |
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#define HMATRIX2_M13PR_OFFSET 20 |
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#define HMATRIX2_M13PR_SIZE 4 |
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#define HMATRIX2_M14PR_OFFSET 24 |
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#define HMATRIX2_M14PR_SIZE 4 |
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#define HMATRIX2_M15PR_OFFSET 28 |
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#define HMATRIX2_M15PR_SIZE 4 |
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|
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/* Bitfields in MRCR */ |
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#define HMATRIX2_RBC0_OFFSET 0 |
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#define HMATRIX2_RBC0_SIZE 1 |
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#define HMATRIX2_RBC1_OFFSET 1 |
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#define HMATRIX2_RBC1_SIZE 1 |
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#define HMATRIX2_RBC2_OFFSET 2 |
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#define HMATRIX2_RBC2_SIZE 1 |
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#define HMATRIX2_RBC3_OFFSET 3 |
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#define HMATRIX2_RBC3_SIZE 1 |
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#define HMATRIX2_RBC4_OFFSET 4 |
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#define HMATRIX2_RBC4_SIZE 1 |
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#define HMATRIX2_RBC5_OFFSET 5 |
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#define HMATRIX2_RBC5_SIZE 1 |
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#define HMATRIX2_RBC6_OFFSET 6 |
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#define HMATRIX2_RBC6_SIZE 1 |
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#define HMATRIX2_RBC7_OFFSET 7 |
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#define HMATRIX2_RBC7_SIZE 1 |
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#define HMATRIX2_RBC8_OFFSET 8 |
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#define HMATRIX2_RBC8_SIZE 1 |
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#define HMATRIX2_RBC9_OFFSET 9 |
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#define HMATRIX2_RBC9_SIZE 1 |
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#define HMATRIX2_RBC10_OFFSET 10 |
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#define HMATRIX2_RBC10_SIZE 1 |
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#define HMATRIX2_RBC11_OFFSET 11 |
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#define HMATRIX2_RBC11_SIZE 1 |
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#define HMATRIX2_RBC12_OFFSET 12 |
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#define HMATRIX2_RBC12_SIZE 1 |
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#define HMATRIX2_RBC13_OFFSET 13 |
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#define HMATRIX2_RBC13_SIZE 1 |
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#define HMATRIX2_RBC14_OFFSET 14 |
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#define HMATRIX2_RBC14_SIZE 1 |
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#define HMATRIX2_RBC15_OFFSET 15 |
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#define HMATRIX2_RBC15_SIZE 1 |
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|
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/* Bitfields in SFR0 */ |
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#define HMATRIX2_SFR_OFFSET 0 |
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#define HMATRIX2_SFR_SIZE 32 |
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|
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/* Bitfields in SFR4 */ |
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#define HMATRIX2_CS1A_OFFSET 1 |
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#define HMATRIX2_CS1A_SIZE 1 |
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#define HMATRIX2_CS3A_OFFSET 3 |
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#define HMATRIX2_CS3A_SIZE 1 |
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#define HMATRIX2_CS4A_OFFSET 4 |
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#define HMATRIX2_CS4A_SIZE 1 |
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#define HMATRIX2_CS5A_OFFSET 5 |
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#define HMATRIX2_CS5A_SIZE 1 |
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#define HMATRIX2_DBPUC_OFFSET 8 |
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#define HMATRIX2_DBPUC_SIZE 1 |
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|
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/* Bitfields in VERSION */ |
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#define HMATRIX2_VERSION_OFFSET 0 |
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#define HMATRIX2_VERSION_SIZE 12 |
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#define HMATRIX2_MFN_OFFSET 16 |
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#define HMATRIX2_MFN_SIZE 3 |
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|
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/* Constants for ULBT */ |
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#define HMATRIX2_ULBT_INFINITE 0 |
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#define HMATRIX2_ULBT_SINGLE 1 |
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#define HMATRIX2_ULBT_FOUR_BEAT 2 |
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#define HMATRIX2_ULBT_SIXTEEN_BEAT 4 |
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|
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/* Constants for DEFMSTR_TYPE */ |
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#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT 0 |
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#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT 1 |
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#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT 2 |
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|
||||
/* Constants for ARBT */ |
||||
#define HMATRIX2_ARBT_ROUND_ROBIN 0 |
||||
#define HMATRIX2_ARBT_FIXED_PRIORITY 1 |
||||
|
||||
/* Bit manipulation macros */ |
||||
#define HMATRIX2_BIT(name) \ |
||||
(1 << HMATRIX2_##name##_OFFSET) |
||||
#define HMATRIX2_BF(name,value) \ |
||||
(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1)) \
|
||||
<< HMATRIX2_##name##_OFFSET) |
||||
#define HMATRIX2_BFEXT(name,value) \ |
||||
(((value) >> HMATRIX2_##name##_OFFSET) \
|
||||
& ((1 << HMATRIX2_##name##_SIZE) - 1)) |
||||
#define HMATRIX2_BFINS(name,value,old) \ |
||||
(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1) \
|
||||
<< HMATRIX2_##name##_OFFSET)) \
|
||||
| HMATRIX2_BF(name,value)) |
||||
|
||||
/* Register access macros */ |
||||
#define hmatrix2_readl(reg) \ |
||||
readl((void *)HMATRIX_BASE + HMATRIX2_##reg) |
||||
#define hmatrix2_writel(reg,value) \ |
||||
writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg) |
||||
|
||||
#endif /* __ASM_AVR32_HMATRIX2_H__ */ |
||||
@ -0,0 +1,131 @@ |
||||
/*
|
||||
* Copyright (C) 2008 Atmel Corporation |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __ASM_AVR32_HMATRIX_COMMON_H__ |
||||
#define __ASM_AVR32_HMATRIX_COMMON_H__ |
||||
|
||||
/* HMATRIX register offsets */ |
||||
struct hmatrix_regs { |
||||
u32 MCFG[16]; |
||||
u32 SCFG[16]; |
||||
struct { |
||||
u32 A; |
||||
u32 B; |
||||
} PRS[16]; |
||||
u32 MRCR; |
||||
u32 __reserved[3]; |
||||
u32 SFR[16]; |
||||
}; |
||||
|
||||
/* Bitfields in MCFG */ |
||||
#define HMATRIX_ULBT_OFFSET 0 |
||||
#define HMATRIX_ULBT_SIZE 3 |
||||
|
||||
/* Bitfields in SCFG */ |
||||
#define HMATRIX_SLOT_CYCLE_OFFSET 0 |
||||
#define HMATRIX_SLOT_CYCLE_SIZE 8 |
||||
#define HMATRIX_DEFMSTR_TYPE_OFFSET 16 |
||||
#define HMATRIX_DEFMSTR_TYPE_SIZE 2 |
||||
#define HMATRIX_FIXED_DEFMSTR_OFFSET 18 |
||||
#define HMATRIX_FIXED_DEFMSTR_SIZE 4 |
||||
#define HMATRIX_ARBT_OFFSET 24 |
||||
#define HMATRIX_ARBT_SIZE 1 |
||||
|
||||
/* Bitfields in PRS.A */ |
||||
#define HMATRIX_M0PR_OFFSET 0 |
||||
#define HMATRIX_M0PR_SIZE 4 |
||||
#define HMATRIX_M1PR_OFFSET 4 |
||||
#define HMATRIX_M1PR_SIZE 4 |
||||
#define HMATRIX_M2PR_OFFSET 8 |
||||
#define HMATRIX_M2PR_SIZE 4 |
||||
#define HMATRIX_M3PR_OFFSET 12 |
||||
#define HMATRIX_M3PR_SIZE 4 |
||||
#define HMATRIX_M4PR_OFFSET 16 |
||||
#define HMATRIX_M4PR_SIZE 4 |
||||
#define HMATRIX_M5PR_OFFSET 20 |
||||
#define HMATRIX_M5PR_SIZE 4 |
||||
#define HMATRIX_M6PR_OFFSET 24 |
||||
#define HMATRIX_M6PR_SIZE 4 |
||||
#define HMATRIX_M7PR_OFFSET 28 |
||||
#define HMATRIX_M7PR_SIZE 4 |
||||
|
||||
/* Bitfields in PRS.B */ |
||||
#define HMATRIX_M8PR_OFFSET 0 |
||||
#define HMATRIX_M8PR_SIZE 4 |
||||
#define HMATRIX_M9PR_OFFSET 4 |
||||
#define HMATRIX_M9PR_SIZE 4 |
||||
#define HMATRIX_M10PR_OFFSET 8 |
||||
#define HMATRIX_M10PR_SIZE 4 |
||||
#define HMATRIX_M11PR_OFFSET 12 |
||||
#define HMATRIX_M11PR_SIZE 4 |
||||
#define HMATRIX_M12PR_OFFSET 16 |
||||
#define HMATRIX_M12PR_SIZE 4 |
||||
#define HMATRIX_M13PR_OFFSET 20 |
||||
#define HMATRIX_M13PR_SIZE 4 |
||||
#define HMATRIX_M14PR_OFFSET 24 |
||||
#define HMATRIX_M14PR_SIZE 4 |
||||
#define HMATRIX_M15PR_OFFSET 28 |
||||
#define HMATRIX_M15PR_SIZE 4 |
||||
|
||||
/* Constants for ULBT */ |
||||
#define HMATRIX_ULBT_INFINITE 0 |
||||
#define HMATRIX_ULBT_SINGLE 1 |
||||
#define HMATRIX_ULBT_FOUR_BEAT 2 |
||||
#define HMATRIX_ULBT_EIGHT_BEAT 3 |
||||
#define HMATRIX_ULBT_SIXTEEN_BEAT 4 |
||||
|
||||
/* Constants for DEFMSTR_TYPE */ |
||||
#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT 0 |
||||
#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT 1 |
||||
#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT 2 |
||||
|
||||
/* Constants for ARBT */ |
||||
#define HMATRIX_ARBT_ROUND_ROBIN 0 |
||||
#define HMATRIX_ARBT_FIXED_PRIORITY 1 |
||||
|
||||
/* Bit manipulation macros */ |
||||
#define HMATRIX_BIT(name) \ |
||||
(1 << HMATRIX_##name##_OFFSET) |
||||
#define HMATRIX_BF(name,value) \ |
||||
(((value) & ((1 << HMATRIX_##name##_SIZE) - 1)) \
|
||||
<< HMATRIX_##name##_OFFSET) |
||||
#define HMATRIX_BFEXT(name,value) \ |
||||
(((value) >> HMATRIX_##name##_OFFSET) \
|
||||
& ((1 << HMATRIX_##name##_SIZE) - 1)) |
||||
#define HMATRIX_BFINS(name,value,old) \ |
||||
(((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1) \
|
||||
<< HMATRIX_##name##_OFFSET)) \
|
||||
| HMATRIX_BF(name,value)) |
||||
|
||||
/* Register access macros */ |
||||
#define __hmatrix_reg(reg) \ |
||||
(((volatile struct hmatrix_regs *)HMATRIX_BASE)->reg) |
||||
#define hmatrix_read(reg) \ |
||||
(__hmatrix_reg(reg)) |
||||
#define hmatrix_write(reg, value) \ |
||||
do { __hmatrix_reg(reg) = (value); } while (0) |
||||
|
||||
#define hmatrix_slave_read(slave, reg) \ |
||||
hmatrix_read(reg[HMATRIX_SLAVE_##slave]) |
||||
#define hmatrix_slave_write(slave, reg, value) \ |
||||
hmatrix_write(reg[HMATRIX_SLAVE_##slave], value) |
||||
|
||||
#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */ |
||||
@ -0,0 +1,203 @@ |
||||
/*
|
||||
* Copyright (C) 2005-2006 Atmel Corporation |
||||
* |
||||
* Configuration settings for the ATSTK1002 CPU daughterboard |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/memory-map.h> |
||||
|
||||
#define CONFIG_AVR32 1 |
||||
#define CONFIG_AT32AP 1 |
||||
#define CONFIG_AT32AP7000 1 |
||||
#define CONFIG_ATSTK1006 1 |
||||
#define CONFIG_ATSTK1000 1 |
||||
|
||||
#define CONFIG_ATSTK1000_EXT_FLASH 1 |
||||
|
||||
/*
|
||||
* Timer clock frequency. We're using the CPU-internal COUNT register |
||||
* for this, so this is equivalent to the CPU core clock frequency |
||||
*/ |
||||
#define CFG_HZ 1000 |
||||
|
||||
/*
|
||||
* Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
||||
* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the |
||||
* PLL frequency. |
||||
* (CFG_OSC0_HZ * CFG_PLL0_MUL) / CFG_PLL0_DIV = PLL MHz |
||||
*/ |
||||
#define CONFIG_PLL 1 |
||||
#define CFG_POWER_MANAGER 1 |
||||
#define CFG_OSC0_HZ 20000000 |
||||
#define CFG_PLL0_DIV 1 |
||||
#define CFG_PLL0_MUL 7 |
||||
#define CFG_PLL0_SUPPRESS_CYCLES 16 |
||||
/*
|
||||
* Set the CPU running at: |
||||
* PLL / (2^CFG_CLKDIV_CPU) = CPU MHz |
||||
*/ |
||||
#define CFG_CLKDIV_CPU 0 |
||||
/*
|
||||
* Set the HSB running at: |
||||
* PLL / (2^CFG_CLKDIV_HSB) = HSB MHz |
||||
*/ |
||||
#define CFG_CLKDIV_HSB 1 |
||||
/*
|
||||
* Set the PBA running at: |
||||
* PLL / (2^CFG_CLKDIV_PBA) = PBA MHz |
||||
*/ |
||||
#define CFG_CLKDIV_PBA 2 |
||||
/*
|
||||
* Set the PBB running at: |
||||
* PLL / (2^CFG_CLKDIV_PBB) = PBB MHz |
||||
*/ |
||||
#define CFG_CLKDIV_PBB 1 |
||||
|
||||
/*
|
||||
* The PLLOPT register controls the PLL like this: |
||||
* icp = PLLOPT<2> |
||||
* ivco = PLLOPT<1:0> |
||||
* |
||||
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). |
||||
*/ |
||||
#define CFG_PLL0_OPT 0x04 |
||||
|
||||
#undef CONFIG_USART0 |
||||
#define CONFIG_USART1 1 |
||||
#undef CONFIG_USART2 |
||||
#undef CONFIG_USART3 |
||||
|
||||
/* User serviceable stuff */ |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
#define CONFIG_STACKSIZE (2048) |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_BOOTARGS \ |
||||
"console=ttyS0 root=mtd3 fbmem=2400k" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"fsload; bootm $(fileaddr)" |
||||
|
||||
/*
|
||||
* Only interrupt autoboot if <space> is pressed. Otherwise, garbage |
||||
* data on the serial line may interrupt the boot sequence. |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 1 |
||||
#define CONFIG_AUTOBOOT 1 |
||||
#define CONFIG_AUTOBOOT_KEYED 1 |
||||
#define CONFIG_AUTOBOOT_PROMPT \ |
||||
"Press SPACE to abort autoboot in %d seconds\n" |
||||
#define CONFIG_AUTOBOOT_DELAY_STR "d" |
||||
#define CONFIG_AUTOBOOT_STOP_STR " " |
||||
|
||||
/*
|
||||
* After booting the board for the first time, new ethernet addresses |
||||
* should be generated and assigned to the environment variables |
||||
* "ethaddr" and "eth1addr". This is normally done during production. |
||||
*/ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_MMC |
||||
|
||||
#undef CONFIG_CMD_AUTOSCRIPT |
||||
#undef CONFIG_CMD_FPGA |
||||
#undef CONFIG_CMD_SETGETDCR |
||||
#undef CONFIG_CMD_XIMG |
||||
|
||||
#define CONFIG_ATMEL_USART 1 |
||||
#define CONFIG_MACB 1 |
||||
#define CONFIG_PIO2 1 |
||||
#define CFG_NR_PIOS 5 |
||||
#define CFG_HSDRAMC 1 |
||||
#define CONFIG_MMC 1 |
||||
|
||||
#define CFG_DCACHE_LINESZ 32 |
||||
#define CFG_ICACHE_LINESZ 32 |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
|
||||
/* External flash on STK1000 */ |
||||
#if 0 |
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#endif |
||||
|
||||
#define CFG_FLASH_BASE 0x00000000 |
||||
#define CFG_FLASH_SIZE 0x800000 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#define CFG_MAX_FLASH_SECT 135 |
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
|
||||
#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE |
||||
#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE |
||||
#define CFG_SDRAM_BASE EBI_SDRAM_BASE |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 65536 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) |
||||
|
||||
#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) |
||||
|
||||
#define CFG_MALLOC_LEN (256*1024) |
||||
#define CFG_DMA_ALLOC_LEN (16384) |
||||
|
||||
/* Allow 4MB for the kernel run-time image */ |
||||
#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
||||
#define CFG_BOOTPARAMS_LEN (16 * 1024) |
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */ |
||||
#define CFG_PROMPT "U-Boot> " |
||||
#define CFG_CBSIZE 256 |
||||
#define CFG_MAXARGS 16 |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
#define CFG_LONGHELP 1 |
||||
|
||||
#define CFG_MEMTEST_START EBI_SDRAM_BASE |
||||
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x3f00000) |
||||
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue