- Add support for RPC/STx GP3, Motorola 8560 board - Update 85xx TSEC driver so it searches MII for first available PHY and uses that one. - Add functions to support console MII commands. * Patch by Tolunay Orkun, 07 Apr 2004: Move initialization of bi_iic_fast[] from board_init_f() to board_init_r() * Patch by Yasushi Shoji, 07 Apr 2004: Cleanup microblaze port * Patch by Sangmoon Kim, 07 Apr 2004: Add auto SDRAM module detection for Debris boardmaster
parent
d4326aca18
commit
7abf0c5886
@ -0,0 +1,48 @@ |
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#
|
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# (C) Copyright 2001
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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SOBJS := init.o
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#SOBJS :=
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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|
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#########################################################################
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|
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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|
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-include .depend |
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|
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#########################################################################
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@ -0,0 +1,33 @@ |
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
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# (C) Copyright 2002,2003 Motorola Inc.
|
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#
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# Copied from ADS85xx for STx GP3 - Dan Malek
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# default CCARBAR is at 0xff700000
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# assume U-Boot is less than 0.5MB
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#
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TEXT_BASE = 0xfff80000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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@ -0,0 +1,517 @@ |
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/*
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* (C) Copyright 2003, Dan Malek, Embedded Edge, LLC. <dan@embeddededge.com> |
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* Copied from ADS85xx. |
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* Updated to support the Silicon Tx GP3 8560. We should only find |
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* two Intel 28F640 parts in 16-bit mode (i.e. 32-bit wide flash), |
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* but I left other code here in case people order custom boards. |
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* |
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* (C) Copyright 2003 Motorola Inc. |
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* Xianghua Xiao,(X.Xiao@motorola.com) |
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* |
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* (C) Copyright 2000, 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com |
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* Add support the Sharp chips on the mpc8260ads. |
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* I started with board/ip860/flash.c and made changes I found in |
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* the MTD project by David Schleef. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#if !defined(CFG_NO_FLASH) |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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#if defined(CFG_ENV_IS_IN_FLASH) |
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# ifndef CFG_ENV_ADDR |
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
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# endif |
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# ifndef CFG_ENV_SIZE |
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# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
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# endif |
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# ifndef CFG_ENV_SECT_SIZE |
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# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
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# endif |
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#endif |
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#undef DEBUG |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static int clear_block_lock_bit(vu_long * addr); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size; |
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int i; |
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/* Init: enable write,
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* or we cannot even write flash commands |
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*/ |
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for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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/* set the default sector offset */ |
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} |
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/* Static FLASH Bank configuration here - FIXME XXX */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
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size, size<<20); |
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} |
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/* Re-do sizing to get full correct info */ |
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size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
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flash_info[0].size = size; |
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#if !defined(CONFIG_RAM_AS_FLASH) |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE+monitor_flash_len-1, |
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&flash_info[0]); |
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#endif |
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#ifdef CFG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, |
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&flash_info[0]); |
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#endif |
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#endif |
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return (size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: printf ("Intel "); break; |
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case FLASH_MAN_SHARP: printf ("Sharp "); break; |
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default: printf ("Unknown Vendor "); break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F640C3T: printf ("28F640C3T (64 Mbit x 2, 128 x 128k)\n"); |
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break; |
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default: printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " " |
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); |
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} |
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printf ("\n"); |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
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{ |
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short i; |
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ulong value; |
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ulong base = (ulong)addr; |
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ulong sector_offset; |
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#ifdef DEBUG |
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printf("Check flash at 0x%08x\n",(uint)addr); |
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#endif |
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/* Write "Intelligent Identifier" command: read Manufacturer ID */ |
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*addr = 0x90909090; |
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udelay(20); |
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asm("sync"); |
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value = addr[0] & 0x00FF00FF; |
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#ifdef DEBUG |
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printf("manufacturer=0x%x\n",(uint)value); |
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#endif |
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switch (value) { |
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case MT_MANUFACT: /* SHARP, MT or => Intel */ |
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case INTEL_ALT_MANU: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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printf("unknown manufacturer: %x\n", (unsigned int)value); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* no or unknown flash */ |
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} |
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value = addr[1]; /* device ID */ |
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#ifdef DEBUG |
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printf("deviceID=0x%x\n",(uint)value); |
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#endif |
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switch (value) { |
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case (INTEL_ID_28F640C3T): |
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info->flash_id += FLASH_28F640C3T; |
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info->sector_count = 135; |
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info->size = 0x01000000; |
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sector_offset = 0x20000; |
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break; /* => 2x8 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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return (0); /* => no or unknown flash */ |
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} |
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/* set up sector start address table
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* The first 127 blocks are large, the last 8 are small. |
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*/ |
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for (i = 0; i < 127; i++) { |
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info->start[i] = base; |
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base += sector_offset; |
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/* Sectors are locked upon reset */ |
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info->protect[i] = 0; |
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} |
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for (i = 127; i < 135; i++) { |
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info->start[i] = base; |
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base += 0x4000; |
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/* Sectors are locked upon reset */ |
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info->protect[i] = 0; |
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} |
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|
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/*
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* Prevent writes to uninitialized FLASH. |
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*/ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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addr = (vu_long *)info->start[0]; |
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*addr = 0xFFFFFF; /* reset bank to read array mode */ |
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asm("sync"); |
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} |
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return (info->size); |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong start, now, last; |
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|
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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|
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if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) |
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&& ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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|
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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|
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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|
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#ifdef DEBUG |
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printf("\nFlash Erase:\n"); |
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#endif |
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/* Make Sure Block Lock Bit is not set. */ |
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if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ |
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return 1; |
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} |
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|
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/* Start erase on unprotected sectors */ |
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#if defined(DEBUG) |
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printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); |
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#endif |
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for (sect = s_first; sect<=s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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vu_long *addr = (vu_long *)(info->start[sect]); |
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asm("sync"); |
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|
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last = start = get_timer (0); |
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|
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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|
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/* Reset Array */ |
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*addr = 0xffffffff; |
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asm("sync"); |
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/* Clear Status Register */ |
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*addr = 0x50505050; |
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asm("sync"); |
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/* Single Block Erase Command */ |
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*addr = 0x20202020; |
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asm("sync"); |
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/* Confirm */ |
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*addr = 0xD0D0D0D0; |
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asm("sync"); |
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|
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if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { |
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/* Resume Command, as per errata update */ |
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*addr = 0xD0D0D0D0; |
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asm("sync"); |
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} |
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|
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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|
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/* wait at least 80us - let's wait 1 ms */ |
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udelay (1000); |
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while ((*addr & 0x00800080) != 0x00800080) { |
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if(*addr & 0x00200020){ |
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printf("Error in Block Erase - Lock Bit may be set!\n"); |
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printf("Status Register = 0x%X\n", (uint)*addr); |
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*addr = 0xFFFFFFFF; /* reset bank */ |
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asm("sync"); |
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return 1; |
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} |
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if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
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*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
/* reset to read mode */ |
||||
*addr = 0xFFFFFFFF; |
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asm("sync"); |
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} |
||||
} |
||||
|
||||
printf ("flash erase done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
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* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long *)dest; |
||||
ulong start, csr; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*addr & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* Write Command */ |
||||
*addr = 0x10101010; |
||||
asm("sync"); |
||||
|
||||
/* Write Data */ |
||||
*addr = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
flag = 0; |
||||
|
||||
while (((csr = *addr) & 0x00800080) != 0x00800080) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
flag = 1; |
||||
break; |
||||
} |
||||
} |
||||
if (csr & 0x40404040) { |
||||
printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); |
||||
flag = 1; |
||||
} |
||||
|
||||
/* Clear Status Registers Command */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
/* Reset to read array mode */ |
||||
*addr = 0xFFFFFFFF; |
||||
asm("sync"); |
||||
|
||||
return (flag); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Clear Block Lock Bit, returns: |
||||
* 0 - OK |
||||
* 1 - Timeout |
||||
*/ |
||||
|
||||
static int clear_block_lock_bit(vu_long * addr) |
||||
{ |
||||
ulong start, now; |
||||
|
||||
/* Reset Array */ |
||||
*addr = 0xffffffff; |
||||
asm("sync"); |
||||
/* Clear Status Register */ |
||||
*addr = 0x50505050; |
||||
asm("sync"); |
||||
|
||||
*addr = 0x60606060; |
||||
asm("sync"); |
||||
*addr = 0xd0d0d0d0; |
||||
asm("sync"); |
||||
|
||||
start = get_timer (0); |
||||
while((*addr & 0x00800080) != 0x00800080){ |
||||
if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout on clearing Block Lock Bit\n"); |
||||
*addr = 0xFFFFFFFF; /* reset bank */ |
||||
asm("sync"); |
||||
return 1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
#endif /* !CFG_NO_FLASH */ |
@ -0,0 +1,153 @@ |
||||
/* |
||||
* Copyright (C) 2003 Embedded Edge, LLC |
||||
* Dan Malek <dan@embeddededge.com>
|
||||
* Copied from ADS85xx. |
||||
* Updates for Silicon Tx GP3 8560. We only support 32-bit flash |
||||
* and DDR with SPD EEPROM configuration. |
||||
* |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
/* TLB1 entries configuration: */ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* If RAMBOOT, we are testing and the BDI has set up |
||||
* much of the MMU already. |
||||
* TLB 4,5 SDRAM |
||||
* TLB 15 is default CCSRBAR. |
||||
*/ |
||||
.long 0x09 /* the following data table uses a few of 16 TLB entries */ |
||||
|
||||
.long TLB1_MAS0(1,1,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,2,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) |
||||
.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,3,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_LBC_LCLDEVS_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
.long TLB1_MAS0(1,4,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,5,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,6,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
#else |
||||
.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
#endif |
||||
.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,7,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
#ifdef CONFIG_L2_INIT_RAM |
||||
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) |
||||
#else |
||||
.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) |
||||
#endif |
||||
.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(1,8,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
.long TLB1_MAS0(1,15,0) |
||||
.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) |
||||
#else |
||||
.long TLB1_MAS0(1,15,0) |
||||
.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long TLB1_MAS2(0,0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) |
||||
#endif |
||||
entry_end |
||||
|
||||
/* LAW(Local Access Window) configuration: |
||||
* 0000_0000-8000_0000: Up to 2G DDR |
||||
* f000_0000-f3ff_ffff: PCI(256M) |
||||
* f400_0000-f7ff_ffff: RapidIO(128M) |
||||
* f800_0000-ffff_ffff: localbus(128M) |
||||
* f800_0000-fbff_ffff: LBC SDRAM(64M) |
||||
* fc00_0000-fcff_ffff: LBC BCSR (1M, Chip select 1) |
||||
* fdf0_0000-fdff_ffff: CCSRBAR(1M) |
||||
* ff00_0000-ffff_ffff: Flash(16M) |
||||
* We don't need a local window for CCSRBAR and flash because they |
||||
* reside in their default mapped spaces. |
||||
*/ |
||||
|
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_2G)) & ~LAWAR_EN) |
||||
|
||||
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR2 0 |
||||
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x03
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 |
||||
entry_end |
@ -0,0 +1,424 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Embedded Edge, LLC |
||||
* Dan Malek, <dan@embeddededge.com> |
||||
* Copied from ADS85xx. |
||||
* Updates for Silicon Tx GP3 8560 |
||||
* |
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
extern long int spd_sdram (void); |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <ioports.h> |
||||
#include <asm/io.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
|
||||
long int fixed_sdram (void); |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ |
||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ |
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
static uint64_t blinky_increment; |
||||
static uint64_t next_led_update; |
||||
static uint led_bit; |
||||
|
||||
int board_pre_init (void) |
||||
{ |
||||
#if defined(CONFIG_PCI) |
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_pcix_t *pci = &immr->im_pcix; |
||||
|
||||
pci->peer &= 0xfffffffdf; /* disable master abort */ |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void reset_phy (void) |
||||
{ |
||||
volatile uint *blatch; |
||||
|
||||
blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; |
||||
|
||||
/* reset Giga bit Ethernet port if needed here */ |
||||
|
||||
*blatch &= ~0x000000c0; |
||||
udelay(100); |
||||
*blatch = 0x000000c1; /* Light one led, too */ |
||||
udelay(1000); |
||||
|
||||
#if 0 /* This is the port we really want to use for debugging. */
|
||||
/* reset the CPM FEC port */ |
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
bcsr->bcsr2 &= ~FETH2_RST; |
||||
udelay(2); |
||||
bcsr->bcsr2 |= FETH2_RST; |
||||
udelay(1000); |
||||
#elif (CONFIG_ETHER_INDEX == 3) |
||||
bcsr->bcsr3 &= ~FETH3_RST; |
||||
udelay(2); |
||||
bcsr->bcsr3 |= FETH3_RST; |
||||
udelay(1000); |
||||
#endif |
||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) |
||||
miiphy_reset(0x0); /* reset PHY */ |
||||
miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */ |
||||
miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); |
||||
#endif /* CONFIG_MII */ |
||||
#endif |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
sys_info_t sysinfo; |
||||
|
||||
get_sys_info (&sysinfo); |
||||
|
||||
printf ("Board: Silicon Tx GPPP 8560 Board\n"); |
||||
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); |
||||
printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); |
||||
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); |
||||
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|
||||
|| (CFG_LBC_LCRR & 0x0f) == 8) { |
||||
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); |
||||
} else { |
||||
printf("\tLBC: unknown\n"); |
||||
} |
||||
printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); |
||||
printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/* Blinkin' LEDS for Robert.
|
||||
*/ |
||||
void |
||||
show_activity(int flag) |
||||
{ |
||||
volatile uint *blatch; |
||||
|
||||
if (next_led_update > get_ticks()) |
||||
return; |
||||
|
||||
blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; |
||||
|
||||
led_bit >>= 1; |
||||
if (led_bit == 0) |
||||
led_bit = 0x08; |
||||
*blatch = (0xc0 | led_bit); |
||||
eieio(); |
||||
next_led_update += (get_tbclk() / 4); |
||||
} |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
extern long spd_sdram (void); |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
volatile ccsr_gur_t *gur= &immap->im_gur; |
||||
uint temp_ddrdll = 0; |
||||
|
||||
/* Work around to stabilize DDR DLL */ |
||||
temp_ddrdll = gur->ddrdllcr; |
||||
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; |
||||
asm("sync;isync;msync"); |
||||
#endif |
||||
|
||||
dram_size = spd_sdram (); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
{ |
||||
/* Initialize all of memory for ECC, then
|
||||
* enable errors */ |
||||
uint *p = 0; |
||||
uint i = 0; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
||||
dma_init(); |
||||
for (*p = 0; p < (uint *)(8 * 1024); p++) { |
||||
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } |
||||
*p = (unsigned int)0xdeadbeef; |
||||
if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } |
||||
} |
||||
|
||||
/* 8K */ |
||||
dma_xfer((uint *)0x2000,0x2000,(uint *)0); |
||||
/* 16K */ |
||||
dma_xfer((uint *)0x4000,0x4000,(uint *)0); |
||||
/* 32K */ |
||||
dma_xfer((uint *)0x8000,0x8000,(uint *)0); |
||||
/* 64K */ |
||||
dma_xfer((uint *)0x10000,0x10000,(uint *)0); |
||||
/* 128k */ |
||||
dma_xfer((uint *)0x20000,0x20000,(uint *)0); |
||||
/* 256k */ |
||||
dma_xfer((uint *)0x40000,0x40000,(uint *)0); |
||||
/* 512k */ |
||||
dma_xfer((uint *)0x80000,0x80000,(uint *)0); |
||||
/* 1M */ |
||||
dma_xfer((uint *)0x100000,0x100000,(uint *)0); |
||||
/* 2M */ |
||||
dma_xfer((uint *)0x200000,0x200000,(uint *)0); |
||||
/* 4M */ |
||||
dma_xfer((uint *)0x400000,0x400000,(uint *)0); |
||||
|
||||
for (i = 1; i < dram_size / 0x800000; i++) { |
||||
dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); |
||||
} |
||||
|
||||
/* Enable errors for ECC */ |
||||
ddr->err_disable = 0x00000000; |
||||
asm("sync;isync;msync"); |
||||
} |
||||
#endif |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
#ifndef CFG_RAMBOOT |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS; |
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG; |
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1; |
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2; |
||||
ddr->sdram_mode = CFG_DDR_MODE; |
||||
ddr->sdram_interval = CFG_DDR_INTERVAL; |
||||
#if defined (CONFIG_DDR_ECC) |
||||
ddr->err_disable = 0x0000000D; |
||||
ddr->err_sbe = 0x00ff0000; |
||||
#endif |
||||
asm("sync;isync;msync"); |
||||
udelay(500); |
||||
#if defined (CONFIG_DDR_ECC) |
||||
/* Enable ECC checking */ |
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); |
||||
#else |
||||
ddr->sdram_cfg = CFG_DDR_CONTROL; |
||||
#endif |
||||
asm("sync; isync; msync"); |
||||
udelay(500); |
||||
#endif |
||||
return ( CFG_SDRAM_SIZE * 1024 * 1024); |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
@ -0,0 +1,157 @@ |
||||
/* |
||||
* (C) Copyright 2003 Embedded Edge, LLC |
||||
* Dan Malek, <dan@embeddededge.com> |
||||
* Copied from ADS85xx. |
||||
* Updates for Silicon Tx GP3 8560. |
||||
* |
||||
* (C) Copyright 2002,2003,Motorola,Inc. |
||||
* Xianghua Xiao, X.Xiao@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/stxgp3/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/stxgp3/init.o (.text) |
||||
cpu/mpc85xx/commproc.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/serial_scc.o (.text) |
||||
cpu/mpc85xx/ether_fcc.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
cpu/mpc85xx/tsec.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
cpu/mpc85xx/i2c.o (.text) |
||||
cpu/mpc85xx/spd_sdram.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,403 @@ |
||||
/*
|
||||
* (C) Copyright 2003 Embedded Edge, LLC |
||||
* Dan Malek <dan@embeddededge.com> |
||||
* Copied from ADS85xx. |
||||
* Updates for Silicon Tx GP3 8560 board. |
||||
* |
||||
* (C) Copyright 2002,2003 Motorola,Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* mpc8560ads board configuration file */ |
||||
/* please refer to doc/README.mpc85xx for more info */ |
||||
/* make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
||||
#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ |
||||
#define CONFIG_MPC8560 1 /* MPC8560 specific */ |
||||
#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ |
||||
|
||||
#undef CONFIG_PCI /* pci ethernet support */ |
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support*/ |
||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
|
||||
#if defined(CONFIG_MPC85xx_REV1) |
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
#endif |
||||
|
||||
/* Using Localbus SDRAM to emulate flash before we can program the flash,
|
||||
* normally you need a flash-boot image(u-boot.bin), if so undef this. |
||||
*/ |
||||
#undef CONFIG_RAM_AS_FLASH |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ |
||||
|
||||
/* Blinkin' LEDs for Robert :-)
|
||||
*/ |
||||
#define CONFIG_SHOW_ACTIVITY 1 |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */ |
||||
#define CONFIG_DDR_SETTING |
||||
#endif |
||||
|
||||
/* below can be toggled for performance analysis. otherwise use default */ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#undef CONFIG_BTB /* toggle branch predition */ |
||||
#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ |
||||
defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
|
||||
defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) |
||||
#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." |
||||
#endif |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
/* GPPP supports up to 2G of DRAM. Allocate up to 1G until we get
|
||||
* a chance to try it out. Actual size is always read from sdram eeprom. |
||||
*/ |
||||
#define CFG_SDRAM_SIZE 1024 /* DDR is 1GB */ |
||||
|
||||
/* Localbus SDRAM is an option, not all boards have it.
|
||||
*/ |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
||||
#else |
||||
#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ |
||||
#endif |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ |
||||
#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ |
||||
#else /* Boot from real Flash */ |
||||
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
||||
#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ |
||||
#endif |
||||
|
||||
#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 136 /* sectors per device */ |
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* The configuration latch is Chip Select 1.
|
||||
* It's an 8-bit latch in the upper 8 bits of the word. |
||||
*/ |
||||
#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */ |
||||
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ |
||||
#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#ifdef CFG_RAMBOOT |
||||
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ |
||||
#else |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#endif |
||||
#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
|
||||
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ |
||||
|
||||
#if defined(CONFIG_DDR_SETTING) |
||||
#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ |
||||
#define CFG_DDR_CS0_CONFIG 0x80000002 |
||||
#define CFG_DDR_TIMING_1 0x37344321 |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/ |
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/ |
||||
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
||||
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/ |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/* local bus definitions */ |
||||
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
#define CFG_LBC_LSRT 0x20000000 |
||||
#define CFG_LBC_MRTPR 0x20000000 |
||||
#define CFG_LBC_LSDMR_1 0x2861b723 |
||||
#define CFG_LBC_LSDMR_2 0x0861b723 |
||||
#define CFG_LBC_LSDMR_3 0x0861b723 |
||||
#define CFG_LBC_LSDMR_4 0x1861b723 |
||||
#define CFG_LBC_LSDMR_5 0x4061b723 |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
||||
#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
||||
|
||||
#define CONFIG_BAUDRATE 38400 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#if 0 |
||||
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
||||
#else |
||||
/* I did the 'if 0' so we could keep the syntax above if ever needed. */ |
||||
#undef CFG_I2C_NOPROBES |
||||
#endif |
||||
|
||||
#define CFG_PCI_MEM_BASE 0xe0000000 |
||||
#define CFG_PCI_MEM_PHYS 0xe0000000 |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#if defined(CONFIG_PCI) /* PCI Ethernet card */ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */ |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0003 |
||||
#else |
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x0009 |
||||
#endif |
||||
#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 8 /* PHY address */ |
||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
||||
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - Select bus for bd/buffers |
||||
* - Full duplex |
||||
*/ |
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
#define CFG_CPMFCR_RAMTYPE 0 |
||||
#if 0 |
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE) |
||||
#else |
||||
#define CFG_FCC_PSMR 0 |
||||
#endif |
||||
#define FETH2_RST 0x01 |
||||
#elif (CONFIG_ETHER_INDEX == 3) |
||||
/* need more definitions here for FE3 */ |
||||
#define FETH3_RST 0x80 |
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications |
||||
*/ |
||||
#define MDIO_PORT 2 /* Port C */ |
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
||||
else iop->pdat &= ~0x00400000 |
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
||||
else iop->pdat &= ~0x00200000 |
||||
|
||||
#define MIIDELAY udelay(1) |
||||
#endif |
||||
|
||||
/* Environment */ |
||||
/* We use the top boot sector flash, so we have some 16K sectors for env
|
||||
* But....functions don't seem smart enough yet. |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) |
||||
#define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ |
||||
#endif |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" |
||||
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xff900000" |
||||
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) & \
|
||||
~(CFG_CMD_ENV | \
|
||||
CFG_CMD_LOADS )) |
||||
#elif defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ |
||||
CFG_CMD_MII | CFG_CMD_I2C ) & \
|
||||
~(CFG_CMD_ENV)) |
||||
#elif defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) & \
|
||||
~(CFG_CMD_ENV)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) |
||||
#elif defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ |
||||
CFG_CMD_MII | CFG_CMD_I2C) |
||||
#elif defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) |
||||
#endif |
||||
#endif |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*Note: change below for your network setting!!! */ |
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_ETHADDR 00:01:af:07:9b:8a |
||||
#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b |
||||
#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c |
||||
#endif |
||||
|
||||
#define CONFIG_SERVERIP 192.168.85.1 |
||||
#define CONFIG_IPADDR 192.168.85.60 |
||||
#define CONFIG_GATEWAYIP 192.168.85.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_HOSTNAME STX_GP3 |
||||
#define CONFIG_ROOTPATH /gppproot |
||||
#define CONFIG_BOOTFILE uImage |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue