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@ -278,6 +278,25 @@ static void dpll4_init_34xx(u32 sil_index, u32 clk_index) |
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wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); |
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} |
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static void dpll5_init_34xx(u32 sil_index, u32 clk_index) |
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{ |
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE; |
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dpll_param *ptr = (dpll_param *) get_per2_dpll_param(); |
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/* Moving it to the right sysclk base */ |
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ptr = ptr + clk_index; |
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/* PER2 DPLL (DPLL5) */ |
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sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP); |
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wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY); |
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sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */ |
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sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */ |
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sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/ |
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sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */ |
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sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */ |
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wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY); |
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} |
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static void mpu_init_34xx(u32 sil_index, u32 clk_index) |
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{ |
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE; |
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@ -587,6 +606,7 @@ void prcm_init(void) |
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dpll3_init_34xx(sil_index, clk_index); |
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dpll4_init_34xx(sil_index, clk_index); |
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dpll5_init_34xx(sil_index, clk_index); |
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iva_init_34xx(sil_index, clk_index); |
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mpu_init_34xx(sil_index, clk_index); |
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