Add support for Instituto Atlantico's ATUM8548 board Signed-off-by: robert lazarski <robertlazarski@gmail.com>master
robert lazarski
18 years ago
committed by
Andrew Fleming-AFLEMING
parent
9e3ed392d2
commit
7bd6104b71
@ -0,0 +1,147 @@ |
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/* |
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* Copyright 2007 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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.resetvec 0xFFFFFFFC : |
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{ |
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*(.resetvec) |
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} = 0xffff |
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.bootpg 0xFFFFF000 : |
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{ |
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cpu/mpc85xx/start.o (.bootpg) |
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board/atum8548/init.o (.bootpg) |
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} = 0xffff |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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cpu/mpc85xx/start.o (.text) |
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board/atum8548/init.o (.text) |
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cpu/mpc85xx/traps.o (.text) |
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cpu/mpc85xx/interrupts.o (.text) |
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cpu/mpc85xx/cpu_init.o (.text) |
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cpu/mpc85xx/cpu.o (.text) |
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cpu/mpc85xx/speed.o (.text) |
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lib_generic/crc32.o (.text) |
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lib_ppc/extable.o (.text) |
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lib_generic/zlib.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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*(.eh_frame) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,29 @@ |
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Building U-Boot |
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--------------- |
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The ATUM8548 code is known to build using ELDK 4.1. |
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$ make ATUM8548_config |
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Configuring for ATUM8548 board... |
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$ make |
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Using Flash |
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----------- |
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The ATUM8548 board has one flash bank, of 128MB in size (2^23 = 0x08000000). |
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The BDI2000 commands for copying u-boot into flash are |
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as follows: |
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erase 0xFFF80000 0x4000 0x20 |
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prog 0xfff80000 uboot.bin bin |
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Booting Linux |
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------------- |
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U-boot/kermit commands for booting linux via NFS - assumming the proper |
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bootargs are set - are as follows: |
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tftp 1000000 uImage.atum |
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tftp c00000 mpc8548atum.dtb |
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bootm 1000000 - c00000 |
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@ -0,0 +1,465 @@ |
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/*
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* Copyright 2007 |
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com |
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* |
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* Copyright 2004, 2007 Freescale Semiconductor. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* atum8548 board configuration file |
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* |
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* Please refer to doc/README.atum8548 for more info. |
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* |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/* Debug Options, Disable in production
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#define ET_DEBUG 1 |
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#define CONFIG_PANIC_HANG 1 |
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#define DEBUG 1 |
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*/ |
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/* CPLD Configuration Options */ |
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#define MPC85xx_ATUM_CLKOCR 0x80000002 |
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/* High Level Configuration Options */ |
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#define CONFIG_BOOKE 1 /* BOOKE */ |
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#define CONFIG_E500 1 /* BOOKE e500 family */ |
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
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#define CONFIG_MPC8548 1 /* MPC8548 specific */ |
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#define CONFIG_PCI 1 /* enable any pci type devices */ |
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#define CONFIG_PCI1 1 /* PCI controller 1 */ |
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
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#define CONFIG_PCI2 1 /* PCI controller 2 */ |
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
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#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ |
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#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
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#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ |
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#define CONFIG_SYS_CLK_FREQ 33000000 |
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/*
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* These can be toggled for performance analysis, otherwise use default. |
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*/ |
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#define CONFIG_L2_CACHE /* toggle L2 cache */ |
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#define CONFIG_BTB /* toggle branch predition */ |
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ |
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/*
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* Only possible on E500 Version 2 or newer cores. |
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*/ |
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#define CONFIG_ENABLE_36BIT_PHYS 1 |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
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#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ |
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#define CONFIG_ENABLE_36BIT_PHYS 1 |
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#undef CFG_DRAM_TEST |
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#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x00400000 |
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/*
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* Base addresses -- Note these are effective addresses where the |
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* actual resources get mapped (not physical addresses) |
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*/ |
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
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#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ |
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#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
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#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) |
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#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) |
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/*
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* DDR Setup |
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*/ |
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
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#if defined(CONFIG_SPD_EEPROM) |
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/*
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* Determine DDR configuration from I2C interface. |
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*/ |
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
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#else |
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/*
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* Manually set up DDR parameters |
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*/ |
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#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */ |
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#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */ |
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#define CFG_DDR_CS0_CONFIG 0x80000102 |
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#define CFG_DDR_TIMING_0 0x00260802 |
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#define CFG_DDR_TIMING_1 0x38355322 |
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#define CFG_DDR_TIMING_2 0x039048c7 |
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#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
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#define CFG_DDR_MODE 0x00000432 |
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#define CFG_DDR_INTERVAL 0x05150100 |
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#define DDR_SDRAM_CFG 0x43000000 |
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#endif |
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#undef CONFIG_CLOCKS_IN_MHZ |
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/*
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* Local Bus Definitions |
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*/ |
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/*
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* FLASH on the Local Bus |
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* based on flash chip S29GL01GP |
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* One bank, 128M, using the CFI driver. |
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* Boot from BR0 bank at 0xf800_0000 |
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* |
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* BR0: |
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* Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0 |
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* Port Size = 16 bits = BRx[19:20] = 10 |
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* Use GPCM = BRx[24:26] = 000 |
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* Valid = BRx[31] = 1 |
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* |
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* 0 4 8 12 16 20 24 28 |
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* 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0 |
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* |
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* OR0: |
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* Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0 |
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* Reserved ORx[17:18] = 00 |
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* CSNT = ORx[20] = 1 |
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* ACS = half cycle delay = ORx[21:22] = 11 |
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* SCY = 6 = ORx[24:27] = 0110 |
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* TRLX = use relaxed timing = ORx[29] = 1 |
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* EAD = use external address latch delay = OR[31] = 1 |
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* |
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* 0 4 8 12 16 20 24 28 |
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* 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx |
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*/ |
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#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */ |
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#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */ |
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#define CFG_BR0_PRELIM 0xf8001001 |
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#define CFG_OR0_PRELIM 0xf8000E65 |
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
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#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ |
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#undef CFG_FLASH_CHECKSUM |
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#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */ |
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#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */ |
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
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#define CFG_FLASH_CFI_DRIVER 1 |
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#define CFG_FLASH_CFI 1 |
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#define CFG_FLASH_EMPTY_INFO |
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/*
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* Flash on the LocalBus |
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*/ |
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#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
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/* Memory */ |
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#define CFG_INIT_RAM_LOCK 1 |
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#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
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#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
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/* Serial Port */ |
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#define CONFIG_CONS_INDEX 1 |
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#undef CONFIG_SERIAL_SOFTWARE_FIFO |
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#define CFG_NS16550 |
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#define CFG_NS16550_SERIAL |
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#define CFG_NS16550_REG_SIZE 1 |
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#define CFG_NS16550_CLK get_bus_freq(0) |
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#define CFG_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
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/* Use the HUSH parser */ |
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#define CFG_HUSH_PARSER |
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#ifdef CFG_HUSH_PARSER |
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#define CFG_PROMPT_HUSH_PS2 "> " |
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#endif |
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||||||
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/* pass open firmware flat tree */ |
||||||
|
#define CONFIG_OF_LIBFDT 1 |
||||||
|
#define CONFIG_OF_BOARD_SETUP 1 |
||||||
|
|
||||||
|
/*
|
||||||
|
* I2C |
||||||
|
*/ |
||||||
|
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||||
|
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||||
|
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||||
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||||
|
#define CFG_I2C_EEPROM_ADDR 0x57 |
||||||
|
#define CFG_I2C_SLAVE 0x7F |
||||||
|
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||||
|
#define CFG_I2C_OFFSET 0x3000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* General PCI |
||||||
|
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||||
|
*/ |
||||||
|
#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
||||||
|
|
||||||
|
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||||
|
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||||
|
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||||
|
#define CFG_PCI1_IO_BASE 0x00000000 |
||||||
|
#define CFG_PCI1_IO_PHYS 0xe2000000 |
||||||
|
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||||
|
|
||||||
|
#ifdef CONFIG_PCI2 |
||||||
|
#define CFG_PCI2_MEM_BASE 0xC0000000 |
||||||
|
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||||
|
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||||
|
#define CFG_PCI2_IO_BASE 0x00000000 |
||||||
|
#define CFG_PCI2_IO_PHYS 0xe2800000 |
||||||
|
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1 |
||||||
|
#define CFG_PCIE1_MEM_BASE 0xa0000000 |
||||||
|
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE |
||||||
|
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||||
|
#define CFG_PCIE1_IO_BASE 0x00000000 |
||||||
|
#define CFG_PCIE1_IO_PHYS 0xe3000000 |
||||||
|
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
#if !defined(CONFIG_PCI_PNP) |
||||||
|
#define PCI_ENET0_IOADDR 0xe0000000 |
||||||
|
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||||
|
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||||
|
#endif |
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) |
||||||
|
|
||||||
|
#define CONFIG_NET_MULTI |
||||||
|
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||||
|
|
||||||
|
#undef CONFIG_EEPRO100 |
||||||
|
#undef CONFIG_TULIP |
||||||
|
|
||||||
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||||
|
|
||||||
|
/* PCI view of System Memory */ |
||||||
|
#define CFG_PCI_MEMORY_BUS 0x00000000 |
||||||
|
#define CFG_PCI_MEMORY_PHYS 0x00000000 |
||||||
|
#define CFG_PCI_MEMORY_SIZE 0x80000000 |
||||||
|
|
||||||
|
#endif /* CONFIG_PCI */ |
||||||
|
|
||||||
|
#if defined(CONFIG_TSEC_ENET) |
||||||
|
|
||||||
|
#ifndef CONFIG_NET_MULTI |
||||||
|
#define CONFIG_NET_MULTI 1 |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_MII 1 /* MII PHY management */ |
||||||
|
#define CONFIG_TSEC1 1 |
||||||
|
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||||
|
#define CONFIG_TSEC2 1 |
||||||
|
#define CONFIG_TSEC2_NAME "eTSEC1" |
||||||
|
#define CONFIG_TSEC3 1 |
||||||
|
#define CONFIG_TSEC3_NAME "eTSEC2" |
||||||
|
#define CONFIG_TSEC4 1 |
||||||
|
#define CONFIG_TSEC4_NAME "eTSEC3" |
||||||
|
#undef CONFIG_MPC85XX_FEC |
||||||
|
|
||||||
|
#define TSEC1_PHY_ADDR 0 |
||||||
|
#define TSEC2_PHY_ADDR 1 |
||||||
|
#define TSEC3_PHY_ADDR 2 |
||||||
|
#define TSEC4_PHY_ADDR 3 |
||||||
|
|
||||||
|
#define TSEC1_PHYIDX 0 |
||||||
|
#define TSEC2_PHYIDX 0 |
||||||
|
#define TSEC3_PHYIDX 0 |
||||||
|
#define TSEC4_PHYIDX 0 |
||||||
|
#define TSEC1_FLAGS TSEC_GIGABIT |
||||||
|
#define TSEC2_FLAGS TSEC_GIGABIT |
||||||
|
#define TSEC3_FLAGS TSEC_GIGABIT |
||||||
|
#define TSEC4_FLAGS TSEC_GIGABIT |
||||||
|
|
||||||
|
/* Options are: eTSEC[0-3] */ |
||||||
|
#define CONFIG_ETHPRIME "eTSEC2" |
||||||
|
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||||
|
#endif /* CONFIG_TSEC_ENET */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment |
||||||
|
*/ |
||||||
|
#define CFG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||||
|
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||||
|
#define CFG_ENV_SIZE 0x2000 |
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||||
|
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options |
||||||
|
*/ |
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE |
||||||
|
#define CONFIG_BOOTP_BOOTPATH |
||||||
|
#define CONFIG_BOOTP_GATEWAY |
||||||
|
#define CONFIG_BOOTP_HOSTNAME |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration. |
||||||
|
*/ |
||||||
|
#include <config_cmd_default.h> |
||||||
|
|
||||||
|
#define CONFIG_CMD_PING |
||||||
|
#define CONFIG_CMD_I2C |
||||||
|
#define CONFIG_CMD_MII |
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) |
||||||
|
#define CONFIG_CMD_PCI |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CFG_LONGHELP /* undef to save memory */ |
||||||
|
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||||
|
#else |
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#endif |
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */ |
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data |
||||||
|
* have to be in the first 8 MB of memory, since this is |
||||||
|
* the maximum mapped by the Linux kernel during initialization. |
||||||
|
*/ |
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||||
|
|
||||||
|
/* Cache Configuration */ |
||||||
|
#define CFG_DCACHE_SIZE 32768 |
||||||
|
#define CFG_CACHELINE_SIZE 32 |
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions |
||||||
|
* |
||||||
|
* Boot Flags |
||||||
|
*/ |
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_KGDB) |
||||||
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||||
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Environment Configuration |
||||||
|
*/ |
||||||
|
|
||||||
|
/* The mac addresses for all ethernet interface */ |
||||||
|
#if defined(CONFIG_TSEC_ENET) |
||||||
|
#define CONFIG_HAS_ETH0 |
||||||
|
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
||||||
|
#define CONFIG_HAS_ETH1 |
||||||
|
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
||||||
|
#define CONFIG_HAS_ETH2 |
||||||
|
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
||||||
|
#define CONFIG_HAS_ETH3 |
||||||
|
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
||||||
|
#endif |
||||||
|
|
||||||
|
#define CONFIG_IPADDR 10.101.43.142 |
||||||
|
|
||||||
|
#define CONFIG_HOSTNAME atum |
||||||
|
#define CONFIG_ROOTPATH /nfsroot |
||||||
|
#define CONFIG_BOOTFILE /tftpboot/uImage.atum |
||||||
|
#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */ |
||||||
|
|
||||||
|
#define CONFIG_SERVERIP 10.101.43.10 |
||||||
|
#define CONFIG_GATEWAYIP 10.101.45.1 |
||||||
|
#define CONFIG_NETMASK 255.255.248.0 |
||||||
|
|
||||||
|
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||||
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
|
||||||
|
#define CONFIG_NFSBOOTCOMMAND \ |
||||||
|
"setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=$serverip:$rootpath " \
|
||||||
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $dtbaddr $dtbfile;" \
|
||||||
|
"bootm $loadaddr - $dtbaddr" |
||||||
|
|
||||||
|
|
||||||
|
#define CONFIG_RAMBOOTCOMMAND \ |
||||||
|
"setenv bootargs root=/dev/ram rw " \
|
||||||
|
"console=$consoledev,$baudrate $othbootargs;" \
|
||||||
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||||
|
"tftp $loadaddr $bootfile;" \
|
||||||
|
"tftp $dtbaddr $dtbfile;" \
|
||||||
|
"bootm $loadaddr $ramdiskaddr $dtbaddr" |
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue