From 8d17979d0359492a822a0a409d26e3a3549b4cd4 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 7 Sep 2007 17:05:36 +0200 Subject: [PATCH 1/8] [MPC512x] Correct fixup relocation Signed-off-by: Rafal Jaworowski --- board/ads5121/u-boot.lds | 1 - cpu/mpc512x/config.mk | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds index 038d849..34ceb0f 100644 --- a/board/ads5121/u-boot.lds +++ b/board/ads5121/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS { cpu/mpc512x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 8a07c5a..3259d53 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -19,7 +19,7 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e From 08e2e5fcd2e06670b62e1680a3934c0e55c72810 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 17:09:21 +0200 Subject: [PATCH 2/8] [MPC512x] Proper handling of larger frames in the FEC driver When frame larger than local RX buffer is received, it is split and handled by two buffer descriptors. Prior to this patch the FEC driver discarded contents of a buffer descriptor without the 'LAST' bit set, so the first part of the frame was lost in case of larger frames. This fix allows to safely combine the two pieces into the whole frame. Signed-off-by: Grzegorz Bernacki --- cpu/mpc512x/fec.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index 3c142a9..8104576 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -32,6 +32,9 @@ int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * re int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); +static uchar rx_buff[FEC_MAX_PKT_SIZE]; +static int rx_buff_idx = 0; + /********************************************************************/ #if (DEBUG & 0x2) static void mpc512x_fec_phydump (char *devname) @@ -235,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->op_pause = 0x00010020; /* Frame length=1518; MII mode */ - fec->eth->r_cntrl = 0x05ee000c; + fec->eth->r_cntrl = 0x05ee0024; /* Half-duplex, heartbeat disabled */ fec->eth->x_cntrl = 0x00000000; @@ -520,8 +523,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; unsigned long ievent; - int frame_length, len = 0; - uchar buff[FEC_MAX_PKT_SIZE]; + int frame_length = 0; #if (DEBUG & 0x1) printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); @@ -555,31 +557,37 @@ static int mpc512x_fec_recv (struct eth_device *dev) } if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && - !(pRbd->status & FEC_RBD_ERR) && + if (!(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { /* * Get buffer size */ - frame_length = pRbd->dataLength - 4; - + if (pRbd->status & FEC_RBD_LAST) + frame_length = pRbd->dataLength - 4; + else + frame_length = pRbd->dataLength; #if (DEBUG & 0x20) { int i; - printf ("recv data hdr:"); + printf ("recv data length 0x%08x data hdr: ", + pRbd->dataLength); for (i = 0; i < 14; i++) printf ("%x ", *((uint8*)pRbd->dataPointer + i)); printf("\n"); } #endif - /* * Fill the buffer and pass it to upper layers */ - memcpy (buff, (void*)pRbd->dataPointer, frame_length); - NetReceive ((uchar*)buff, frame_length); - len = frame_length; + memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer, + frame_length - rx_buff_idx); + rx_buff_idx = frame_length; + + if (pRbd->status & FEC_RBD_LAST) { + NetReceive ((uchar*)rx_buff, frame_length); + rx_buff_idx = 0; + } } /* @@ -590,7 +598,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) /* Try to fill Buffer Descriptors */ fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ - return len; + return frame_length; } /********************************************************************/ From ff7640c9ead8806b5d827f2b29f9cb2632add729 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 7 Sep 2007 17:43:36 +0200 Subject: [PATCH 3/8] Fix typo in MAKEALL script. Signed-off-by: Wolfgang Denk --- MAKEALL | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 68bb1ad..2597d1f 100755 --- a/MAKEALL +++ b/MAKEALL @@ -341,7 +341,7 @@ LIST_85xx=" \ LIST_86xx=" \ MPC8641HPCN \ - SBC8641D \ + sbc8641d \ " ######################################################################### From 15ee4734e4e08003d73d9ead3ca80e2a0672e427 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 17:46:18 +0200 Subject: [PATCH 4/8] [PPC440SPe] Convert machine check exceptions handling Convert using fixup mechanism to suppressing MCK for the duration of config read/write transaction: while fixups work fine with the case of a precise exception, we identified a major drawback with this approach when there's an imprecise case. In this scenario there is the following race condition: the fixup is (by design) set to catch the instruction following the one actually causing the exception; if an interrupt (e.g. decrementer) happens between those two instructions, the ISR code is executed before the fixup handler the machine check is no longer protected by the fixup handler as it appears as within the ISR code. In consequence the fixup approach is being phased out and replaced with explicit suppressing of MCK during a PCIe config read/write cycle. Signed-off-by: Grzegorz Bernacki --- cpu/ppc4xx/440spe_pcie.c | 59 ++++++++++++++++++++++++++++-------------------- cpu/ppc4xx/440spe_pcie.h | 16 ++----------- cpu/ppc4xx/traps.c | 6 ----- 3 files changed, 37 insertions(+), 44 deletions(-) diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index bf68cc1..2d0b406 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -40,31 +40,24 @@ enum { LNKW_X8 = 0x8 }; -static inline int pcie_in_8(const volatile unsigned char __iomem *addr) +static void pcie_dmer_disable(void) { - int ret; - - PCIE_IN(lbzx, ret, addr); - - return ret; -} - -static inline int pcie_in_le16(const volatile unsigned short __iomem *addr) -{ - int ret; - - PCIE_IN(lhbrx, ret, addr) - - return ret; + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); } -static inline unsigned pcie_in_le32(const volatile unsigned __iomem *addr) +static void pcie_dmer_enable(void) { - unsigned ret; - - PCIE_IN(lwbrx, ret, addr); - - return ret; + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); } @@ -81,17 +74,27 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, devfn = PCI_BDF(0,0,0); offset += devfn << 4; + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + switch (len) { case 1: - *val = pcie_in_8(hose->cfg_data + offset); + *val = in_8(hose->cfg_data + offset); break; case 2: - *val = pcie_in_le16((u16 *)(hose->cfg_data + offset)); + *val = in_le16((u16 *)(hose->cfg_data + offset)); break; default: - *val = pcie_in_le32((u32*)(hose->cfg_data + offset)); + *val = in_le32((u32*)(hose->cfg_data + offset)); break; } + + pcie_dmer_enable (); + return 0; } @@ -107,6 +110,11 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, devfn = PCI_BDF(0,0,0); offset += devfn << 4; + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + switch (len) { case 1: out_8(hose->cfg_data + offset, val); @@ -118,6 +126,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, out_le32((u32 *)(hose->cfg_data + offset), val); break; } + + pcie_dmer_enable (); + return 0; } diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index eb7cecf..38745eb 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -38,6 +38,7 @@ #define DCRN_PEGPL_REGBAL(base) (base + 0x13) #define DCRN_PEGPL_REGMSK(base) (base + 0x14) #define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) /* * System DCRs (SDRs) @@ -161,20 +162,7 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) -#define PCIE_IN(opcode, ret, addr) \ - __asm__ __volatile__( \ - "sync\n" \ - #opcode " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "isync\n" \ - "b 3f\n" \ - "2: li %0,-1\n" \ - "3:\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign 4\n" \ - ".long 1b,2b\n" \ - ".previous\n" \ - : "=r" (ret) : "r" (addr), "m" (*addr)); +#define GPL_DMER_MASK_DISA 0x02000000 int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index f5365cb..38b6f89 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -151,12 +151,6 @@ MachineCheckException(struct pt_regs *regs) int uncorr_ecc = 0; #endif - /* Probing PCI(E) using config cycles may cause this exception - * when a device is not present. To gracefully recover in such - * scenarios config read/write routines need to be instrumented in - * order to return via fixup handler. For examples refer to - * pcie_in_8(), pcie_in_le16() and pcie_in_le32() - */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; val = mfspr(MCSR); From 7f1913938984ef6c6a46cb53e003719196d9c5de Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:20:23 +0200 Subject: [PATCH 5/8] [PPC440SPe] Improve PCIe configuration space access - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/init.S | 12 ++--- board/amcc/katmai/katmai.c | 9 ++-- board/amcc/yucca/init.S | 12 ++--- board/amcc/yucca/yucca.c | 9 ++-- cpu/ppc4xx/405gp_pci.c | 17 ++++--- cpu/ppc4xx/440spe_pcie.c | 111 +++++++++++++++++++++++++++++++++++---------- include/common.h | 2 +- include/configs/katmai.h | 10 ++-- include/configs/yucca.h | 10 ++-- 9 files changed, 130 insertions(+), 62 deletions(-) diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 5202ae6..e3f3da6 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -67,9 +67,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -109,9 +109,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index b804d55..a9ae4a3 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -392,7 +392,7 @@ int katmai_pcie_card_present(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -401,7 +401,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for katmai card presence */ if (!katmai_pcie_card_present(i)) @@ -418,8 +418,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -443,6 +443,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index c92dcf7..67e8f8f 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -70,9 +70,9 @@ tlbtabA: tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) @@ -112,9 +112,9 @@ tlbtabB: tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d08fcf3..252e4fe 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port) static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; -void pcie_setup_hoses(void) +void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; @@ -855,7 +855,7 @@ void pcie_setup_hoses(void) * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ - bus = 1; + bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) @@ -874,8 +874,8 @@ void pcie_setup_hoses(void) hose = &pcie_hose[i]; hose->first_busno = bus; - hose->last_busno = bus; - bus++; + hose->last_busno = bus; + hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, @@ -899,6 +899,7 @@ void pcie_setup_hoses(void) * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; #endif } } diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 2837929..282e7a1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -443,7 +443,7 @@ void pci_init_board(void) static struct pci_controller ppc440_hose = {0}; -void pci_440_init (struct pci_controller *hose) +int pci_440_init (struct pci_controller *hose) { int reg_num = 0; @@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #elif defined(CONFIG_440GP) unsigned long strap; @@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose) if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } #endif #endif /* CONFIG_DISABLE_PISE_TEST */ @@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose) * PCI controller init *--------------------------------------------------------------------------*/ hose->first_busno = 0; - hose->last_busno = 0xff; + hose->last_busno = 0; /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, @@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose) if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); - return; + return -1; } pci_register_hose( hose ); @@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose) #endif hose->last_busno = pci_hose_scan(hose); } + return hose->last_busno; } void pci_init_board(void) { - pci_440_init (&ppc440_hose); + int busno; + + busno = pci_440_init (&ppc440_hose); #if defined(CONFIG_440SPE) - pcie_setup_hoses(); + pcie_setup_hoses(busno + 1); #endif } diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 2d0b406..158f1c5 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -40,6 +40,23 @@ enum { LNKW_X8 = 0x8 }; +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) +{ + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE) + base = (u8*)CFG_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) + base = (u8*)CFG_PCIE1_XCFGBASE; + if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) + base = (u8*)CFG_PCIE2_XCFGBASE; + } + + return base; +} + static void pcie_dmer_disable(void) { mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), @@ -60,18 +77,35 @@ static void pcie_dmer_enable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); } - static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { + u8 *address; *val = 0; + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + /* - * 440SPE implements only one function per port + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc//init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -101,13 +135,24 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 val) { + u8 *address; + /* - * 440SPE implements only one function per port + * Bus numbers are relative to hose->first_busno */ - if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * Same constraints as in pcie_read_config(). + */ + if (PCI_BUS(devfn) >= 16) return 0; - devfn = PCI_BDF(0,0,0); + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); offset += devfn << 4; /* @@ -137,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u u32 v; int rv; - rv = pcie_read_config(hose, dev, offset, 1, &v); + rv = pcie_read_config(hose, dev, offset, 1, &v); *val = (u8)v; return rv; } @@ -794,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); switch (port) { case 0: @@ -822,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - if (ppc440spe_revB()) { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - } else { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); - } + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); /* * Set up outbound translation to hose->mem_space from PLB @@ -886,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); printf("PCIE:%d successfully set as rootpoint\n",port); + + /* Set Device and Vendor Id */ + switch (port) { + case 0: + out_le16(mbase + 0x200, 0xaaa0); + out_le16(mbase + 0x202, 0xbed0); + break; + case 1: + out_le16(mbase + 0x200, 0xaaa1); + out_le16(mbase + 0x202, 0xbed1); + break; + case 2: + out_le16(mbase + 0x200, 0xaaa2); + out_le16(mbase + 0x202, 0xbed2); + break; + default: + out_le16(mbase + 0x200, 0xaaa3); + out_le16(mbase + 0x202, 0xbed3); + } + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + } int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) @@ -963,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; diff --git a/include/common.h b/include/common.h index 9a5a0ab..aca281b 100644 --- a/include/common.h +++ b/include/common.h @@ -275,7 +275,7 @@ void pciinfo (int, int); # endif int is_pci_host (struct pci_controller *); #if defined(CONFIG_440SPE) - void pcie_setup_hoses(void); + void pcie_setup_hoses(int busno); #endif #endif diff --git a/include/configs/katmai.h b/include/configs/katmai.h index b6d0f51..7834e39 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -66,11 +66,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 906f046..323535a 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -68,11 +68,11 @@ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 -#define CFG_PCIE0_XCFGBASE 0xc0000400 -#define CFG_PCIE1_CFGBASE 0xc0001000 -#define CFG_PCIE1_XCFGBASE 0xc0001400 -#define CFG_PCIE2_CFGBASE 0xc0002000 -#define CFG_PCIE2_XCFGBASE 0xc0002400 +#define CFG_PCIE1_CFGBASE 0xc1000000 +#define CFG_PCIE2_CFGBASE 0xc2000000 +#define CFG_PCIE0_XCFGBASE 0xc3000000 +#define CFG_PCIE1_XCFGBASE 0xc3001000 +#define CFG_PCIE2_XCFGBASE 0xc3002000 /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE From 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 7 Sep 2007 18:35:37 +0200 Subject: [PATCH 6/8] [PPC440SPe] PCIe environment settings for Katmai and Yucca - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki --- board/amcc/katmai/katmai.c | 12 ++++++++++++ board/amcc/yucca/yucca.c | 12 ++++++++++++ include/configs/katmai.h | 3 ++- include/configs/yucca.h | 3 ++- 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a9ae4a3..afd60ec 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -396,6 +396,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -439,6 +441,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 252e4fe..397b018 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + char *env; + unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes @@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno) */ #else ppc440spe_setup_pcie_rootpoint(hose, i); + + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul (env, NULL, 10); + if (delay > 5) + printf ("Warning, expect noticable delay before PCIe" + "scan due to 'pciscandelay' value!\n"); + mdelay (delay * 1000); + } + /* * Config access can only go down stream */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7834e39..7908e5a 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -201,6 +201,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -322,7 +323,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 323535a..74033b4 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -182,6 +182,7 @@ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "pciconfighost=1\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -297,7 +298,7 @@ #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#undef CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ From a7d7eca791a37f452c9da10fef4b31dd7aa9a622 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Fri, 7 Sep 2007 09:25:07 -0600 Subject: [PATCH 7/8] Bugfix: make bootm+libfdt compile on boards with no flash Signed-off-by: Grant Likely --- common/cmd_bootm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 9f5e0b4..6ebedfb 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -834,9 +834,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, of_flat_tree += 4 - tail; } +#ifndef CFG_NO_FLASH /* move the blob if it is in flash (set of_data to !null) */ if (addr2info ((ulong)of_flat_tree) != NULL) of_data = (ulong)of_flat_tree; +#endif #if defined(CONFIG_OF_FLAT_TREE) From 1d9e31e04911a6bb7cc66dd91132c699101c32e2 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 9 Sep 2007 21:21:33 +0200 Subject: [PATCH 8/8] Fix compile error in spc1920 config. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Markus Klotzbücher Signed-off-by: Wolfgang Denk --- include/configs/spc1920.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index b4ab9ad..2efc8f1 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -31,14 +31,9 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_MII -/* #define MII_DEBUG */ -/* #define CONFIG_FEC_ENET */ #undef CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 #define FEC_ENET -/* #define CONFIG_FEC2_PHY_NORXERR */ -/* #define CFG_DISCOVER_PHY */ -/* #define CONFIG_PHY_ADDR 0x1 */ #define CONFIG_FEC2_PHY 1 #define CONFIG_BAUDRATE 19200 @@ -100,14 +95,12 @@ #define CONFIG_CMD_ECHO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_MII -#undef CONFIG_CMD_NET - - /* * Miscellaneous configurable options */