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@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode |
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# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) |
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" |
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The above memory controller interleaving and bank interleaving can be mixed. The syntax is |
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setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1" |
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Memory controller address hashing |
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================================== |
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If the DDR controller supports address hashing, it can be enabled by hwconfig. |
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Syntax is: |
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hwconfig=fsl_ddr:addr_hash=true |
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Combination of hwconfig |
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======================= |
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Hwconfig can be combined with multiple parameters, for example, on a supported |
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platform |
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hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 |
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