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@ -157,12 +157,16 @@ const struct emif_regs emif_regs_lpddr2 = { |
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.emif_rd_wr_lvl_rmp_ctl = 0x0, |
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.emif_rd_wr_lvl_ctl = 0x0, |
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.emif_ddr_phy_ctlr_1 = 0x0E084006, |
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.emif_rd_wr_exec_thresh = 0x00000405, |
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.emif_rd_wr_exec_thresh = 0x80000405, |
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.emif_ddr_ext_phy_ctrl_1 = 0x04010040, |
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.emif_ddr_ext_phy_ctrl_2 = 0x00500050, |
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.emif_ddr_ext_phy_ctrl_3 = 0x00500050, |
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.emif_ddr_ext_phy_ctrl_4 = 0x00500050, |
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.emif_ddr_ext_phy_ctrl_5 = 0x00500050 |
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.emif_ddr_ext_phy_ctrl_5 = 0x00500050, |
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.emif_prio_class_serv_map = 0x80000001, |
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.emif_connect_id_serv_1_map = 0x80000094, |
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.emif_connect_id_serv_2_map = 0x00000000, |
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.emif_cos_config = 0x000FFFFF |
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}; |
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const u32 ext_phy_ctrl_const_base_lpddr2[] = { |
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@ -217,7 +221,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz = { |
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.emif_rd_wr_lvl_rmp_win = 0x0, |
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.emif_rd_wr_lvl_rmp_ctl = 0x0, |
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.emif_rd_wr_lvl_ctl = 0x0, |
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.emif_rd_wr_exec_thresh = 0x00000405 |
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.emif_rd_wr_exec_thresh = 0x80000405, |
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.emif_prio_class_serv_map = 0x80000001, |
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.emif_connect_id_serv_1_map = 0x80000094, |
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.emif_connect_id_serv_2_map = 0x00000000, |
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.emif_cos_config = 0x000FFFFF |
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}; |
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/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ |
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@ -236,7 +244,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_beta = { |
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.emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
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.emif_ddr_ext_phy_ctrl_4 = 0x000000B5, |
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.emif_ddr_ext_phy_ctrl_5 = 0x000000E5, |
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.emif_rd_wr_exec_thresh = 0x00000405 |
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.emif_rd_wr_exec_thresh = 0x80000405, |
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.emif_prio_class_serv_map = 0x80000001, |
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.emif_connect_id_serv_1_map = 0x80000094, |
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.emif_connect_id_serv_2_map = 0x00000000, |
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.emif_cos_config = 0x000FFFFF |
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}; |
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/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ |
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@ -255,7 +267,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = { |
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.emif_ddr_ext_phy_ctrl_3 = 0x00000091, |
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.emif_ddr_ext_phy_ctrl_4 = 0x000000B9, |
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.emif_ddr_ext_phy_ctrl_5 = 0x000000E6, |
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.emif_rd_wr_exec_thresh = 0x00000405 |
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.emif_rd_wr_exec_thresh = 0x80000405, |
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.emif_prio_class_serv_map = 0x80000001, |
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.emif_connect_id_serv_1_map = 0x80000094, |
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.emif_connect_id_serv_2_map = 0x00000000, |
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.emif_cos_config = 0x000FFFFF |
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}; |
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static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { |
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@ -277,7 +293,11 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { |
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.emif_rd_wr_lvl_rmp_win = 0x0, |
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.emif_rd_wr_lvl_rmp_ctl = 0x00000000, |
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.emif_rd_wr_lvl_ctl = 0x00000000, |
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.emif_rd_wr_exec_thresh = 0x00000000, |
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.emif_rd_wr_exec_thresh = 0x80000000, |
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.emif_prio_class_serv_map = 0x80000001, |
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.emif_connect_id_serv_1_map = 0x80000094, |
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.emif_connect_id_serv_2_map = 0x00000000, |
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.emif_cos_config = 0x000FFFFF |
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}; |
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const u32 ext_phy_ctrl_const_base_ddr3[] = { |
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@ -587,8 +607,44 @@ void sdram_init(void) |
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int board_init(void) |
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{ |
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struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; |
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u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, |
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modena_init0_bw_integer, modena_init0_watermark_0; |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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/* Clear all important bits for DSS errata that may need to be tweaked*/ |
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mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & |
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MREQPRIO_0_SAB_INIT0_MASK; |
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mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; |
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modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & |
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BW_LIMITER_BW_FRAC_MASK; |
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modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & |
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BW_LIMITER_BW_INT_MASK; |
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modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & |
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BW_LIMITER_BW_WATERMARK_MASK; |
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/* Setting MReq Priority of the DSS*/ |
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mreqprio_0 |= 0x77; |
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/*
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* Set L3 Fast Configuration Register |
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* Limiting bandwith for ARM core to 700 MBPS |
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*/ |
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modena_init0_bw_fractional |= 0x10; |
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modena_init0_bw_integer |= 0x3; |
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writel(mreqprio_0, &cdev->mreqprio_0); |
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writel(mreqprio_1, &cdev->mreqprio_1); |
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writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); |
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writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); |
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writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); |
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return 0; |
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} |
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