This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the stv0991 device tree. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>master
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Cadence QSPI controller device tree bindings |
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-------------------------------------------- |
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Required properties: |
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- compatible : should be "cadence,qspi". |
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- reg : 1.Physical base address and size of SPI registers map. |
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2. Physical base address & size of NOR Flash. |
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- clocks : Clock phandles (see clock bindings for details). |
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- sram-size : spi controller sram size. |
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- status : enable in requried dts. |
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connected flash properties |
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-------------------------- |
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- spi-max-frequency : Max supported spi frequency. |
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- page-size : Flash page size. |
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- block-size : Flash memory block size. |
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- tshsl-ns : Added delay in master reference clocks (ref_clk) for |
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the length that the master mode chip select outputs |
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are de-asserted between transactions. |
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- tsd2d-ns : Delay in master reference clocks (ref_clk) between one |
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chip select being de-activated and the activation of |
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another. |
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- tchsh-ns : Delay in master reference clocks between last bit of |
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current transaction and de-asserting the device chip |
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select (n_ss_out). |
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- tslch-ns : Delay in master reference clocks between setting |
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n_ss_out low and first bit transfer |
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