@ -30,6 +30,8 @@
# include <asm/arch/at91_rstc.h>
# include <asm/arch/gpio.h>
# include <asm/arch/io.h>
# include <lcd.h>
# include <atmel_lcdc.h>
# if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
# include <net.h>
# endif
@ -150,6 +152,65 @@ static void at91sam9261ek_dm9000_hw_init(void)
}
# endif
# ifdef CONFIG_LCD
vidinfo_t panel_info = {
vl_col : 240 ,
vl_row : 320 ,
vl_clk : 4965000 ,
vl_sync : ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED ,
vl_bpix : 3 ,
vl_tft : 1 ,
vl_hsync_len : 5 ,
vl_left_margin : 1 ,
vl_right_margin : 33 ,
vl_vsync_len : 1 ,
vl_upper_margin : 1 ,
vl_lower_margin : 0 ,
mmio : AT91SAM9261_LCDC_BASE ,
} ;
void lcd_enable ( void )
{
at91_set_gpio_value ( AT91_PIN_PA12 , 0 ) ; /* power up */
}
void lcd_disable ( void )
{
at91_set_gpio_value ( AT91_PIN_PA12 , 1 ) ; /* power down */
}
static void at91sam9261ek_lcd_hw_init ( void )
{
at91_set_A_periph ( AT91_PIN_PB1 , 0 ) ; /* LCDHSYNC */
at91_set_A_periph ( AT91_PIN_PB2 , 0 ) ; /* LCDDOTCK */
at91_set_A_periph ( AT91_PIN_PB3 , 0 ) ; /* LCDDEN */
at91_set_A_periph ( AT91_PIN_PB4 , 0 ) ; /* LCDCC */
at91_set_A_periph ( AT91_PIN_PB7 , 0 ) ; /* LCDD2 */
at91_set_A_periph ( AT91_PIN_PB8 , 0 ) ; /* LCDD3 */
at91_set_A_periph ( AT91_PIN_PB9 , 0 ) ; /* LCDD4 */
at91_set_A_periph ( AT91_PIN_PB10 , 0 ) ; /* LCDD5 */
at91_set_A_periph ( AT91_PIN_PB11 , 0 ) ; /* LCDD6 */
at91_set_A_periph ( AT91_PIN_PB12 , 0 ) ; /* LCDD7 */
at91_set_A_periph ( AT91_PIN_PB15 , 0 ) ; /* LCDD10 */
at91_set_A_periph ( AT91_PIN_PB16 , 0 ) ; /* LCDD11 */
at91_set_A_periph ( AT91_PIN_PB17 , 0 ) ; /* LCDD12 */
at91_set_A_periph ( AT91_PIN_PB18 , 0 ) ; /* LCDD13 */
at91_set_A_periph ( AT91_PIN_PB19 , 0 ) ; /* LCDD14 */
at91_set_A_periph ( AT91_PIN_PB20 , 0 ) ; /* LCDD15 */
at91_set_B_periph ( AT91_PIN_PB23 , 0 ) ; /* LCDD18 */
at91_set_B_periph ( AT91_PIN_PB24 , 0 ) ; /* LCDD19 */
at91_set_B_periph ( AT91_PIN_PB25 , 0 ) ; /* LCDD20 */
at91_set_B_periph ( AT91_PIN_PB26 , 0 ) ; /* LCDD21 */
at91_set_B_periph ( AT91_PIN_PB27 , 0 ) ; /* LCDD22 */
at91_set_B_periph ( AT91_PIN_PB28 , 0 ) ; /* LCDD23 */
at91_sys_write ( AT91_PMC_SCER , AT91_PMC_HCK1 ) ;
gd - > fb_base = AT91SAM9261_SRAM_BASE ;
}
# endif
int board_init ( void )
{
/* Enable Ctrlc */
@ -170,6 +231,9 @@ int board_init(void)
# ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init ( ) ;
# endif
# ifdef CONFIG_LCD
at91sam9261ek_lcd_hw_init ( ) ;
# endif
return 0 ;
}