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@ -1,18 +1,16 @@ |
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/*
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* Freescale Three Speed Ethernet Controller driver |
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* |
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* This software may be used and distributed according to the |
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* terms of the GNU Public License, Version 2, incorporated |
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* herein by reference. |
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* |
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* Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. |
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* (C) Copyright 2003, Motorola, Inc. |
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* author Andy Fleming |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <dm.h> |
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#include <malloc.h> |
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#include <net.h> |
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#include <command.h> |
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@ -24,21 +22,7 @@ |
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DECLARE_GLOBAL_DATA_PTR; |
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#define TX_BUF_CNT 2 |
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static uint rx_idx; /* index of the current RX buffer */ |
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static uint tx_idx; /* index of the current TX buffer */ |
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#ifdef __GNUC__ |
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static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); |
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static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); |
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#else |
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#error "rtx must be 64-bit aligned" |
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#endif |
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static int tsec_send(struct eth_device *dev, void *packet, int length); |
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#ifndef CONFIG_DM_ETH |
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/* Default initializations for TSEC controllers. */ |
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static struct tsec_info_struct tsec_info[] = { |
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@ -64,6 +48,7 @@ static struct tsec_info_struct tsec_info[] = { |
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STD_TSEC_INFO(4), /* TSEC4 */ |
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#endif |
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}; |
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#endif /* CONFIG_DM_ETH */ |
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#define TBIANA_SETTINGS ( \ |
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TBIANA_ASYMMETRIC_PAUSE \
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@ -84,8 +69,10 @@ static struct tsec_info_struct tsec_info[] = { |
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/* Configure the TBI for SGMII operation */ |
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static void tsec_configure_serdes(struct tsec_private *priv) |
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{ |
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/* Access TBI PHY registers at given TSEC register offset as opposed
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* to the register offset used for external PHY accesses */ |
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/*
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* Access TBI PHY registers at given TSEC register offset as opposed |
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* to the register offset used for external PHY accesses |
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*/ |
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), |
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0, TBI_ANA, TBIANA_SETTINGS); |
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tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), |
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@ -100,7 +87,8 @@ static void tsec_configure_serdes(struct tsec_private *priv) |
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/* Set the appropriate hash bit for the given addr */ |
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/* The algorithm works like so:
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/*
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* The algorithm works like so: |
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* 1) Take the Destination Address (ie the multicast address), and |
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* do a CRC on it (little endian), and reverse the bits of the |
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* result. |
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@ -111,9 +99,13 @@ static void tsec_configure_serdes(struct tsec_private *priv) |
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* hash index which gaddr register to use, and the 5 other bits |
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* indicate which bit (assuming an IBM numbering scheme, which |
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* for PowerPC (tm) is usually the case) in the register holds |
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* the entry. */ |
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static int |
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tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) |
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* the entry. |
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*/ |
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#ifndef CONFIG_DM_ETH |
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static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) |
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#else |
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static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set) |
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#endif |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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@ -135,7 +127,8 @@ tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) |
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} |
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#endif /* Multicast TFTP ? */ |
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/* Initialized required registers to appropriate values, zeroing
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/*
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* Initialized required registers to appropriate values, zeroing |
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* those we don't care about (unless zero is bad, in which case, |
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* choose a more appropriate value) |
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*/ |
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@ -181,7 +174,8 @@ static void init_registers(struct tsec __iomem *regs) |
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} |
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/* Configure maccfg2 based on negotiated speed and duplex
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/*
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* Configure maccfg2 based on negotiated speed and duplex |
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* reported by PHY handling code |
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*/ |
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static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) |
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@ -212,7 +206,8 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) |
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case 10: |
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maccfg2 |= MACCFG2_MII; |
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/* Set R100 bit in all modes although
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/*
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* Set R100 bit in all modes although |
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* it is only used in RGMII mode |
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*/ |
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if (phydev->speed == 100) |
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@ -231,15 +226,174 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) |
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); |
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} |
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/*
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* This returns the status bits of the device. The return value |
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* is never checked, and this is what the 8260 driver did, so we |
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* do the same. Presumably, this would be zero if there were no |
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* errors |
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*/ |
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#ifndef CONFIG_DM_ETH |
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static int tsec_send(struct eth_device *dev, void *packet, int length) |
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#else |
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static int tsec_send(struct udevice *dev, void *packet, int length) |
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#endif |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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uint16_t status; |
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int result = 0; |
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int i; |
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/* Find an empty buffer descriptor */ |
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for (i = 0; |
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; |
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i++) { |
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if (i >= TOUT_LOOP) { |
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debug("%s: tsec: tx buffers full\n", dev->name); |
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return result; |
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} |
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} |
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out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet); |
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out_be16(&priv->txbd[priv->tx_idx].length, length); |
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status = in_be16(&priv->txbd[priv->tx_idx].status); |
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out_be16(&priv->txbd[priv->tx_idx].status, status | |
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(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); |
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/* Tell the DMA to go */ |
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out_be32(®s->tstat, TSTAT_CLEAR_THALT); |
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/* Wait for buffer to be transmitted */ |
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for (i = 0; |
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in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY; |
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i++) { |
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if (i >= TOUT_LOOP) { |
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debug("%s: tsec: tx error\n", dev->name); |
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return result; |
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} |
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} |
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priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT; |
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result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS; |
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return result; |
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} |
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#ifndef CONFIG_DM_ETH |
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static int tsec_recv(struct eth_device *dev) |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { |
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int length = in_be16(&priv->rxbd[priv->rx_idx].length); |
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uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status); |
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uchar *packet = net_rx_packets[priv->rx_idx]; |
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/* Send the packet up if there were no errors */ |
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if (!(status & RXBD_STATS)) |
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net_process_received_packet(packet, length - 4); |
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else |
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printf("Got error %x\n", (status & RXBD_STATS)); |
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out_be16(&priv->rxbd[priv->rx_idx].length, 0); |
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status = RXBD_EMPTY; |
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/* Set the wrap bit if this is the last element in the list */ |
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if ((priv->rx_idx + 1) == PKTBUFSRX) |
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status |= RXBD_WRAP; |
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out_be16(&priv->rxbd[priv->rx_idx].status, status); |
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; |
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} |
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if (in_be32(®s->ievent) & IEVENT_BSY) { |
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out_be32(®s->ievent, IEVENT_BSY); |
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
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} |
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return -1; |
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} |
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#else |
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static int tsec_recv(struct udevice *dev, int flags, uchar **packetp) |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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int ret = -1; |
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if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { |
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int length = in_be16(&priv->rxbd[priv->rx_idx].length); |
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uint16_t status = in_be16(&priv->rxbd[priv->rx_idx].status); |
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uint32_t buf; |
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/* Send the packet up if there were no errors */ |
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if (!(status & RXBD_STATS)) { |
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buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr); |
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*packetp = (uchar *)buf; |
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ret = length - 4; |
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} else { |
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printf("Got error %x\n", (status & RXBD_STATS)); |
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} |
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} |
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if (in_be32(®s->ievent) & IEVENT_BSY) { |
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out_be32(®s->ievent, IEVENT_BSY); |
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out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
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} |
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return ret; |
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} |
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static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length) |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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uint16_t status; |
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out_be16(&priv->rxbd[priv->rx_idx].length, 0); |
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status = RXBD_EMPTY; |
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/* Set the wrap bit if this is the last element in the list */ |
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if ((priv->rx_idx + 1) == PKTBUFSRX) |
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status |= RXBD_WRAP; |
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out_be16(&priv->rxbd[priv->rx_idx].status, status); |
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priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; |
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return 0; |
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} |
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#endif |
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/* Stop the interface */ |
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#ifndef CONFIG_DM_ETH |
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static void tsec_halt(struct eth_device *dev) |
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#else |
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static void tsec_halt(struct udevice *dev) |
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#endif |
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{ |
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struct tsec_private *priv = (struct tsec_private *)dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
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setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
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while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) |
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!= (IEVENT_GRSC | IEVENT_GTSC)) |
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; |
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clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); |
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/* Shut down the PHY, as needed */ |
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phy_shutdown(priv->phydev); |
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} |
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
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/*
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* When MACCFG1[Rx_EN] is enabled during system boot as part |
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* of the eTSEC port initialization sequence, |
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* the eTSEC Rx logic may not be properly initialized. |
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*/ |
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void redundant_init(struct eth_device *dev) |
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void redundant_init(struct tsec_private *priv) |
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{ |
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struct tsec_private *priv = dev->priv; |
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struct tsec __iomem *regs = priv->regs; |
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uint t, count = 0; |
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int fail = 1; |
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@ -274,25 +428,27 @@ void redundant_init(struct eth_device *dev) |
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do { |
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uint16_t status; |
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tsec_send(dev, (void *)pkt, sizeof(pkt)); |
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tsec_send(priv->dev, (void *)pkt, sizeof(pkt)); |
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/* Wait for buffer to be received */ |
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for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { |
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for (t = 0; |
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in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY; |
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t++) { |
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if (t >= 10 * TOUT_LOOP) { |
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printf("%s: tsec: rx error\n", dev->name); |
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printf("%s: tsec: rx error\n", priv->dev->name); |
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break; |
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} |
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} |
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if (!memcmp(pkt, (void *)net_rx_packets[rx_idx], sizeof(pkt))) |
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if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt))) |
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fail = 0; |
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out_be16(&rxbd[rx_idx].length, 0); |
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out_be16(&priv->rxbd[priv->rx_idx].length, 0); |
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status = RXBD_EMPTY; |
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if ((rx_idx + 1) == PKTBUFSRX) |
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if ((priv->rx_idx + 1) == PKTBUFSRX) |
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status |= RXBD_WRAP; |
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out_be16(&rxbd[rx_idx].status, status); |
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rx_idx = (rx_idx + 1) % PKTBUFSRX; |
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out_be16(&priv->rxbd[priv->rx_idx].status, status); |
|
|
|
|
priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; |
|
|
|
|
|
|
|
|
|
if (in_be32(®s->ievent) & IEVENT_BSY) { |
|
|
|
|
out_be32(®s->ievent, IEVENT_BSY); |
|
|
|
@ -315,49 +471,49 @@ void redundant_init(struct eth_device *dev) |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
/* Set up the buffers and their descriptors, and bring up the
|
|
|
|
|
/*
|
|
|
|
|
* Set up the buffers and their descriptors, and bring up the |
|
|
|
|
* interface |
|
|
|
|
*/ |
|
|
|
|
static void startup_tsec(struct eth_device *dev) |
|
|
|
|
static void startup_tsec(struct tsec_private *priv) |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
uint16_t status; |
|
|
|
|
int i; |
|
|
|
|
|
|
|
|
|
/* reset the indices to zero */ |
|
|
|
|
rx_idx = 0; |
|
|
|
|
tx_idx = 0; |
|
|
|
|
priv->rx_idx = 0; |
|
|
|
|
priv->tx_idx = 0; |
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
|
|
|
|
uint svr; |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
/* Point to the buffer descriptors */ |
|
|
|
|
out_be32(®s->tbase, (u32)&txbd[0]); |
|
|
|
|
out_be32(®s->rbase, (u32)&rxbd[0]); |
|
|
|
|
out_be32(®s->tbase, (u32)&priv->txbd[0]); |
|
|
|
|
out_be32(®s->rbase, (u32)&priv->rxbd[0]); |
|
|
|
|
|
|
|
|
|
/* Initialize the Rx Buffer descriptors */ |
|
|
|
|
for (i = 0; i < PKTBUFSRX; i++) { |
|
|
|
|
out_be16(&rxbd[i].status, RXBD_EMPTY); |
|
|
|
|
out_be16(&rxbd[i].length, 0); |
|
|
|
|
out_be32(&rxbd[i].bufptr, (u32)net_rx_packets[i]); |
|
|
|
|
out_be16(&priv->rxbd[i].status, RXBD_EMPTY); |
|
|
|
|
out_be16(&priv->rxbd[i].length, 0); |
|
|
|
|
out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]); |
|
|
|
|
} |
|
|
|
|
status = in_be16(&rxbd[PKTBUFSRX - 1].status); |
|
|
|
|
out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); |
|
|
|
|
status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status); |
|
|
|
|
out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); |
|
|
|
|
|
|
|
|
|
/* Initialize the TX Buffer Descriptors */ |
|
|
|
|
for (i = 0; i < TX_BUF_CNT; i++) { |
|
|
|
|
out_be16(&txbd[i].status, 0); |
|
|
|
|
out_be16(&txbd[i].length, 0); |
|
|
|
|
out_be32(&txbd[i].bufptr, 0); |
|
|
|
|
out_be16(&priv->txbd[i].status, 0); |
|
|
|
|
out_be16(&priv->txbd[i].length, 0); |
|
|
|
|
out_be32(&priv->txbd[i].bufptr, 0); |
|
|
|
|
} |
|
|
|
|
status = in_be16(&txbd[TX_BUF_CNT - 1].status); |
|
|
|
|
out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); |
|
|
|
|
status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status); |
|
|
|
|
out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 |
|
|
|
|
svr = get_svr(); |
|
|
|
|
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) |
|
|
|
|
redundant_init(dev); |
|
|
|
|
redundant_init(priv); |
|
|
|
|
#endif |
|
|
|
|
/* Enable Transmit and Receive */ |
|
|
|
|
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); |
|
|
|
@ -369,113 +525,22 @@ static void startup_tsec(struct eth_device *dev) |
|
|
|
|
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* This returns the status bits of the device. The return value
|
|
|
|
|
* is never checked, and this is what the 8260 driver did, so we |
|
|
|
|
* do the same. Presumably, this would be zero if there were no |
|
|
|
|
* errors |
|
|
|
|
*/ |
|
|
|
|
static int tsec_send(struct eth_device *dev, void *packet, int length) |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
uint16_t status; |
|
|
|
|
int result = 0; |
|
|
|
|
int i; |
|
|
|
|
|
|
|
|
|
/* Find an empty buffer descriptor */ |
|
|
|
|
for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { |
|
|
|
|
if (i >= TOUT_LOOP) { |
|
|
|
|
debug("%s: tsec: tx buffers full\n", dev->name); |
|
|
|
|
return result; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
out_be32(&txbd[tx_idx].bufptr, (u32)packet); |
|
|
|
|
out_be16(&txbd[tx_idx].length, length); |
|
|
|
|
status = in_be16(&txbd[tx_idx].status); |
|
|
|
|
out_be16(&txbd[tx_idx].status, status | |
|
|
|
|
(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); |
|
|
|
|
|
|
|
|
|
/* Tell the DMA to go */ |
|
|
|
|
out_be32(®s->tstat, TSTAT_CLEAR_THALT); |
|
|
|
|
|
|
|
|
|
/* Wait for buffer to be transmitted */ |
|
|
|
|
for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { |
|
|
|
|
if (i >= TOUT_LOOP) { |
|
|
|
|
debug("%s: tsec: tx error\n", dev->name); |
|
|
|
|
return result; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
tx_idx = (tx_idx + 1) % TX_BUF_CNT; |
|
|
|
|
result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; |
|
|
|
|
|
|
|
|
|
return result; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int tsec_recv(struct eth_device *dev) |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
|
|
|
|
|
while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { |
|
|
|
|
int length = in_be16(&rxbd[rx_idx].length); |
|
|
|
|
uint16_t status = in_be16(&rxbd[rx_idx].status); |
|
|
|
|
|
|
|
|
|
/* Send the packet up if there were no errors */ |
|
|
|
|
if (!(status & RXBD_STATS)) |
|
|
|
|
net_process_received_packet(net_rx_packets[rx_idx], |
|
|
|
|
length - 4); |
|
|
|
|
else |
|
|
|
|
printf("Got error %x\n", (status & RXBD_STATS)); |
|
|
|
|
|
|
|
|
|
out_be16(&rxbd[rx_idx].length, 0); |
|
|
|
|
|
|
|
|
|
status = RXBD_EMPTY; |
|
|
|
|
/* Set the wrap bit if this is the last element in the list */ |
|
|
|
|
if ((rx_idx + 1) == PKTBUFSRX) |
|
|
|
|
status |= RXBD_WRAP; |
|
|
|
|
out_be16(&rxbd[rx_idx].status, status); |
|
|
|
|
|
|
|
|
|
rx_idx = (rx_idx + 1) % PKTBUFSRX; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (in_be32(®s->ievent) & IEVENT_BSY) { |
|
|
|
|
out_be32(®s->ievent, IEVENT_BSY); |
|
|
|
|
out_be32(®s->rstat, RSTAT_CLEAR_RHALT); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
return -1; |
|
|
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Stop the interface */ |
|
|
|
|
static void tsec_halt(struct eth_device *dev) |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
|
|
|
|
|
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
|
|
|
|
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); |
|
|
|
|
|
|
|
|
|
while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) |
|
|
|
|
!= (IEVENT_GRSC | IEVENT_GTSC)) |
|
|
|
|
; |
|
|
|
|
|
|
|
|
|
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN); |
|
|
|
|
|
|
|
|
|
/* Shut down the PHY, as needed */ |
|
|
|
|
phy_shutdown(priv->phydev); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Initializes data structures and registers for the controller,
|
|
|
|
|
* and brings the interface up. Returns the link status, meaning |
|
|
|
|
/*
|
|
|
|
|
* Initializes data structures and registers for the controller, |
|
|
|
|
* and brings the interface up. Returns the link status, meaning |
|
|
|
|
* that it returns success if the link is up, failure otherwise. |
|
|
|
|
* This allows u-boot to find the first active controller. |
|
|
|
|
* This allows U-Boot to find the first active controller. |
|
|
|
|
*/ |
|
|
|
|
#ifndef CONFIG_DM_ETH |
|
|
|
|
static int tsec_init(struct eth_device *dev, bd_t * bd) |
|
|
|
|
#else |
|
|
|
|
static int tsec_init(struct udevice *dev) |
|
|
|
|
#endif |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
#ifdef CONFIG_DM_ETH |
|
|
|
|
struct eth_pdata *pdata = dev_get_platdata(dev); |
|
|
|
|
#endif |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
u32 tempval; |
|
|
|
|
int ret; |
|
|
|
@ -489,17 +554,27 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) |
|
|
|
|
/* Init ECNTRL */ |
|
|
|
|
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
|
|
|
|
|
|
|
|
|
/* Copy the station address into the address registers.
|
|
|
|
|
/*
|
|
|
|
|
* Copy the station address into the address registers. |
|
|
|
|
* For a station address of 0x12345678ABCD in transmission |
|
|
|
|
* order (BE), MACnADDR1 is set to 0xCDAB7856 and |
|
|
|
|
* MACnADDR2 is set to 0x34120000. |
|
|
|
|
*/ |
|
|
|
|
#ifndef CONFIG_DM_ETH |
|
|
|
|
tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | |
|
|
|
|
(dev->enetaddr[3] << 8) | dev->enetaddr[2]; |
|
|
|
|
#else |
|
|
|
|
tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) | |
|
|
|
|
(pdata->enetaddr[3] << 8) | pdata->enetaddr[2]; |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
out_be32(®s->macstnaddr1, tempval); |
|
|
|
|
|
|
|
|
|
#ifndef CONFIG_DM_ETH |
|
|
|
|
tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); |
|
|
|
|
#else |
|
|
|
|
tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16); |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
out_be32(®s->macstnaddr2, tempval); |
|
|
|
|
|
|
|
|
@ -507,7 +582,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) |
|
|
|
|
init_registers(regs); |
|
|
|
|
|
|
|
|
|
/* Ready the device for tx/rx */ |
|
|
|
|
startup_tsec(dev); |
|
|
|
|
startup_tsec(priv); |
|
|
|
|
|
|
|
|
|
/* Start up the PHY */ |
|
|
|
|
ret = phy_startup(priv->phydev); |
|
|
|
@ -551,8 +626,8 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv) |
|
|
|
|
* be set by the platform code. |
|
|
|
|
*/ |
|
|
|
|
if ((interface == PHY_INTERFACE_MODE_RGMII_ID) || |
|
|
|
|
(interface == PHY_INTERFACE_MODE_RGMII_TXID) || |
|
|
|
|
(interface == PHY_INTERFACE_MODE_RGMII_RXID)) |
|
|
|
|
(interface == PHY_INTERFACE_MODE_RGMII_TXID) || |
|
|
|
|
(interface == PHY_INTERFACE_MODE_RGMII_RXID)) |
|
|
|
|
return interface; |
|
|
|
|
|
|
|
|
|
return PHY_INTERFACE_MODE_RGMII; |
|
|
|
@ -565,14 +640,13 @@ static phy_interface_t tsec_get_interface(struct tsec_private *priv) |
|
|
|
|
return PHY_INTERFACE_MODE_MII; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Discover which PHY is attached to the device, and configure it
|
|
|
|
|
/*
|
|
|
|
|
* Discover which PHY is attached to the device, and configure it |
|
|
|
|
* properly. If the PHY is not recognized, then return 0 |
|
|
|
|
* (failure). Otherwise, return 1 |
|
|
|
|
*/ |
|
|
|
|
static int init_phy(struct eth_device *dev) |
|
|
|
|
static int init_phy(struct tsec_private *priv) |
|
|
|
|
{ |
|
|
|
|
struct tsec_private *priv = (struct tsec_private *)dev->priv; |
|
|
|
|
struct phy_device *phydev; |
|
|
|
|
struct tsec __iomem *regs = priv->regs; |
|
|
|
|
u32 supported = (SUPPORTED_10baseT_Half | |
|
|
|
@ -584,14 +658,15 @@ static int init_phy(struct eth_device *dev) |
|
|
|
|
supported |= SUPPORTED_1000baseT_Full; |
|
|
|
|
|
|
|
|
|
/* Assign a Physical address to the TBI */ |
|
|
|
|
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); |
|
|
|
|
out_be32(®s->tbipa, priv->tbiaddr); |
|
|
|
|
|
|
|
|
|
priv->interface = tsec_get_interface(priv); |
|
|
|
|
|
|
|
|
|
if (priv->interface == PHY_INTERFACE_MODE_SGMII) |
|
|
|
|
tsec_configure_serdes(priv); |
|
|
|
|
|
|
|
|
|
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); |
|
|
|
|
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, |
|
|
|
|
priv->interface); |
|
|
|
|
if (!phydev) |
|
|
|
|
return 0; |
|
|
|
|
|
|
|
|
@ -605,7 +680,9 @@ static int init_phy(struct eth_device *dev) |
|
|
|
|
return 1; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Initialize device structure. Returns success if PHY
|
|
|
|
|
#ifndef CONFIG_DM_ETH |
|
|
|
|
/*
|
|
|
|
|
* Initialize device structure. Returns success if PHY |
|
|
|
|
* initialization succeeded (i.e. if it recognizes the PHY) |
|
|
|
|
*/ |
|
|
|
|
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) |
|
|
|
@ -630,11 +707,13 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) |
|
|
|
|
priv->phyregs_sgmii = tsec_info->miiregs_sgmii; |
|
|
|
|
|
|
|
|
|
priv->phyaddr = tsec_info->phyaddr; |
|
|
|
|
priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; |
|
|
|
|
priv->flags = tsec_info->flags; |
|
|
|
|
|
|
|
|
|
strcpy(dev->name, tsec_info->devname); |
|
|
|
|
priv->interface = tsec_info->interface; |
|
|
|
|
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); |
|
|
|
|
priv->dev = dev; |
|
|
|
|
dev->iobase = 0; |
|
|
|
|
dev->priv = priv; |
|
|
|
|
dev->init = tsec_init; |
|
|
|
@ -645,7 +724,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) |
|
|
|
|
dev->mcast = tsec_mcast_addr; |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
/* Tell u-boot to get the addr from the env */ |
|
|
|
|
/* Tell U-Boot to get the addr from the env */ |
|
|
|
|
for (i = 0; i < 6; i++) |
|
|
|
|
dev->enetaddr[i] = 0; |
|
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@ -657,7 +736,7 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) |
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clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); |
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/* Try to initialize PHY here, and return */ |
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return init_phy(dev); |
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return init_phy(priv); |
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} |
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/*
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@ -690,3 +769,118 @@ int tsec_standard_init(bd_t *bis) |
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return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); |
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} |
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#else /* CONFIG_DM_ETH */ |
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int tsec_probe(struct udevice *dev) |
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{ |
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struct tsec_private *priv = dev_get_priv(dev); |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct fsl_pq_mdio_info mdio_info; |
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int offset = 0; |
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int reg; |
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const char *phy_mode; |
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int ret; |
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pdata->iobase = (phys_addr_t)dev_get_addr(dev); |
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priv->regs = (struct tsec *)pdata->iobase; |
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offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
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"phy-handle"); |
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if (offset > 0) { |
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reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); |
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priv->phyaddr = reg; |
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} else { |
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debug("phy-handle does not exist under tsec %s\n", dev->name); |
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return -ENOENT; |
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} |
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offset = fdt_parent_offset(gd->fdt_blob, offset); |
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if (offset > 0) { |
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reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0); |
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priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520); |
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} else { |
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debug("No parent node for PHY?\n"); |
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return -ENOENT; |
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} |
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offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
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"tbi-handle"); |
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if (offset > 0) { |
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reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", |
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CONFIG_SYS_TBIPA_VALUE); |
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priv->tbiaddr = reg; |
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} else { |
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priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; |
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} |
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phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, |
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"phy-connection-type", NULL); |
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if (phy_mode) |
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pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
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if (pdata->phy_interface == -1) { |
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debug("Invalid PHY interface '%s'\n", phy_mode); |
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return -EINVAL; |
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} |
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priv->interface = pdata->phy_interface; |
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/* Initialize flags */ |
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priv->flags = TSEC_GIGABIT; |
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if (priv->interface == PHY_INTERFACE_MODE_SGMII) |
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priv->flags |= TSEC_SGMII; |
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mdio_info.regs = priv->phyregs_sgmii; |
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mdio_info.name = (char *)dev->name; |
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ret = fsl_pq_mdio_init(NULL, &mdio_info); |
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if (ret) |
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return ret; |
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/* Reset the MAC */ |
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setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); |
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udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ |
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clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); |
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priv->dev = dev; |
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priv->bus = miiphy_get_dev_by_name(dev->name); |
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/* Try to initialize PHY here, and return */ |
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return !init_phy(priv); |
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} |
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int tsec_remove(struct udevice *dev) |
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{ |
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struct tsec_private *priv = dev->priv; |
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free(priv->phydev); |
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mdio_unregister(priv->bus); |
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mdio_free(priv->bus); |
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return 0; |
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} |
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static const struct eth_ops tsec_ops = { |
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.start = tsec_init, |
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.send = tsec_send, |
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.recv = tsec_recv, |
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.free_pkt = tsec_free_pkt, |
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.stop = tsec_halt, |
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#ifdef CONFIG_MCAST_TFTP |
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.mcast = tsec_mcast_addr, |
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#endif |
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}; |
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static const struct udevice_id tsec_ids[] = { |
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{ .compatible = "fsl,tsec" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(eth_tsec) = { |
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.name = "tsec", |
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.id = UCLASS_ETH, |
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.of_match = tsec_ids, |
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.probe = tsec_probe, |
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.remove = tsec_remove, |
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.ops = &tsec_ops, |
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.priv_auto_alloc_size = sizeof(struct tsec_private), |
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.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
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.flags = DM_FLAG_ALLOC_PRIV_DMA, |
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}; |
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#endif /* CONFIG_DM_ETH */ |
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