Tom Rini
11 years ago
commit
8401bfa91e
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/*
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* (C) Copyright 2013 Altera Corporation <www.altera.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _SOCFPGA_DWMMC_H_ |
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#define _SOCFPGA_DWMMC_H_ |
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extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); |
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#endif /* _SOCFPGA_SDMMC_H_ */ |
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@ -0,0 +1,53 @@ |
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-------------------------------------------- |
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SOCFPGA Documentation for U-Boot and SPL |
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-------------------------------------------- |
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This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore |
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based SOCFPGA. To know more about the hardware itself, please refer to |
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www.altera.com. |
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-------------------------------------------- |
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socfpga_dw_mmc |
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-------------------------------------------- |
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Here are macro and detailed configuration required to enable DesignWare SDMMC |
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controller support within SOCFPGA |
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#define CONFIG_MMC |
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-> To enable the SD MMC framework support |
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#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) |
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-> The base address of CSR register for DesignWare SDMMC controller |
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#define CONFIG_GENERIC_MMC |
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-> Enable the generic MMC driver |
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
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-> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM |
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#define CONFIG_DWMMC |
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-> Enable the common DesignWare SDMMC controller framework |
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#define CONFIG_SOCFPGA_DWMMC |
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-> Enable the SOCFPGA specific driver for DesignWare SDMMC controller |
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#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 |
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-> The FIFO depth for SOCFPGA DesignWare SDMMC controller |
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#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 |
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-> Phase-shifted clock of sdmmc_clk for controller to drive command and data to |
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the card to meet hold time requirements. SD clock is running at 50MHz and |
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drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time |
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is 135 / 360 * 20ns = 7.5ns. |
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#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 |
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-> Phase-shifted clock of sdmmc_clk used to sample the command and data from |
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the card |
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#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 |
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-> Bus width of data line which either 1, 4 or 8 and based on board routing. |
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#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 |
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-> The clock rate to controller. Do note the controller have a wrapper which |
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divide the clock from PLL by 4. |
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@ -0,0 +1,68 @@ |
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/*
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* (C) Copyright 2013 Altera Corporation <www.altera.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <dwmmc.h> |
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#include <asm/arch/dwmmc.h> |
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#include <asm/arch/clock_manager.h> |
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#include <asm/arch/system_manager.h> |
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static const struct socfpga_clock_manager *clock_manager_base = |
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(void *)SOCFPGA_CLKMGR_ADDRESS; |
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static const struct socfpga_system_manager *system_manager_base = |
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(void *)SOCFPGA_SYSMGR_ADDRESS; |
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static char *SOCFPGA_NAME = "SOCFPGA DWMMC"; |
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static void socfpga_dwmci_clksel(struct dwmci_host *host) |
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{ |
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unsigned int drvsel; |
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unsigned int smplsel; |
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/* Disable SDMMC clock. */ |
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clrbits_le32(&clock_manager_base->per_pll_en, |
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); |
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/* Configures drv_sel and smpl_sel */ |
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drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL; |
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smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL; |
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debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel); |
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writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel), |
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&system_manager_base->sdmmcgrp_ctrl); |
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debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, |
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readl(&system_manager_base->sdmmcgrp_ctrl)); |
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/* Enable SDMMC clock */ |
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setbits_le32(&clock_manager_base->per_pll_en, |
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); |
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} |
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int socfpga_dwmmc_init(u32 regbase, int bus_width, int index) |
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{ |
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struct dwmci_host *host = NULL; |
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host = calloc(sizeof(struct dwmci_host), 1); |
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if (!host) { |
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printf("dwmci_host calloc fail!\n"); |
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return -1; |
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} |
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host->name = SOCFPGA_NAME; |
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host->ioaddr = (void *)regbase; |
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host->buswidth = bus_width; |
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host->clksel = socfpga_dwmci_clksel; |
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host->dev_index = index; |
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/* fixed clock divide by 4 which due to the SDMMC wrapper */ |
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host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ; |
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host->fifoth_val = MSIZE(0x2) | |
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RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) | |
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TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2); |
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return add_dwmci(host, host->bus_hz, 400000); |
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} |
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