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@ -44,16 +44,7 @@ |
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#include "cpu.h" |
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#include <asm/arch/anomaly.h> |
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#include <asm/cplb.h> |
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#ifdef DEBUG |
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#define pr_debug(fmt,arg...) printf(fmt,##arg) |
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#else |
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static inline int |
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__attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...) |
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{ |
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return 0; |
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} |
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#endif |
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#include <asm/io.h> |
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void init_IRQ(void) |
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{ |
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@ -83,13 +74,13 @@ void trap_c(struct pt_regs *regs) |
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unsigned short data = 0; |
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switch (trapnr) { |
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/* 0x26 - Data CPLB Miss */ |
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/* 0x26 - Data CPLB Miss */ |
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case VEC_CPLB_M: |
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#ifdef ANOMALY_05000261 |
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/*
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* Work around an anomaly: if we see a new DCPLB fault,
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* return without doing anything. Then,
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* Work around an anomaly: if we see a new DCPLB fault, |
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* return without doing anything. Then, |
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* if we get the same fault again, handle it. |
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*/ |
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addr = last_cplb_fault_retx; |
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@ -104,9 +95,9 @@ void trap_c(struct pt_regs *regs) |
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case VEC_CPLB_I_M: |
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if (data) { |
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addr = *pDCPLB_FAULT_ADDR; |
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addr = *(unsigned int *)pDCPLB_FAULT_ADDR; |
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} else { |
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addr = *pICPLB_FAULT_ADDR; |
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addr = *(unsigned int *)pICPLB_FAULT_ADDR; |
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} |
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for (i = 0; i < page_descriptor_table_size; i++) { |
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if (data) { |
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@ -117,7 +108,7 @@ void trap_c(struct pt_regs *regs) |
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j = icplb_table[i][0]; |
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} |
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if ((j <= addr) && ((j + size) > addr)) { |
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pr_debug("found %i 0x%08x\n", i, j); |
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debug("found %i 0x%08x\n", i, j); |
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break; |
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} |
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} |
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@ -128,16 +119,16 @@ void trap_c(struct pt_regs *regs) |
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/* Turn the cache off */ |
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if (data) { |
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__builtin_bfin_ssync(); |
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sync(); |
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asm(" .align 8; "); |
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*(unsigned int *)DMEM_CONTROL &= |
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~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); |
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__builtin_bfin_ssync(); |
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sync(); |
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} else { |
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__builtin_bfin_ssync(); |
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sync(); |
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asm(" .align 8; "); |
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*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); |
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__builtin_bfin_ssync(); |
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sync(); |
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} |
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if (data) { |
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@ -150,16 +141,16 @@ void trap_c(struct pt_regs *regs) |
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j = 0; |
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while (*I1 & CPLB_LOCK) { |
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pr_debug("skipping %i %08p - %08x\n", j, I1, *I1); |
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debug("skipping %i %08p - %08x\n", j, I1, *I1); |
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*I0++; |
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*I1++; |
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j++; |
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} |
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pr_debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1); |
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debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1); |
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for (; j < 15; j++) { |
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pr_debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1); |
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debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1); |
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*I0++ = *(I0 + 1); |
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*I1++ = *(I1 + 1); |
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} |
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@ -177,22 +168,22 @@ void trap_c(struct pt_regs *regs) |
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} |
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for (j = 0; j < 16; j++) { |
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pr_debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++); |
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debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++); |
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} |
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/* Turn the cache back on */ |
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if (data) { |
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j = *(unsigned int *)DMEM_CONTROL; |
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__builtin_bfin_ssync(); |
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sync(); |
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asm(" .align 8; "); |
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*(unsigned int *)DMEM_CONTROL = |
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ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; |
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__builtin_bfin_ssync(); |
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sync(); |
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} else { |
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__builtin_bfin_ssync(); |
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sync(); |
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asm(" .align 8; "); |
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*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; |
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__builtin_bfin_ssync(); |
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sync(); |
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} |
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break; |
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@ -209,42 +200,41 @@ void trap_c(struct pt_regs *regs) |
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do_reset(NULL, 0, 0, NULL); |
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} |
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trap_c_return: |
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return; |
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} |
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void dump(struct pt_regs *fp) |
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{ |
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pr_debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", |
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debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n", |
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fp->rete, fp->retn, fp->retx, fp->rets); |
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pr_debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg); |
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pr_debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp); |
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pr_debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", |
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debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg); |
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debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp); |
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debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", |
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fp->r0, fp->r1, fp->r2, fp->r3); |
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pr_debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", |
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debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", |
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fp->r4, fp->r5, fp->r6, fp->r7); |
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pr_debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", |
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debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", |
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fp->p0, fp->p1, fp->p2, fp->p3); |
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pr_debug("P4: %08lx P5: %08lx FP: %08lx\n", |
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debug("P4: %08lx P5: %08lx FP: %08lx\n", |
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fp->p4, fp->p5, fp->fp); |
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pr_debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", |
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debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", |
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fp->a0w, fp->a0x, fp->a1w, fp->a1x); |
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pr_debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", |
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debug("LB0: %08lx LT0: %08lx LC0: %08lx\n", |
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fp->lb0, fp->lt0, fp->lc0); |
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pr_debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", |
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debug("LB1: %08lx LT1: %08lx LC1: %08lx\n", |
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fp->lb1, fp->lt1, fp->lc1); |
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pr_debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", |
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debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n", |
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fp->b0, fp->l0, fp->m0, fp->i0); |
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pr_debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", |
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debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n", |
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fp->b1, fp->l1, fp->m1, fp->i1); |
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pr_debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", |
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debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n", |
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fp->b2, fp->l2, fp->m2, fp->i2); |
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pr_debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", |
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debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n", |
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fp->b3, fp->l3, fp->m3, fp->i3); |
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pr_debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR); |
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pr_debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR); |
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debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR); |
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debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR); |
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} |
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