From eea5a743a2193ef2a05b9bc6dc447ba241416f35 Mon Sep 17 00:00:00 2001 From: Markus Brunner Date: Mon, 28 Apr 2008 08:47:47 +0200 Subject: [PATCH 1/6] ppc4xx: Fixup ebc clock in FDT for 405GP/EP On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc doesn't exist. Signed-off-by: Markus Brunner --- cpu/ppc4xx/fdt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 1f4d6f2..02dece0 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -83,8 +83,14 @@ void ft_cpu_setup(void *blob, bd_t *bd) bd->bi_intfreq, 1); do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); - do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", - sys_info.freqEBC, 1); + + if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0) + do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency", + sys_info.freqEBC, 1); + else + do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency", + sys_info.freqEBC, 1); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* From 135846d6ecaad255ad28d93ebbb78b3d5da68cdc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 29 Apr 2008 13:36:51 +0200 Subject: [PATCH 2/6] ppc4xx: Change ECC initialization on lwmon5 to use clean_dcache_range() As it seems the "old" ECC initialization routine by using dflush() didn't write all lines in the dcache back to memory on lwmon5. This could lead to ECC error upon Linux booting. This patch changes the program_ecc() routine to now use clean_dcache_range() instead of dflush(). clean_dcache_range() uses dcbst which is exactly what we want in this case. Since dflush() is known is cause problems, this routine will be removed completely and replaced by clean_dcache_range() with an additional patch. Signed-off-by: Stefan Roese --- board/lwmon5/sdram.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 7c3cf49..36b5100 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -59,7 +60,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); static u32 is_ecc_enabled(void) { @@ -106,6 +106,7 @@ static void program_ecc(u32 start_address, { u32 val; u32 current_addr = start_address; + u32 size; int bytes_remaining; sync(); @@ -123,12 +124,18 @@ static void program_ecc(u32 start_address, * watchdog. */ while (bytes_remaining > 0) { - dcbz_area(current_addr, min((64 << 20), bytes_remaining)); + size = min((64 << 20), bytes_remaining); + + /* Write zero's to SDRAM */ + dcbz_area(current_addr, size); + + /* Write modified dcache lines back to memory */ + clean_dcache_range(current_addr, current_addr + size); + current_addr += 64 << 20; bytes_remaining -= 64 << 20; WATCHDOG_RESET(); } - dflush(); sync(); wait_ddr_idle(); From 85ad184b3b2b0f8af9228477303c55dca1b52ed7 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 29 Apr 2008 13:57:07 +0200 Subject: [PATCH 3/6] ppc4xx: Complete remove bogus dflush() Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese --- board/netstal/hcu5/sdram.c | 6 +++--- cpu/ppc4xx/44x_spd_ddr2.c | 5 +++-- cpu/ppc4xx/denali_spd_ddr2.c | 4 ++-- cpu/ppc4xx/start.S | 29 ----------------------------- 4 files changed, 8 insertions(+), 36 deletions(-) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0b16b505..6b1b53a 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -34,11 +34,11 @@ #include #include #include +#include #include void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); #define DDR_DCR_BASE 0x10 #define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ @@ -185,14 +185,14 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes) #endif sync(); - eieio(); puts(str); /* ECC bit set method for cached memory */ /* Fast method, no noticeable delay */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); blank_string(strlen(str)); /* Clear error status */ diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 9e722b9..5b5de48 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -40,6 +40,7 @@ #include #include #include +#include #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ @@ -237,7 +238,6 @@ static void DQS_calibration_process(void); static void ppc440sp_sdram_register_dump(void); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); -void dflush(void); static u32 mfdcr_any(u32 dcr) { @@ -2355,7 +2355,8 @@ static void program_ecc_addr(unsigned long start_address, } else { /* ECC bit set method for cached memory */ dcbz_area(start_address, num_bytes); - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); } blank_string(strlen(str)); diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index e20c9eb..acf0f49 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -92,7 +92,6 @@ extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); extern void dcbz_area(u32 start_address, u32 num_bytes); -extern void dflush(void); /* * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed @@ -1201,7 +1200,8 @@ long int initdram(int board_type) #else #error Please define CFG_MEM_TOP_HIDE (see README) in your board config file #endif - dflush(); + /* Write modified dcache lines back to memory */ + clean_dcache_range(CFG_SDRAM_BASE, CFG_SDRAM_BASE + dram_size - CFG_MEM_TOP_HIDE); debug("Completed\n"); sync(); remove_tlb(CFG_SDRAM_BASE, dram_size); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 8d2777d..a513b45 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1675,35 +1675,6 @@ trap_reloc: sync blr function_epilog(dcbz_area) - -/*----------------------------------------------------------------------------+ -| dflush. Assume 32K at vector address is cachable. -+----------------------------------------------------------------------------*/ - function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - mfspr r8,dvlim - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 -..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag - mtspr dvlim,r8 - sync - mtmsr r9 - blr - function_epilog(dflush) #endif /* CONFIG_440 */ #endif /* CONFIG_NAND_SPL */ From 4ec9d78fe5cd585d2868731fa108ca1e62730e70 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 29 Apr 2008 14:12:07 +0200 Subject: [PATCH 4/6] ppc4xx: Fix Katmai CFG_MONITOR_LEN Signed-off-by: Stefan Roese --- include/configs/katmai.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 122b700..aad28fb 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -48,7 +48,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ From cab99d6f3281ab6784feccf98b9b425daa58418a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 29 Apr 2008 14:44:54 +0200 Subject: [PATCH 5/6] ppc4xx: Fix compilation warning in denali_spd_ddr2.c Signed-off-by: Stefan Roese --- cpu/ppc4xx/denali_spd_ddr2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index acf0f49..ad805b9 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -45,6 +45,7 @@ #include #include #include +#include #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) From f4c4d21a885ccc222fd0acdf653b683249e85117 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 29 Apr 2008 16:08:05 +0200 Subject: [PATCH 6/6] ppc4xx: Fix CFG_MONITOR_LEN on Katmai failsave this time Signed-off-by: Stefan Roese --- include/configs/katmai.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/katmai.h b/include/configs/katmai.h index aad28fb..d2f6b10 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -48,12 +48,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ - #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ @@ -82,6 +78,10 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1) +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/