Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.hmaster
commit
85b8c5c4bf
@ -1,6 +1,6 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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LOAD 0x0 OBJTREE/spl/u-boot-spl.bin |
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CALL 0x14 0x0 |
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LOAD 0x40000100 u-boot.bin |
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LOAD 0x40000100 OBJTREE/u-boot.bin |
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CALL 0x40000100 0x0 |
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|
@ -1,8 +1,8 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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LOAD 0x0 OBJTREE/spl/u-boot-spl.bin |
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LOAD IVT 0x8000 0x14 |
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CALL HAB 0x8000 0x0 |
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LOAD 0x40000100 u-boot.bin |
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LOAD 0x40000100 OBJTREE/u-boot.bin |
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LOAD IVT 0x8000 0x40000100 |
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CALL HAB 0x8000 0x0 |
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|
@ -0,0 +1,52 @@ |
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/*
|
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
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* |
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* Based on: |
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* |
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* ------------------------------------------------------------------------- |
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* |
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* linux/include/asm-arm/arch-davinci/hardware.h |
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* |
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* Copyright (C) 2006 Texas Instruments. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ASM_DAVINCI_RTC_H |
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#define __ASM_DAVINCI_RTC_H |
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|
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struct davinci_rtc { |
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unsigned int second; |
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unsigned int minutes; |
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unsigned int hours; |
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unsigned int day; |
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unsigned int month; /* 0x10 */ |
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unsigned int year; |
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unsigned int dotw; |
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unsigned int resv1; |
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unsigned int alarmsecond; /* 0x20 */ |
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unsigned int alarmminute; |
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unsigned int alarmhour; |
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unsigned int alarmday; |
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unsigned int alarmmonth; /* 0x30 */ |
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unsigned int alarmyear; |
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unsigned int resv2[2]; |
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unsigned int ctrl; /* 0x40 */ |
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unsigned int status; |
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unsigned int irq; |
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unsigned int complsb; |
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unsigned int compmsb; /* 0x50 */ |
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unsigned int osc; |
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unsigned int resv3[2]; |
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unsigned int scratch0; /* 0x60 */ |
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unsigned int scratch1; |
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unsigned int scratch2; |
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unsigned int kick0r; |
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unsigned int kick1r; /* 0x70 */ |
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}; |
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|
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#define RTC_STATE_BUSY 0x01 |
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#define RTC_STATE_RUN 0x02 |
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|
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#define RTC_KICK0R_WE 0x83e70b13 |
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#define RTC_KICK1R_WE 0x95a4f1e0 |
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#endif |
@ -0,0 +1,10 @@ |
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#
|
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# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
|
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#
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# Author: Igor Grinberg <grinberg@compulab.co.il>
|
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
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obj-$(CONFIG_LCD) += omap3_display.o
|
@ -0,0 +1,80 @@ |
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/*
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* Copyright (c) 2013 Corscience GmbH & Co.KG |
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* Andreas Bießmann <andreas.biessmann@corscience.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <status_led.h> |
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#include <twl4030.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/io.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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|
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#define TRICORDER_STATUS_LED_YELLOW 42 |
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#define TRICORDER_STATUS_LED_GREEN 43 |
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|
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void __led_init(led_id_t mask, int state) |
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{ |
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__led_set(mask, state); |
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} |
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|
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void __led_toggle(led_id_t mask) |
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{ |
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int toggle_gpio = 0; |
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#ifdef STATUS_LED_BIT |
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if (!toggle_gpio && STATUS_LED_BIT & mask) |
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toggle_gpio = TRICORDER_STATUS_LED_GREEN; |
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#endif |
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#ifdef STATUS_LED_BIT1 |
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if (!toggle_gpio && STATUS_LED_BIT1 & mask) |
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toggle_gpio = TRICORDER_STATUS_LED_YELLOW; |
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#endif |
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#ifdef STATUS_LED_BIT2 |
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if (!toggle_gpio && STATUS_LED_BIT2 & mask) { |
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uint8_t val; |
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twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, |
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&val); |
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val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM); |
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twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, |
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val); |
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} |
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#endif |
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if (toggle_gpio) { |
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int state; |
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gpio_request(toggle_gpio, ""); |
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state = gpio_get_value(toggle_gpio); |
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gpio_set_value(toggle_gpio, !state); |
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} |
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} |
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|
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void __led_set(led_id_t mask, int state) |
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{ |
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#ifdef STATUS_LED_BIT |
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if (STATUS_LED_BIT & mask) { |
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gpio_request(TRICORDER_STATUS_LED_GREEN, ""); |
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gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0); |
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gpio_set_value(TRICORDER_STATUS_LED_GREEN, state); |
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} |
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#endif |
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#ifdef STATUS_LED_BIT1 |
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if (STATUS_LED_BIT1 & mask) { |
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gpio_request(TRICORDER_STATUS_LED_YELLOW, ""); |
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gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0); |
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gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state); |
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} |
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#endif |
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#ifdef STATUS_LED_BIT2 |
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if (STATUS_LED_BIT2 & mask) { |
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if (STATUS_LED_OFF == state) |
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twl4030_i2c_write_u8(TWL4030_CHIP_LED, |
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TWL4030_LED_LEDEN, 0); |
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else |
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twl4030_i2c_write_u8(TWL4030_CHIP_LED, |
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TWL4030_LED_LEDEN, |
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(TWL4030_LED_LEDEN_LEDAON | |
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TWL4030_LED_LEDEN_LEDAPWM)); |
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} |
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#endif |
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} |
@ -0,0 +1,251 @@ |
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/*
|
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* (C) Copyright 2013 |
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* Corscience GmbH & Co. KG, <www.corscience.de> |
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* Andreas Bießmann <andreas.biessmann@corscience.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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|
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#include "tricorder-eeprom.h" |
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static inline void warn_wrong_value(const char *msg, unsigned int a, |
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unsigned int b) |
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{ |
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printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b); |
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} |
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|
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static int handle_eeprom_v0(struct tricorder_eeprom *eeprom) |
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{ |
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struct tricorder_eeprom_v0 { |
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uint32_t magic; |
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uint16_t length; |
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uint16_t version; |
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char board_name[TRICORDER_BOARD_NAME_LENGTH]; |
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char board_version[TRICORDER_BOARD_VERSION_LENGTH]; |
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char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; |
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uint32_t crc32; |
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} __packed eepromv0; |
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uint32_t crc; |
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|
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printf("Old EEPROM (v0), consider rewrite!\n"); |
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|
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if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) { |
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warn_wrong_value("length", sizeof(eepromv0), |
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be16_to_cpu(eeprom->length)); |
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return 1; |
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} |
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|
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memcpy(&eepromv0, eeprom, sizeof(eepromv0)); |
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|
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crc = crc32(0L, (unsigned char *)&eepromv0, |
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sizeof(eepromv0) - sizeof(eepromv0.crc32)); |
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if (be32_to_cpu(eepromv0.crc32) != crc) { |
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warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32), |
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crc); |
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return 1; |
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} |
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|
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/* Ok the content is correct, do the conversion */ |
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memset(eeprom->interface_version, 0x0, |
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TRICORDER_INTERFACE_VERSION_LENGTH); |
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crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); |
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eeprom->crc32 = cpu_to_be32(crc); |
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|
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return 0; |
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} |
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|
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static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) |
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{ |
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uint32_t crc; |
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|
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if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) { |
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warn_wrong_value("length", TRICORDER_EEPROM_SIZE, |
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be16_to_cpu(eeprom->length)); |
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return 1; |
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} |
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|
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crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); |
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if (be32_to_cpu(eeprom->crc32) != crc) { |
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warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc); |
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return 1; |
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} |
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|
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return 0; |
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} |
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|
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int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) |
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{ |
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM |
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unsigned int bus = i2c_get_bus_num(); |
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i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); |
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#endif |
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|
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memset(eeprom, 0, TRICORDER_EEPROM_SIZE); |
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|
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i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); |
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM |
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i2c_set_bus_num(bus); |
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#endif |
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|
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if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { |
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warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, |
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be32_to_cpu(eeprom->magic)); |
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return 1; |
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} |
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|
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switch (be16_to_cpu(eeprom->version)) { |
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case 0: |
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return handle_eeprom_v0(eeprom); |
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case 1: |
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return handle_eeprom_v1(eeprom); |
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default: |
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warn_wrong_value("version", TRICORDER_EEPROM_VERSION, |
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be16_to_cpu(eeprom->version)); |
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return 1; |
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} |
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} |
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|
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#if !defined(CONFIG_SPL) |
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int tricorder_eeprom_read(unsigned devaddr) |
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{ |
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struct tricorder_eeprom eeprom; |
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int ret = tricorder_get_eeprom(devaddr, &eeprom); |
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|
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if (ret) |
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return ret; |
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|
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printf("Board type: %.*s\n", |
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sizeof(eeprom.board_name), eeprom.board_name); |
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printf("Board version: %.*s\n", |
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sizeof(eeprom.board_version), eeprom.board_version); |
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printf("Board serial: %.*s\n", |
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sizeof(eeprom.board_serial), eeprom.board_serial); |
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printf("Board interface version: %.*s\n", |
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sizeof(eeprom.interface_version), |
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eeprom.interface_version); |
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|
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return ret; |
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} |
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|
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int tricorder_eeprom_write(unsigned devaddr, const char *name, |
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const char *version, const char *serial, const char *interface) |
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{ |
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struct tricorder_eeprom eeprom, eeprom_verify; |
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size_t length; |
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uint32_t crc; |
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int ret; |
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unsigned char *p; |
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int i; |
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM |
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unsigned int bus; |
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#endif |
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|
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memset(eeprom, 0, TRICORDER_EEPROM_SIZE); |
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memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); |
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|
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eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC); |
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eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE); |
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eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION); |
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|
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length = min(sizeof(eeprom.board_name), strlen(name)); |
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strncpy(eeprom.board_name, name, length); |
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|
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length = min(sizeof(eeprom.board_version), strlen(version)); |
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strncpy(eeprom.board_version, version, length); |
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|
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length = min(sizeof(eeprom.board_serial), strlen(serial)); |
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strncpy(eeprom.board_serial, serial, length); |
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|
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if (interface) { |
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length = min(sizeof(eeprom.interface_version), |
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strlen(interface)); |
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strncpy(eeprom.interface_version, interface, length); |
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} |
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|
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crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE); |
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eeprom.crc32 = cpu_to_be32(crc); |
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|
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#if defined(DEBUG) |
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puts("Tricorder EEPROM content:\n"); |
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print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); |
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#endif |
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|
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#ifdef CONFIG_SYS_EEPROM_BUS_NUM |
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bus = i2c_get_bus_num(); |
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i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); |
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#endif |
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|
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/* do page write to the eeprom */ |
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for (i = 0, p = (unsigned char *)&eeprom; |
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i < sizeof(eeprom); |
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i += 32, p += 32) { |
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ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, |
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p, min(sizeof(eeprom) - i, 32)); |
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if (ret) |
||||
break; |
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udelay(5000); /* 5ms write cycle timing */ |
||||
} |
||||
|
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ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, |
||||
TRICORDER_EEPROM_SIZE); |
||||
|
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if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { |
||||
printf("Tricorder: Could not verify EEPROM content!\n"); |
||||
ret = 1; |
||||
} |
||||
|
||||
#ifdef CONFIG_SYS_EEPROM_BUS_NUM |
||||
i2c_set_bus_num(bus); |
||||
#endif |
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return ret; |
||||
} |
||||
|
||||
int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
if (argc == 3) { |
||||
ulong dev_addr = simple_strtoul(argv[2], NULL, 16); |
||||
eeprom_init(); |
||||
if (strcmp(argv[1], "read") == 0) { |
||||
int rcode; |
||||
|
||||
rcode = tricorder_eeprom_read(dev_addr); |
||||
|
||||
return rcode; |
||||
} |
||||
} else if (argc == 6 || argc == 7) { |
||||
ulong dev_addr = simple_strtoul(argv[2], NULL, 16); |
||||
char *name = argv[3]; |
||||
char *version = argv[4]; |
||||
char *serial = argv[5]; |
||||
char *interface = NULL; |
||||
eeprom_init(); |
||||
|
||||
if (argc == 7) |
||||
interface = argv[6]; |
||||
|
||||
if (strcmp(argv[1], "write") == 0) { |
||||
int rcode; |
||||
|
||||
rcode = tricorder_eeprom_write(dev_addr, name, version, |
||||
serial, interface); |
||||
|
||||
return rcode; |
||||
} |
||||
} |
||||
|
||||
return CMD_RET_USAGE; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
tricordereeprom, 7, 1, do_tricorder_eeprom, |
||||
"Tricorder EEPROM", |
||||
"read devaddr\n" |
||||
" - read Tricorder EEPROM at devaddr and print content\n" |
||||
"tricordereeprom write devaddr name version serial [interface]\n" |
||||
" - write Tricorder EEPROM at devaddr with 'name', 'version'" |
||||
"and 'serial'\n" |
||||
" optional add an HW interface parameter" |
||||
); |
||||
#endif /* CONFIG_SPL */ |
@ -0,0 +1,41 @@ |
||||
/*
|
||||
* (C) Copyright 2013 |
||||
* Corscience GmbH & Co. KG, <www.corscience.de> |
||||
* Andreas Bießmann <andreas.biessmann@corscience.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef TRICORDER_EEPROM_H_ |
||||
#define TRICORDER_EEPROM_H_ |
||||
|
||||
#include <linux/compiler.h> |
||||
|
||||
#define TRICORDER_EEPROM_MAGIC 0xc2a94f52 |
||||
#define TRICORDER_EEPROM_VERSION 1 |
||||
|
||||
#define TRICORDER_BOARD_NAME_LENGTH 12 |
||||
#define TRICORDER_BOARD_VERSION_LENGTH 4 |
||||
#define TRICORDER_BOARD_SERIAL_LENGTH 12 |
||||
#define TRICORDER_INTERFACE_VERSION_LENGTH 4 |
||||
|
||||
struct tricorder_eeprom { |
||||
uint32_t magic; |
||||
uint16_t length; |
||||
uint16_t version; |
||||
char board_name[TRICORDER_BOARD_NAME_LENGTH]; |
||||
char board_version[TRICORDER_BOARD_VERSION_LENGTH]; |
||||
char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; |
||||
char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH]; |
||||
uint32_t crc32; |
||||
} __packed; |
||||
|
||||
#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom) |
||||
#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \ |
||||
sizeof(uint32_t)) |
||||
|
||||
/**
|
||||
* @brief read eeprom information from a specific eeprom address |
||||
*/ |
||||
int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom); |
||||
|
||||
#endif /* TRICORDER_EEPROM_H_ */ |
@ -1,8 +1,12 @@ |
||||
#
|
||||
# (C) Copyright 2006
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := flash.o pdnb3.o nand.o
|
||||
ifndef CONFIG_SPL_BUILD |
||||
obj-y := bg0900.o
|
||||
else |
||||
obj-y := spl_boot.o
|
||||
endif |
@ -0,0 +1,86 @@ |
||||
/*
|
||||
* PPC-AG BG0900 board |
||||
* |
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux-mx28.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <linux/mii.h> |
||||
#include <miiphy.h> |
||||
#include <netdev.h> |
||||
#include <errno.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/*
|
||||
* Functions |
||||
*/ |
||||
int board_early_init_f(void) |
||||
{ |
||||
/* IO0 clock at 480MHz */ |
||||
mxs_set_ioclk(MXC_IOCLK0, 480000); |
||||
/* IO1 clock at 480MHz */ |
||||
mxs_set_ioclk(MXC_IOCLK1, 480000); |
||||
|
||||
/* SSP2 clock at 160MHz */ |
||||
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
return mxs_dram_init(); |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Adress of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
struct mxs_clkctrl_regs *clkctrl_regs = |
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; |
||||
struct eth_device *dev; |
||||
int ret; |
||||
|
||||
ret = cpu_eth_init(bis); |
||||
|
||||
/* BG0900 uses ENET_CLK PAD to drive FEC clock */ |
||||
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, |
||||
&clkctrl_regs->hw_clkctrl_enet); |
||||
|
||||
/* Reset FEC PHYs */ |
||||
gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); |
||||
udelay(200); |
||||
gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); |
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); |
||||
if (ret) { |
||||
puts("FEC MXS: Unable to init FEC0\n"); |
||||
return ret; |
||||
} |
||||
|
||||
dev = eth_get_dev_by_name("FEC0"); |
||||
if (!dev) { |
||||
puts("FEC MXS: Unable to get FEC0 device entry\n"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
#endif |
@ -0,0 +1,153 @@ |
||||
/*
|
||||
* PPC-AG BG0900 Boot setup |
||||
* |
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/iomux-mx28.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) |
||||
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) |
||||
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) |
||||
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) |
||||
|
||||
const iomux_cfg_t iomux_setup[] = { |
||||
/* DUART */ |
||||
MX28_PAD_PWM0__DUART_RX, |
||||
MX28_PAD_PWM1__DUART_TX, |
||||
|
||||
/* GPMI NAND */ |
||||
MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_RDN__GPMI_RDN | |
||||
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), |
||||
MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, |
||||
MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, |
||||
|
||||
/* FEC0 */ |
||||
MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, |
||||
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, |
||||
|
||||
/* FEC0 Reset */ |
||||
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | |
||||
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), |
||||
|
||||
/* EMI */ |
||||
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, |
||||
|
||||
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, |
||||
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, |
||||
|
||||
/* SPI2 (for SPI flash) */ |
||||
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, |
||||
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, |
||||
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, |
||||
MX28_PAD_SSP2_SS0__SSP2_D3 | |
||||
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), |
||||
}; |
||||
|
||||
void mxs_adjust_memory_params(uint32_t *dram_vals) |
||||
{ |
||||
/*
|
||||
* DDR Controller Registers |
||||
* Manufacturer: Winbond |
||||
* Device Part Number: W972GG6JB-25I |
||||
* Clock Freq.: 200MHz |
||||
* Density: 2Gb |
||||
* Chip Selects: 1 |
||||
* Number of Banks: 8 |
||||
* Row address: 14 |
||||
* Column address: 10 |
||||
*/ |
||||
|
||||
dram_vals[0x74 / 4] = 0x0102010A; |
||||
dram_vals[0x98 / 4] = 0x04005003; |
||||
dram_vals[0x9c / 4] = 0x090000c8; |
||||
|
||||
dram_vals[0xa8 / 4] = 0x0036b009; |
||||
dram_vals[0xac / 4] = 0x03270612; |
||||
|
||||
dram_vals[0xb0 / 4] = 0x02020202; |
||||
dram_vals[0xb4 / 4] = 0x00c80029; |
||||
|
||||
dram_vals[0xc0 / 4] = 0x00011900; |
||||
|
||||
dram_vals[0x12c / 4] = 0x07400300; |
||||
dram_vals[0x130 / 4] = 0x07400300; |
||||
dram_vals[0x2c4 / 4] = 0x02030303; |
||||
} |
||||
|
||||
void board_init_ll(const uint32_t arg, const uint32_t *resptr) |
||||
{ |
||||
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); |
||||
} |
@ -1,73 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
#if !defined(CONFIG_FLASH_CFI_DRIVER) |
||||
|
||||
/*
|
||||
* include common flash code (for esd boards) |
||||
*/ |
||||
#include "../common/flash.c" |
||||
|
||||
/*
|
||||
* Prototypes |
||||
*/ |
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
||||
|
||||
static inline ulong ld(ulong x) |
||||
{ |
||||
ulong k = 0; |
||||
|
||||
while (x >>= 1) |
||||
++k; |
||||
|
||||
return k; |
||||
} |
||||
|
||||
unsigned long flash_init(void) |
||||
{ |
||||
unsigned long size; |
||||
int i; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++) |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
|
||||
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size, size<<20); |
||||
|
||||
/* Reconfigure CS0 to actual FLASH size */ |
||||
*IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, |
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Environment protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR, |
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
||||
|
||||
/* Redundant environment protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CONFIG_ENV_ADDR_REDUND, |
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
||||
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
||||
|
||||
flash_info[0].size = size; |
||||
|
||||
return size; |
||||
} |
||||
|
||||
#endif /* CONFIG_FLASH_CFI_DRIVER */ |
@ -1,129 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#if defined(CONFIG_CMD_NAND) |
||||
|
||||
#include <nand.h> |
||||
|
||||
struct pdnb3_ndfc_regs { |
||||
uchar cmd; |
||||
uchar wait; |
||||
uchar addr; |
||||
uchar term; |
||||
uchar data; |
||||
}; |
||||
|
||||
static u8 hwctl; |
||||
static struct pdnb3_ndfc_regs *pdnb3_ndfc; |
||||
|
||||
#define readb(addr) *(volatile u_char *)(addr) |
||||
#define readl(addr) *(volatile u_long *)(addr) |
||||
#define writeb(d,addr) *(volatile u_char *)(addr) = (d) |
||||
|
||||
/*
|
||||
* The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to |
||||
* the NAND devices. The NDFC has command, address and data registers that |
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the |
||||
* hwcontrol function to save the configuration in a global variable. |
||||
* We can then use this information in the read and write functions to |
||||
* determine which NDFC register to access. |
||||
* |
||||
* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte). |
||||
*/ |
||||
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
||||
{ |
||||
struct nand_chip *this = mtd->priv; |
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) { |
||||
if ( ctrl & NAND_CLE ) |
||||
hwctl |= 0x1; |
||||
else |
||||
hwctl &= ~0x1; |
||||
if ( ctrl & NAND_ALE ) |
||||
hwctl |= 0x2; |
||||
else |
||||
hwctl &= ~0x2; |
||||
if ( (ctrl & NAND_NCE) != NAND_NCE) |
||||
writeb(0x00, &(pdnb3_ndfc->term)); |
||||
} |
||||
if (cmd != NAND_CMD_NONE) |
||||
writeb(cmd, this->IO_ADDR_W); |
||||
} |
||||
|
||||
|
||||
static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) |
||||
{ |
||||
return readb(&(pdnb3_ndfc->data)); |
||||
} |
||||
|
||||
static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) { |
||||
if (hwctl & 0x1) |
||||
writeb(buf[i], &(pdnb3_ndfc->cmd)); |
||||
else if (hwctl & 0x2) |
||||
writeb(buf[i], &(pdnb3_ndfc->addr)); |
||||
else |
||||
writeb(buf[i], &(pdnb3_ndfc->data)); |
||||
} |
||||
} |
||||
|
||||
static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) |
||||
buf[i] = readb(&(pdnb3_ndfc->data)); |
||||
} |
||||
|
||||
static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < len; i++) |
||||
if (buf[i] != readb(&(pdnb3_ndfc->data))) |
||||
return i; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pdnb3_nand_dev_ready(struct mtd_info *mtd) |
||||
{ |
||||
/*
|
||||
* Blocking read to wait for NAND to be ready |
||||
*/ |
||||
readb(&(pdnb3_ndfc->wait)); |
||||
|
||||
/*
|
||||
* Return always true |
||||
*/ |
||||
return 1; |
||||
} |
||||
|
||||
int board_nand_init(struct nand_chip *nand) |
||||
{ |
||||
pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE; |
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT; |
||||
|
||||
/* Set address of NAND IO lines (Using Linear Data Access Region) */ |
||||
nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); |
||||
nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); |
||||
/* Reference hardware control function */ |
||||
nand->cmd_ctrl = pdnb3_nand_hwcontrol; |
||||
nand->read_byte = pdnb3_nand_read_byte; |
||||
nand->write_buf = pdnb3_nand_write_buf; |
||||
nand->read_buf = pdnb3_nand_read_buf; |
||||
nand->verify_buf = pdnb3_nand_verify_buf; |
||||
nand->dev_ready = pdnb3_nand_dev_ready; |
||||
return 0; |
||||
} |
||||
#endif |
@ -1,220 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2006 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <malloc.h> |
||||
#include <asm/arch/ixp425.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* predefine these here for FPGA programming (before including fpga.c) */ |
||||
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) |
||||
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) |
||||
#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) |
||||
#define OLD_VAL old_val |
||||
|
||||
static unsigned long old_val = 0; |
||||
|
||||
/*
|
||||
* include common fpga code (for prodrive boards) |
||||
*/ |
||||
#include "../common/fpga.c" |
||||
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations |
||||
*/ |
||||
int board_init(void) |
||||
{ |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x00000100; |
||||
|
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); |
||||
|
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); |
||||
|
||||
/*
|
||||
* Setup GPIO's for FPGA programming |
||||
*/ |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); |
||||
|
||||
/*
|
||||
* Setup GPIO's for interrupts |
||||
*/ |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); |
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); |
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); |
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); |
||||
GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); |
||||
GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); |
||||
|
||||
/*
|
||||
* Setup GPIO's for 33MHz clock output |
||||
*/ |
||||
*IXP425_GPIO_GPCLKR = 0x01FF0000; |
||||
GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); |
||||
|
||||
/*
|
||||
* Setup other chip select's |
||||
*/ |
||||
*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity |
||||
*/ |
||||
int checkboard(void) |
||||
{ |
||||
char buf[64]; |
||||
int i = getenv_f("serial#", buf, sizeof(buf)); |
||||
|
||||
puts("Board: PDNB3"); |
||||
|
||||
if (i > 0) { |
||||
puts(", serial# "); |
||||
puts(buf); |
||||
} |
||||
putc('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
int do_fpga_boot(unsigned char *fpgadata) |
||||
{ |
||||
unsigned char *dst; |
||||
int status; |
||||
int index; |
||||
int i; |
||||
ulong len = CONFIG_SYS_MALLOC_LEN; |
||||
|
||||
/*
|
||||
* Setup GPIO's for FPGA programming |
||||
*/ |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); |
||||
|
||||
/*
|
||||
* Save value so no readback is required upon programming |
||||
*/ |
||||
old_val = *IXP425_GPIO_GPOUTR; |
||||
|
||||
/*
|
||||
* First try to decompress fpga image (gzip compressed?) |
||||
*/ |
||||
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); |
||||
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { |
||||
printf("Error: Image has to be gzipp'ed!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
status = fpga_boot(dst, len); |
||||
if (status != 0) { |
||||
printf("\nFPGA: Booting failed "); |
||||
switch (status) { |
||||
case ERROR_FPGA_PRG_INIT_LOW: |
||||
printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
||||
break; |
||||
case ERROR_FPGA_PRG_INIT_HIGH: |
||||
printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
||||
break; |
||||
case ERROR_FPGA_PRG_DONE: |
||||
printf("(Timeout: DONE not high after programming FPGA)\n "); |
||||
break; |
||||
} |
||||
|
||||
/* display infos on fpgaimage */ |
||||
index = 15; |
||||
for (i=0; i<4; i++) { |
||||
len = dst[index]; |
||||
printf("FPGA: %s\n", &(dst[index+1])); |
||||
index += len+3; |
||||
} |
||||
putc ('\n'); |
||||
/* delayed reboot */ |
||||
for (i=5; i>0; i--) { |
||||
printf("Rebooting in %2d seconds \r",i); |
||||
for (index=0;index<1000;index++) |
||||
udelay(1000); |
||||
} |
||||
putc('\n'); |
||||
do_reset(NULL, 0, 0, NULL); |
||||
} |
||||
|
||||
puts("FPGA: "); |
||||
|
||||
/* display infos on fpgaimage */ |
||||
index = 15; |
||||
for (i=0; i<4; i++) { |
||||
len = dst[index]; |
||||
printf("%s ", &(dst[index+1])); |
||||
index += len+3; |
||||
} |
||||
putc('\n'); |
||||
|
||||
free(dst); |
||||
|
||||
/*
|
||||
* Reset FPGA |
||||
*/ |
||||
GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); |
||||
udelay(10); |
||||
GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
ulong addr; |
||||
|
||||
if (argc < 2) |
||||
return cmd_usage(cmdtp); |
||||
|
||||
addr = simple_strtoul(argv[1], NULL, 16); |
||||
|
||||
return do_fpga_boot((unsigned char *)addr); |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
fpga, 2, 0, do_fpga, |
||||
"boot FPGA", |
||||
"address size\n - boot FPGA with gzipped image at <address>" |
||||
); |
||||
|
||||
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) |
||||
extern struct pci_controller hose; |
||||
extern void pci_ixp_init(struct pci_controller * hose); |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
extern void pci_ixp_init (struct pci_controller *hose); |
||||
|
||||
pci_ixp_init(&hose); |
||||
} |
||||
#endif |
@ -0,0 +1,7 @@ |
||||
#
|
||||
# (C) Copyright 2013 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := udoo.o
|
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
||||
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define WDT_EN IMX_GPIO_NR(5, 4) |
||||
#define WDT_TRG IMX_GPIO_NR(3, 19) |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static iomux_v3_cfg_t const uart2_pads[] = { |
||||
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = { |
||||
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = { |
||||
MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), |
||||
MX6_PAD_EIM_D19__GPIO_3_19, |
||||
}; |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
||||
} |
||||
|
||||
static void setup_iomux_wdog(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
||||
gpio_direction_output(WDT_TRG, 0); |
||||
gpio_direction_output(WDT_EN, 1); |
||||
} |
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; |
||||
|
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
return 1; /* Always present */ |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
||||
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
||||
usdhc_cfg.max_bus_width = 4; |
||||
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg); |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_wdog(); |
||||
setup_iomux_uart(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: Udoo\n"); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __CONFIGS_BG0900_H__ |
||||
#define __CONFIGS_BG0900_H__ |
||||
|
||||
/* System configurations */ |
||||
#define CONFIG_MX28 /* i.MX28 SoC */ |
||||
|
||||
/* U-Boot Commands */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_GPIO |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVEENV |
||||
#define CONFIG_CMD_SETEXPR |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_CMD_SPI |
||||
|
||||
/* Memory configuration */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */ |
||||
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
|
||||
/* Environment */ |
||||
#define CONFIG_ENV_SIZE (16 * 1024) |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
|
||||
/* FEC Ethernet on SoC */ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
/* SPI */ |
||||
#ifdef CONFIG_CMD_SPI |
||||
#define CONFIG_DEFAULT_SPI_BUS 2 |
||||
#define CONFIG_DEFAULT_SPI_CS 0 |
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 |
||||
|
||||
/* SPI FLASH */ |
||||
#ifdef CONFIG_CMD_SF |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SF_DEFAULT_BUS 2 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
|
||||
#define CONFIG_ENV_SPI_BUS 2 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 40000000 |
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
/* Boot Linux */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_BOOTARGS "console=ttyAMA0,115200" |
||||
#define CONFIG_BOOTCOMMAND "bootm" |
||||
#define CONFIG_LOADADDR 0x42000000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* Extra Environment */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"update_spi_firmware_filename=u-boot.sb\0" \
|
||||
"update_spi_firmware_maxsz=0x80000\0" \
|
||||
"update_spi_firmware=" /* Update the SPI flash firmware */ \
|
||||
"if sf probe 2:0 ; then " \
|
||||
"if tftp ${update_spi_firmware_filename} ; then " \
|
||||
"sf erase 0x0 +${filesize} ; " \
|
||||
"sf write ${loadaddr} 0x0 ${filesize} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" |
||||
|
||||
/* The rest of the configuration is shared */ |
||||
#include <configs/mxs.h> |
||||
|
||||
#endif /* __CONFIGS_BG0900_H__ */ |
@ -1,320 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2006-2007 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* Configuation settings for the PDNB3 board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ |
||||
#define CONFIG_PDNB3 1 /* on an PDNB3 board */ |
||||
|
||||
#define CONFIG_MACH_TYPE 1002 |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ |
||||
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ |
||||
|
||||
/*
|
||||
* Ethernet |
||||
*/ |
||||
#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ |
||||
#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ |
||||
|
||||
/*
|
||||
* Misc configuration options |
||||
*/ |
||||
#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ |
||||
#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (1 << 20) |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_IXP_SERIAL |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#if !defined(CONFIG_SCPU) |
||||
#define CONFIG_CMD_NAND |
||||
#endif |
||||
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ |
||||
|
||||
#define CONFIG_IXP425_TIMER_CLK 66666666 |
||||
|
||||
/***************************************************************
|
||||
* Platform/Board specific defines start here. |
||||
***************************************************************/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Default configuration (environment varibles...) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"hostname=pdnb3\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
|
||||
"mtdparts=${mtdparts}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/buildroot\0" \
|
||||
"bootfile=/tftpboot/netbox/uImage\0" \
|
||||
"kernel_addr=50080000\0" \
|
||||
"ramdisk_addr=50200000\0" \
|
||||
"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
|
||||
"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
|
||||
"cp.b 100000 50000000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load update\0" \
|
||||
"ipaddr=10.0.0.233\0" \
|
||||
"serverip=10.0.0.152\0" \
|
||||
"netmask=255.255.0.0\0" \
|
||||
"ethaddr=c6:6f:13:36:f3:81\0" \
|
||||
"eth1addr=c6:6f:13:36:f3:82\0" \
|
||||
"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
|
||||
"4k@508k(renv)\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run net_nfs" |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x50000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0x50000000 |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#if defined(CONFIG_SCPU) |
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ |
||||
#else |
||||
#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Expansion bus settings |
||||
*/ |
||||
#if defined(CONFIG_SCPU) |
||||
#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */ |
||||
#else |
||||
#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */ |
||||
#endif |
||||
#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */ |
||||
|
||||
/*
|
||||
* SDRAM settings |
||||
*/ |
||||
#define CONFIG_SYS_SDR_CONFIG 0x18 |
||||
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 |
||||
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
||||
|
||||
/*
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#if defined(CONFIG_SCPU) |
||||
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ |
||||
#endif |
||||
|
||||
#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ |
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
||||
#if defined(CONFIG_SCPU) |
||||
/* no redundant environment on SCPU */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#else |
||||
#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SCPU) |
||||
/*
|
||||
* NAND-FLASH stuff |
||||
*/ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ |
||||
#endif |
||||
|
||||
/*
|
||||
* GPIO settings |
||||
*/ |
||||
|
||||
/* FPGA program pin configuration */ |
||||
#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ |
||||
#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ |
||||
#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */ |
||||
#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */ |
||||
#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */ |
||||
|
||||
/* other GPIO's */ |
||||
#define CONFIG_SYS_GPIO_RESTORE_INT 0 |
||||
#define CONFIG_SYS_GPIO_RESTART_INT 1 |
||||
#define CONFIG_SYS_GPIO_SYS_RUNNING 2 |
||||
#define CONFIG_SYS_GPIO_PCI_INTA 3 |
||||
#define CONFIG_SYS_GPIO_PCI_INTB 4 |
||||
#define CONFIG_SYS_GPIO_I2C_SCL 6 |
||||
#define CONFIG_SYS_GPIO_I2C_SDA 7 |
||||
#define CONFIG_SYS_GPIO_FPGA_RESET 9 |
||||
#define CONFIG_SYS_GPIO_CLK_33M 15 |
||||
|
||||
/*
|
||||
* I2C stuff |
||||
*/ |
||||
|
||||
/* enable I2C and select the hardware/software driver */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) |
||||
#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) |
||||
|
||||
#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) |
||||
#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) |
||||
#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) |
||||
#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) |
||||
#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \ |
||||
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) |
||||
#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \ |
||||
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) |
||||
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ |
||||
|
||||
/*
|
||||
* I2C RTC |
||||
*/ |
||||
#if 0 /* test-only */
|
||||
#define CONFIG_RTC_DS1340 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
#else |
||||
/* M41T11 Serial Access Timekeeper(R) SRAM */ |
||||
#define CONFIG_RTC_M41T11 1 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Spartan3 FPGA configuration support |
||||
*/ |
||||
#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ |
||||
|
||||
#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/ |
||||
#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */ |
||||
#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */ |
||||
#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */ |
||||
#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */ |
||||
|
||||
/*
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 |
||||
|
||||
/* additions for new relocation code, must be added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
@ -0,0 +1,206 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for Udoo board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
#include <asm/sizes.h> |
||||
|
||||
#define CONFIG_MX6 |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define MACH_TYPE_UDOO 4800 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_UDOO |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Command definition */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_CMD_BMODE |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) |
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
/* MMC Configuration */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc1\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x11000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"update_sd_firmware_filename=u-boot.imx\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H * */ |
Loading…
Reference in new issue