Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>master
Jagan Teki
8 years ago
committed by
Stefano Babic
parent
704b9cfc9e
commit
871ec6da42
@ -0,0 +1,50 @@ |
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/* |
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* Copyright (C) 2015 Amarula Solutions B.V. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* version 2 as published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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/dts-v1/; |
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|
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#include "imx6q.dtsi" |
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#include "imx6qdl-icore-rqs.dtsi" |
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|
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/ { |
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model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; |
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compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; |
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}; |
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@ -0,0 +1,83 @@ |
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/* |
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* Copyright (C) 2015 Amarula Solutions B.V. |
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* |
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* This file is dual-licensed: you can use it either under the terms |
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* of the GPL or the X11 license, at your option. Note that this dual |
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* licensing only applies to this file, and not this project as a |
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* whole. |
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* |
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* a) This file is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* version 2 as published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* Or, alternatively |
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* |
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* b) Permission is hereby granted, free of charge, to any person |
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* obtaining a copy of this software and associated documentation |
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* files (the "Software"), to deal in the Software without |
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* restriction, including without limitation the rights to use |
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* copy, modify, merge, publish, distribute, sublicense, and/or |
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* sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following |
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* conditions: |
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* |
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* The above copyright notice and this permission notice shall be |
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* included in all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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*/ |
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|
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/clock/imx6qdl-clock.h> |
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|
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/ { |
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memory { |
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reg = <0x10000000 0x80000000>; |
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}; |
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}; |
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|
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&uart4 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart4>; |
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status = "okay"; |
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}; |
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|
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&usdhc3 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usdhc3>; |
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
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no-1-8-v; |
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status = "okay"; |
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}; |
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|
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&iomuxc { |
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pinctrl_uart4: uart4grp { |
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fsl,pins = < |
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MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
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MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
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>; |
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}; |
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|
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pinctrl_usdhc3: usdhc3grp { |
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fsl,pins = < |
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 |
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 |
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 |
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 |
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 |
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 |
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>; |
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}; |
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}; |
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@ -0,0 +1,12 @@ |
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if TARGET_MX6Q_ICORE_RQS |
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|
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config SYS_BOARD |
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default "icorem6_rqs" |
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|
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config SYS_VENDOR |
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default "engicam" |
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|
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config SYS_CONFIG_NAME |
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default "imx6qdl_icore_rqs" |
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endif |
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@ -0,0 +1,6 @@ |
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ICOREM6QDL_RQS BOARD |
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M: Jagan Teki <jagan@amarulasolutions.com> |
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S: Maintained |
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F: board/engicam/icorem6_rqs |
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F: include/configs/imx6qdl_icore_rqs.h |
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F: configs/imx6q_icore_rqs_mmc_defconfig |
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@ -0,0 +1,6 @@ |
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# Copyright (C) 2016 Amarula Solutions B.V.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := icorem6_rqs.o
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@ -0,0 +1,30 @@ |
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How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit: |
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---------------------------------------------------------------- |
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|
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$ make mrproper |
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|
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- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual: |
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$ make imx6q_icore_rqs_mmc_defconfig |
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|
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- Build U-Boot |
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$ make |
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This will generate the SPL image called SPL and the u-boot-dtb.img. |
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|
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- Flash the SPL image into the micro SD card: |
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sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync |
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|
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- Flash the u-boot-dtb.img image into the micro SD card: |
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sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync |
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|
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- Jumper settings: |
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MMC Boot: JM3 Closed |
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|
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- Connect the Serial cable between the Starter Kit and the PC for the console. |
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(J28 is the Linux Serial console connector) |
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|
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- Insert the micro SD card in the board, power it up and U-Boot messages should |
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come up. |
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@ -0,0 +1,399 @@ |
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/*
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* Copyright (C) 2016 Amarula Solutions B.V. |
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* Copyright (C) 2016 Engicam S.r.l. |
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* Author: Jagan Teki <jagan@amarulasolutions.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <linux/sizes.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/imx-common/iomux-v3.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const uart4_pads[] = { |
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IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
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}; |
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int board_early_init_f(void) |
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{ |
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SETUP_IOMUX_PADS(uart4_pads); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* Address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = imx_ddr_size(); |
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return 0; |
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} |
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#ifdef CONFIG_SPL_BUILD |
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#include <libfdt.h> |
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#include <spl.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/mx6-ddr.h> |
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/* MMC board initialization is needed till adding DM support in SPL */ |
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#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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static iomux_v3_cfg_t const usdhc3_pads[] = { |
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IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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}; |
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struct fsl_esdhc_cfg usdhc_cfg[1] = { |
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{USDHC3_BASE_ADDR, 1, 4}, |
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}; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
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int ret = 0; |
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switch (cfg->esdhc_base) { |
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case USDHC3_BASE_ADDR: |
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ret = 1; |
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break; |
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} |
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return ret; |
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} |
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int board_mmc_init(bd_t *bis) |
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{ |
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int i, ret; |
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/*
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* According to the board_mmc_init() the following map is done: |
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* (U-boot device node) (Physical Port) |
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* mmc0 USDHC3 |
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*/ |
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
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switch (i) { |
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case 0: |
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SETUP_IOMUX_PADS(usdhc3_pads); |
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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break; |
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default: |
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printf("Warning - USDHC%d controller not supporting\n", |
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i + 1); |
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return 0; |
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} |
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
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if (ret) { |
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printf("Warning: failed to initialize mmc dev %d\n", i); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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#endif |
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/*
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* Driving strength: |
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* 0x30 == 40 Ohm |
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* 0x28 == 48 Ohm |
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*/ |
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#define IMX6DQ_DRIVE_STRENGTH 0x30 |
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#define IMX6SDL_DRIVE_STRENGTH 0x28 |
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/* configure MX6Q/DUAL mmdc DDR io registers */ |
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static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { |
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.dram_sdqs0 = 0x28, |
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.dram_sdqs1 = 0x28, |
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.dram_sdqs2 = 0x28, |
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.dram_sdqs3 = 0x28, |
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.dram_sdqs4 = 0x28, |
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.dram_sdqs5 = 0x28, |
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.dram_sdqs6 = 0x28, |
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.dram_sdqs7 = 0x28, |
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.dram_dqm0 = 0x28, |
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.dram_dqm1 = 0x28, |
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.dram_dqm2 = 0x28, |
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.dram_dqm3 = 0x28, |
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.dram_dqm4 = 0x28, |
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.dram_dqm5 = 0x28, |
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.dram_dqm6 = 0x28, |
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.dram_dqm7 = 0x28, |
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.dram_cas = 0x30, |
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.dram_ras = 0x30, |
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.dram_sdclk_0 = 0x30, |
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.dram_sdclk_1 = 0x30, |
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.dram_reset = 0x30, |
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.dram_sdcke0 = 0x3000, |
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.dram_sdcke1 = 0x3000, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdodt0 = 0x30, |
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.dram_sdodt1 = 0x30, |
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}; |
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|
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/* configure MX6Q/DUAL mmdc GRP io registers */ |
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static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { |
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.grp_b0ds = 0x30, |
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.grp_b1ds = 0x30, |
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.grp_b2ds = 0x30, |
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.grp_b3ds = 0x30, |
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.grp_b4ds = 0x30, |
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.grp_b5ds = 0x30, |
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.grp_b6ds = 0x30, |
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.grp_b7ds = 0x30, |
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.grp_addds = 0x30, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_ddrmode = 0x00020000, |
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.grp_ctlds = 0x30, |
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.grp_ddr_type = 0x000c0000, |
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}; |
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|
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/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
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.dram_sdclk_0 = 0x30, |
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.dram_sdclk_1 = 0x30, |
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.dram_cas = 0x30, |
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.dram_ras = 0x30, |
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.dram_reset = 0x30, |
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.dram_sdcke0 = 0x30, |
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.dram_sdcke1 = 0x30, |
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.dram_sdba2 = 0x00000000, |
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.dram_sdodt0 = 0x30, |
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.dram_sdodt1 = 0x30, |
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.dram_sdqs0 = 0x28, |
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.dram_sdqs1 = 0x28, |
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.dram_sdqs2 = 0x28, |
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.dram_sdqs3 = 0x28, |
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.dram_sdqs4 = 0x28, |
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.dram_sdqs5 = 0x28, |
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.dram_sdqs6 = 0x28, |
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.dram_sdqs7 = 0x28, |
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.dram_dqm0 = 0x28, |
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.dram_dqm1 = 0x28, |
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.dram_dqm2 = 0x28, |
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.dram_dqm3 = 0x28, |
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.dram_dqm4 = 0x28, |
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.dram_dqm5 = 0x28, |
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.dram_dqm6 = 0x28, |
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.dram_dqm7 = 0x28, |
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}; |
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|
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
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.grp_ddr_type = 0x000c0000, |
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.grp_ddrmode_ctl = 0x00020000, |
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.grp_ddrpke = 0x00000000, |
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.grp_addds = 0x30, |
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.grp_ctlds = 0x30, |
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.grp_ddrmode = 0x00020000, |
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.grp_b0ds = 0x28, |
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.grp_b1ds = 0x28, |
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.grp_b2ds = 0x28, |
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.grp_b3ds = 0x28, |
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.grp_b4ds = 0x28, |
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.grp_b5ds = 0x28, |
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.grp_b6ds = 0x28, |
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.grp_b7ds = 0x28, |
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}; |
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|
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/* mt41j256 */ |
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static struct mx6_ddr3_cfg mt41j256 = { |
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.mem_speed = 1066, |
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.density = 2, |
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.width = 16, |
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.banks = 8, |
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.rowaddr = 13, |
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.coladdr = 10, |
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.pagesz = 2, |
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.trcd = 1375, |
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.trcmin = 4875, |
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.trasmin = 3500, |
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.SRT = 0, |
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}; |
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|
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static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { |
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.p0_mpwldectrl0 = 0x000E0009, |
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.p0_mpwldectrl1 = 0x0018000E, |
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.p1_mpwldectrl0 = 0x00000007, |
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.p1_mpwldectrl1 = 0x00000000, |
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.p0_mpdgctrl0 = 0x43280334, |
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.p0_mpdgctrl1 = 0x031C0314, |
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.p1_mpdgctrl0 = 0x4318031C, |
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.p1_mpdgctrl1 = 0x030C0258, |
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.p0_mprddlctl = 0x3E343A40, |
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.p1_mprddlctl = 0x383C3844, |
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.p0_mpwrdlctl = 0x40404440, |
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.p1_mpwrdlctl = 0x4C3E4446, |
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}; |
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|
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/* DDR 64bit */ |
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static struct mx6_ddr_sysinfo mem_q = { |
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.ddr_type = DDR_TYPE_DDR3, |
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.dsize = 2, |
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.cs1_mirror = 0, |
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/* config for full 4GB range so that get_mem_size() works */ |
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.cs_density = 32, |
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.ncs = 1, |
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.bi_on = 1, |
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.rtt_nom = 2, |
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.rtt_wr = 2, |
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.ralat = 5, |
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.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { |
||||
.p0_mpwldectrl0 = 0x001F0024, |
||||
.p0_mpwldectrl1 = 0x00110018, |
||||
.p1_mpwldectrl0 = 0x001F0024, |
||||
.p1_mpwldectrl1 = 0x00110018, |
||||
.p0_mpdgctrl0 = 0x4230022C, |
||||
.p0_mpdgctrl1 = 0x02180220, |
||||
.p1_mpdgctrl0 = 0x42440248, |
||||
.p1_mpdgctrl1 = 0x02300238, |
||||
.p0_mprddlctl = 0x44444A48, |
||||
.p1_mprddlctl = 0x46484A42, |
||||
.p0_mpwrdlctl = 0x38383234, |
||||
.p1_mpwrdlctl = 0x3C34362E, |
||||
}; |
||||
|
||||
/* DDR 64bit 1GB */ |
||||
static struct mx6_ddr_sysinfo mem_dl = { |
||||
.dsize = 2, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
/* DDR 32bit 512MB */ |
||||
static struct mx6_ddr_sysinfo mem_s = { |
||||
.dsize = 1, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
}; |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
writel(0x00003F3F, &ccm->CCGR0); |
||||
writel(0x0030FC00, &ccm->CCGR1); |
||||
writel(0x000FC000, &ccm->CCGR2); |
||||
writel(0x3F300000, &ccm->CCGR3); |
||||
writel(0xFF00F300, &ccm->CCGR4); |
||||
writel(0x0F0000C3, &ccm->CCGR5); |
||||
writel(0x000003CC, &ccm->CCGR6); |
||||
} |
||||
|
||||
static void gpr_init(void) |
||||
{ |
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */ |
||||
writel(0xF00000CF, &iomux->gpr[4]); |
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
||||
writel(0x007F007F, &iomux->gpr[6]); |
||||
writel(0x007F007F, &iomux->gpr[7]); |
||||
} |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
if (is_mx6solo()) { |
||||
mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); |
||||
} else if (is_mx6dl()) { |
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); |
||||
} else if (is_mx6dq()) { |
||||
mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); |
||||
mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); |
||||
} |
||||
|
||||
udelay(100); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
ccgr_init(); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
gpr_init(); |
||||
|
||||
/* iomux */ |
||||
board_early_init_f(); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,38 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_MX6Q_ICORE_RQS=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" |
||||
CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb" |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" |
||||
CONFIG_SYS_PROMPT="icorem6qdl-rqs> " |
||||
CONFIG_SPL=y |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_DISPLAY_CPUINFO=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_AUTO_COMPLETE=y |
||||
CONFIG_SYS_MAXARGS=32 |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_BLK is not set |
||||
# CONFIG_DM_MMC_OPS is not set |
||||
CONFIG_CMD_BOOTZ=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_LIBFDT=y |
||||
CONFIG_MXC_UART=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
CONFIG_SPL_EXT_SUPPORT=y |
||||
@ -0,0 +1,124 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V. |
||||
* Copyright (C) 2016 Engicam S.r.l. |
||||
* |
||||
* Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H |
||||
#define __IMX6QLD_ICORE_RQS_CONFIG_H |
||||
|
||||
#include <linux/sizes.h> |
||||
#include "mx6_common.h" |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) |
||||
|
||||
/* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE SZ_128K |
||||
|
||||
/* Allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/* Environment */ |
||||
#ifndef CONFIG_ENV_IS_NOWHERE |
||||
/* Environment in MMC */ |
||||
# if defined(CONFIG_ENV_IS_IN_MMC) |
||||
# define CONFIG_ENV_OFFSET 0x100000 |
||||
# endif |
||||
#endif |
||||
|
||||
/* Default environment */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* UART */ |
||||
#ifdef CONFIG_MXC_UART |
||||
# define CONFIG_MXC_UART_BASE UART4_BASE |
||||
#endif |
||||
|
||||
/* MMC */ |
||||
#ifdef CONFIG_FSL_USDHC |
||||
# define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#endif |
||||
|
||||
/* SPL */ |
||||
#ifdef CONFIG_SPL |
||||
# define CONFIG_SPL_MMC_SUPPORT |
||||
# include "imx6_spl.h" |
||||
# ifdef CONFIG_SPL_BUILD |
||||
# undef CONFIG_DM_GPIO |
||||
# undef CONFIG_DM_MMC |
||||
# endif |
||||
#endif |
||||
|
||||
#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */ |
||||
Loading…
Reference in new issue