This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>master
Valentin Longchamp
11 years ago
committed by
York Sun
parent
935b402eae
commit
877bfe37dc
@ -0,0 +1,48 @@ |
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#
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# (C) Copyright 2001-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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ifneq ($(OBJTREE),$(SRCTREE)) |
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$(shell mkdir -p $(obj)../common) |
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endif |
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LIB = $(obj)lib$(BOARD).o
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COBJS := $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \
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../common/common.o ../common/ivm.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,64 @@ |
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/*
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* (C) Copyright 2013 Keymile AG |
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* Valentin Longchamp <valentin.longchamp@keymile.com> |
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* |
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* Copyright 2009-2011 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <hwconfig.h> |
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#include <asm/mmu.h> |
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#include <asm/fsl_ddr_sdram.h> |
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#include <asm/fsl_ddr_dimm_params.h> |
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void fsl_ddr_board_options(memctl_options_t *popts, |
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dimm_params_t *pdimm, |
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unsigned int ctrl_num) |
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{ |
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if (ctrl_num) { |
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printf("Wrong parameter for controller number %d", ctrl_num); |
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return; |
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} |
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/* automatic calibration for nb of cycles between read and DQS pre */ |
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popts->cpo_override = 0xFF; |
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/* 1/2 clk delay between wr command and data strobe */ |
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popts->write_data_delay = 4; |
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/* clk lauched 1/2 applied cylcle after address command */ |
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popts->clk_adjust = 4; |
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/* 1T timing: command/address held for only 1 cycle */ |
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popts->twot_en = 0; |
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/* we have only one module, half str should be OK */ |
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popts->half_strength_driver_enable = 1; |
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/* wrlvl values overriden as recommended by ddr init func */ |
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popts->wrlvl_override = 1; |
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popts->wrlvl_sample = 0xf; |
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popts->wrlvl_start = 0x6; |
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/* Enable ZQ calibration */ |
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popts->zq_en = 1; |
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/* DHC_EN =1, ODT = 75 Ohm */ |
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm; |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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phys_size_t dram_size = 0; |
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puts("Initializing with SPD\n"); |
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dram_size = fsl_ddr_sdram(); |
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dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
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dram_size *= 0x100000; |
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debug(" DDR: "); |
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return dram_size; |
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} |
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@ -0,0 +1,71 @@ |
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/*
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* (C) Copyright 2013 Keymile AG |
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* Valentin Longchamp <valentin.longchamp@keymile.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <fm_eth.h> |
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#include <fsl_mdio.h> |
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#include <phy.h> |
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int board_eth_init(bd_t *bis) |
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{ |
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int ret = 0; |
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#ifdef CONFIG_FMAN_ENET |
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struct fsl_pq_mdio_info dtsec_mdio_info; |
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printf("Initializing Fman\n"); |
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dtsec_mdio_info.regs = |
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(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; |
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
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/* Register the real 1G MDIO bus */ |
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fsl_pq_mdio_init(bis, &dtsec_mdio_info); |
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/* DTESC1/2 don't have a PHY, they are temporarily disabled
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* so that u-boot doesn't try to unsuccessfuly enable them */ |
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fm_disable_port(FM1_DTSEC1); |
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fm_disable_port(FM1_DTSEC2); |
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/*
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* Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf |
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* This is the debug interface, the only one used in u-boot |
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*/ |
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fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); |
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fm_info_set_mdio(FM1_DTSEC5, |
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); |
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ret = cpu_eth_init(bis); |
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/* reenable DTSEC1/2 for later (kernel) */ |
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fm_enable_port(FM1_DTSEC1); |
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fm_enable_port(FM1_DTSEC2); |
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#endif |
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return ret; |
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} |
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#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL) |
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#define mv88E1118_PAGE_REG 22 |
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int board_phy_config(struct phy_device *phydev) |
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{ |
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if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) { |
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/* driver config is good */ |
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if (phydev->drv->config) |
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phydev->drv->config(phydev); |
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/* but we still need to fix the LEDs */ |
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phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003); |
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phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840); |
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phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000); |
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} |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,258 @@ |
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/*
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* (C) Copyright 2013 Keymile AG |
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* Valentin Longchamp <valentin.longchamp@keymile.com> |
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* |
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* Copyright 2011,2012 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <linux/compiler.h> |
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#include <asm/mmu.h> |
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#include <asm/processor.h> |
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#include <asm/cache.h> |
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#include <asm/immap_85xx.h> |
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#include <asm/fsl_law.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#include <fm_eth.h> |
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#include "../common/common.h" |
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#include "kmp204x.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); |
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return 0; |
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} |
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/* TODO: implement the I2C deblocking function */ |
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int i2c_make_abort(void) |
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{ |
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return 1; |
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} |
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#define ZL30158_RST 8 |
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#define ZL30343_RST 9 |
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int board_early_init_f(void) |
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{ |
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ |
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setbits_be32(&gur->ddrclkdr, 0x001f000f); |
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/* take the Zarlinks out of reset as soon as possible */ |
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qrio_prst(ZL30158_RST, false, false); |
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qrio_prst(ZL30343_RST, false, false); |
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/* and set their reset to power-up only */ |
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qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); |
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qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST); |
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return 0; |
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} |
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int board_early_init_r(void) |
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{ |
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/* Flush d-cache and invalidate i-cache of any FLASH data */ |
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flush_dcache(); |
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invalidate_icache(); |
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set_liodns(); |
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setup_portals(); |
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return 0; |
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} |
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unsigned long get_board_sys_clk(unsigned long dummy) |
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{ |
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return 66666666; |
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} |
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#define WDMASK_OFF 0x16 |
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static void qrio_wdmask(u8 bit, bool wden) |
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{ |
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u16 wdmask; |
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; |
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wdmask = in_be16(qrio_base + WDMASK_OFF); |
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if (wden) |
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wdmask |= (1 << bit); |
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else |
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wdmask &= ~(1 << bit); |
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out_be16(qrio_base + WDMASK_OFF, wdmask); |
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} |
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#define PRST_OFF 0x1a |
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void qrio_prst(u8 bit, bool en, bool wden) |
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{ |
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u16 prst; |
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; |
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qrio_wdmask(bit, wden); |
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prst = in_be16(qrio_base + PRST_OFF); |
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if (en) |
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prst &= ~(1 << bit); |
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else |
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prst |= (1 << bit); |
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out_be16(qrio_base + PRST_OFF, prst); |
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} |
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#define PRSTCFG_OFF 0x1c |
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void qrio_prstcfg(u8 bit, u8 mode) |
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{ |
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u32 prstcfg; |
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u8 i; |
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; |
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prstcfg = in_be32(qrio_base + PRSTCFG_OFF); |
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for (i = 0; i < 2; i++) { |
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if (mode & (1<<i)) |
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set_bit(2*bit+i, &prstcfg); |
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else |
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clear_bit(2*bit+i, &prstcfg); |
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} |
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out_be32(qrio_base + PRSTCFG_OFF, prstcfg); |
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} |
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#define BOOTCOUNT_OFF 0x12 |
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void bootcount_store(ulong counter) |
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{ |
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u8 val; |
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; |
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val = (counter <= 255) ? (u8)counter : 255; |
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out_8(qrio_base + BOOTCOUNT_OFF, val); |
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} |
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ulong bootcount_load(void) |
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{ |
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u8 val; |
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void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; |
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val = in_8(qrio_base + BOOTCOUNT_OFF); |
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return val; |
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} |
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#define NUM_SRDS_BANKS 2 |
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#define PHY_RST 15 |
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int misc_init_r(void) |
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{ |
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serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
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u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100, |
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SRDS_PLLCR0_RFCK_SEL_125}; |
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unsigned int i; |
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/* check SERDES reference clocks */ |
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for (i = 0; i < NUM_SRDS_BANKS; i++) { |
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u32 actual = in_be32(®s->bank[i].pllcr0); |
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actual &= SRDS_PLLCR0_RFCK_SEL_MASK; |
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if (actual != expected[i]) { |
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printf("Warning: SERDES bank %u expects reference \
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clock %sMHz, but actual is %sMHz\n", i + 1, |
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serdes_clock_to_string(expected[i]), |
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serdes_clock_to_string(actual)); |
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} |
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} |
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/* take the mgmt eth phy out of reset */ |
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qrio_prst(PHY_RST, false, false); |
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return 0; |
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} |
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#if defined(CONFIG_HUSH_INIT_VAR) |
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int hush_init_var(void) |
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{ |
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ivm_read_eeprom(); |
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return 0; |
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} |
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#endif |
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#if defined(CONFIG_LAST_STAGE_INIT) |
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int last_stage_init(void) |
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{ |
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set_km_env(); |
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return 0; |
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} |
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#endif |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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void fdt_fixup_fman_mac_addresses(void *blob) |
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{ |
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int node, i, ret; |
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char *tmp, *end; |
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unsigned char mac_addr[6]; |
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/* get the mac addr from env */ |
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tmp = getenv("ethaddr"); |
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if (!tmp) { |
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printf("ethaddr env variable not defined\n"); |
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return; |
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} |
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for (i = 0; i < 6; i++) { |
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mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; |
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if (tmp) |
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tmp = (*end) ? end+1 : end; |
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} |
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/* find the correct fdt ethernet path and correct it */ |
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node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000"); |
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if (node < 0) { |
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printf("no /soc/fman/ethernet path offset\n"); |
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return; |
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} |
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ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6); |
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if (ret) { |
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printf("error setting local-mac-address property\n"); |
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return; |
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} |
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} |
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#endif |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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phys_addr_t base; |
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phys_size_t size; |
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ft_cpu_setup(blob, bd); |
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base = getenv_bootm_low(); |
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size = getenv_bootm_size(); |
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fdt_fixup_memory(blob, (u64)base, (u64)size); |
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#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) |
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fdt_fixup_dr_usb(blob, bd); |
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#endif |
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#ifdef CONFIG_PCI |
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pci_of_setup(blob, bd); |
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#endif |
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fdt_fixup_liodn(blob); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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fdt_fixup_fman_ethernet(blob); |
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fdt_fixup_fman_mac_addresses(blob); |
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#endif |
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} |
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@ -0,0 +1,15 @@ |
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/*
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* (C) Copyright 2013 Keymile AG |
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* Valentin Longchamp <valentin.longchamp@keymile.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 |
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#define PRSTCFG_POWUP_UNIT_RST 0x1 |
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#define PRSTCFG_POWUP_RST 0x3 |
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void qrio_prst(u8 bit, bool en, bool wden); |
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void qrio_prstcfg(u8 bit, u8 mode); |
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void pci_of_setup(void *blob, bd_t *bd); |
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@ -0,0 +1,40 @@ |
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/*
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* (C) Copyright 2013 Keymile AG |
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* Valentin Longchamp <valentin.longchamp@keymile.com> |
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* |
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* Copyright 2008-2011 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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struct law_entry law_table[] = { |
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
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SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), |
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#endif |
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), |
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#endif |
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#ifdef CONFIG_SYS_DCSRBAR_PHYS |
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/* Limit DCSR to 32M to access NPC Trace Buffer */ |
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), |
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#endif |
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#ifdef CONFIG_SYS_NAND_BASE_PHYS |
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), |
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#endif |
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SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), |
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#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS |
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SET_LAW(CONFIG_SYS_LBAPP1_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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#endif |
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#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS |
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SET_LAW(CONFIG_SYS_LBAPP2_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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#endif |
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}; |
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int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,35 @@ |
||||
# |
||||
# Copyright 2012 Freescale Semiconductor, Inc. |
||||
# |
||||
# SPDX-License-Identifier: GPL-2.0+ |
||||
# |
||||
# Refer docs/README.pblimage for more details about how-to configure |
||||
# and create PBL boot image |
||||
# |
||||
|
||||
#PBI commands |
||||
#Initialize CPC1 as 1MB SRAM |
||||
09010000 00200400 |
||||
09138000 00000000 |
||||
091380c0 00000100 |
||||
09010100 00000000 |
||||
09010104 fff0000b |
||||
09010f00 08000000 |
||||
09010000 80000000 |
||||
#Configure LAW for CPC1 |
||||
09000d00 00000000 |
||||
09000d04 fff00000 |
||||
09000d08 81000013 |
||||
09000010 00000000 |
||||
09000014 ff000000 |
||||
09000018 81000000 |
||||
#Initialize eSPI controller, default configuration is slow for eSPI to |
||||
#load data, this configuration comes from u-boot eSPI driver. |
||||
09110000 80000403 |
||||
09110020 27170008 |
||||
09110024 00100008 |
||||
09110028 00100008 |
||||
0911002c 00100008 |
||||
#Flush PBL data |
||||
09138000 00000000 |
||||
091380c0 00000000 |
||||
@ -0,0 +1,35 @@ |
||||
/*
|
||||
* (C) Copyright 2013 Keymile AG |
||||
* Valentin Longchamp <valentin.longchamp@keymile.com> |
||||
* |
||||
* Copyright 2007-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
#include "kmp204x.h" |
||||
|
||||
#define PCIE_SW_RST 14 |
||||
#define HOOPER_SW_RST 12 |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
qrio_prst(PCIE_SW_RST, false, false); |
||||
qrio_prst(HOOPER_SW_RST, false, false); |
||||
/* Hooper is not direcly PCIe capable */ |
||||
mdelay(50); |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
||||
@ -0,0 +1,11 @@ |
||||
# |
||||
# Default RCW for kmp204x boards |
||||
# |
||||
|
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#64 bytes RCW data |
||||
14600000 00000000 28200000 00000000 |
||||
148E70CF CFC02000 58000000 41000000 |
||||
00000000 00000000 00000000 F4428002 |
||||
00000000 00000000 00000000 00000000 |
||||
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* (C) Copyright 2013 Keymile AG |
||||
* Valentin Longchamp <valentin.longchamp@keymile.com> |
||||
* |
||||
* Copyright 2008-2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
/* TLB 1 */ |
||||
/* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
|
||||
* SRAM is at 0xfff00000, it covered the 0xfffff000. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
/* QRIO */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_64K, 1), |
||||
/* *I*G* - PCI1 */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_512M, 1), |
||||
/* *I*G* - PCI3 */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_512M, 1), |
||||
/* *I*G* - PCI1&3 I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_128K, 1), |
||||
#ifdef CONFIG_SYS_LBAPP1_BASE_PHYS |
||||
/* LBAPP1 */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_LBAPP2_BASE_PHYS |
||||
/* LBAPP2 */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
/* Bman/Qman */ |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_1M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, |
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_1M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||
MAS3_SW|MAS3_SR, 0, |
||||
0, 11, BOOKE_PAGESZ_1M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, |
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 12, BOOKE_PAGESZ_1M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 13, BOOKE_PAGESZ_4M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
/*
|
||||
* *I*G - NAND |
||||
* entry 14 and 15 has been used hard coded, they will be disabled |
||||
* in cpu_init_f, so we use entry 16 for nand. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 16, BOOKE_PAGESZ_32K, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,450 @@ |
||||
/*
|
||||
* (C) Copyright 2013 Keymile AG |
||||
* Valentin Longchamp <valentin.longchamp@keymile.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_KMP204X_H |
||||
#define _CONFIG_KMP204X_H |
||||
|
||||
#define CONFIG_PHYS_64BIT |
||||
#define CONFIG_PPC_P2041 |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfff80000 |
||||
|
||||
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" |
||||
|
||||
#define CONFIG_NAND_ECC_BCH |
||||
|
||||
/* common KM defines */ |
||||
#include "keymile-common.h" |
||||
|
||||
#define CONFIG_SYS_RAMBOOT |
||||
#define CONFIG_RAMBOOT_PBL |
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
||||
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/keymile/kmp204x/pbi.cfg |
||||
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/keymile/kmp204x/rcw_kmp204x.cfg |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE |
||||
#define CONFIG_E500 /* BOOKE e500 family */ |
||||
#define CONFIG_E500MC /* BOOKE e500mc family */ |
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ |
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ |
||||
#define CONFIG_MP /* support multiple processors */ |
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ |
||||
#define CONFIG_PCI /* Enable PCI/PCIE */ |
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */ |
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */ |
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
||||
|
||||
#define CONFIG_SYS_DPAA_RMAN /* RMan */ |
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */ |
||||
|
||||
/* Environment in SPI Flash */ |
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_SPI_BUS 0 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 20000000 |
||||
#define CONFIG_ENV_SPI_MODE 0 |
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ |
||||
#define CONFIG_ENV_SIZE 0x004000 /* 16K env */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x010000 |
||||
#define CONFIG_ENV_OFFSET_REDUND 0x110000 |
||||
#define CONFIG_ENV_TOTAL_SIZE 0x020000 |
||||
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned long get_board_sys_clk(unsigned long dummy); |
||||
#endif |
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_SYS_CACHE_STASHING |
||||
#define CONFIG_BACKSIDE_L2_CACHE |
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS |
||||
|
||||
#define CONFIG_ADDR_MAP |
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
||||
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00800000 |
||||
#define CONFIG_SYS_ALT_MEMTEST |
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM |
||||
*/ |
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE |
||||
#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ |
||||
CONFIG_RAMBOOT_TEXT_BASE) |
||||
#define CONFIG_SYS_L3_SIZE (1024 << 10) |
||||
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) |
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000 |
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CONFIG_VERY_BIG_RAM |
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
||||
|
||||
#define CONFIG_DDR_SPD |
||||
#define CONFIG_FSL_DDR3 |
||||
#define CONFIG_FSL_DDR_INTERACTIVE |
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0 |
||||
#define SPD_EEPROM_ADDRESS 0x54 |
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
|
||||
/******************************************************************************
|
||||
* (PRAM usage) |
||||
* ... ------------------------------------------------------- |
||||
* ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM |
||||
* ... |<------------------- pram -------------------------->| |
||||
* ... ------------------------------------------------------- |
||||
* @END_OF_RAM: |
||||
* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose |
||||
* @CONFIG_KM_PHRAM: address for /var |
||||
* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) |
||||
* @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM |
||||
*/ |
||||
|
||||
/* size of rootfs in RAM */ |
||||
#define CONFIG_KM_ROOTFSSIZE 0x0 |
||||
/* pseudo-non volatile RAM [hex] */ |
||||
#define CONFIG_KM_PNVRAM 0x80000 |
||||
/* physical RAM MTD size [hex] */ |
||||
#define CONFIG_KM_PHRAM 0x100000 |
||||
/* resereved pram area at the end of memroy [hex] */ |
||||
#define CONFIG_KM_RESERVED_PRAM 0x0 |
||||
/* enable protected RAM */ |
||||
#define CONFIG_PRAM 0 |
||||
|
||||
#define CONFIG_KM_CRAMFS_ADDR 0x2000000 |
||||
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ |
||||
#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ |
||||
|
||||
#define CONFIG_BOOTCOUNT_LIMIT |
||||
|
||||
/*
|
||||
* Local Bus Definitions |
||||
*/ |
||||
|
||||
/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ |
||||
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) |
||||
|
||||
/* Nand Flash */ |
||||
#define CONFIG_NAND_FSL_ELBC |
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000 |
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
||||
|
||||
#define CONFIG_BCH |
||||
|
||||
/* NAND flash config */ |
||||
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */ |
||||
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ |
||||
| OR_FCM_BCTLD /* LBCTL not ass */ \
|
||||
| OR_FCM_SCY_1 /* 1 clk wait cycle */ \
|
||||
| OR_FCM_RST /* 1 clk read setup */ \
|
||||
| OR_FCM_PGS /* Large page size */ \
|
||||
| OR_FCM_CST) /* 0.25 command setup */ |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
||||
|
||||
/* QRIO FPGA */ |
||||
#define CONFIG_SYS_QRIO_BASE 0xfb000000 |
||||
#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull |
||||
|
||||
#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ |
||||
| BR_PS_8 /* Port Size 8 bits */ \
|
||||
| BR_DECC_OFF /* no error corr */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
|
||||
#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ |
||||
| OR_GPCM_BCTLD /* no LCTL assert */ \
|
||||
| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
|
||||
| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
|
||||
| OR_GPCM_TRLX /* relaxed tmgs */ \
|
||||
| OR_GPCM_EAD) /* extra bus clk cycles */ |
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ |
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_LAST_STAGE_INIT |
||||
|
||||
#define CONFIG_HWCONFIG |
||||
|
||||
/* define to use L1 as initial stack */ |
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CONFIG_SYS_INIT_RAM_LOCK |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR |
||||
/* The assembler doesn't like typecast */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) |
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2 |
||||
* shorted - index 1 |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1 |
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
||||
|
||||
#define CONFIG_KM_CONSOLE_TTY "ttyS0" |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS |
||||
|
||||
/* new uImage format support */ |
||||
#define CONFIG_FIT |
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_NUM_I2C_BUSES 3 |
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1 |
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 |
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
||||
#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ |
||||
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
|
||||
} |
||||
|
||||
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ |
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI |
||||
*/ |
||||
#define CONFIG_FSL_ESPI |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000 |
||||
#define CONFIG_SF_DEFAULT_MODE 0 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Memory space is mapped 1-1, but I/O space must start from 0. |
||||
*/ |
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 |
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull |
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||
|
||||
/* Qman/Bman */ |
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 |
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull |
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 |
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_SYS_DPAA_PME |
||||
/* Default address of microcode for the Linux Fman driver
|
||||
* env is stored at 0x100000, sector size is 0x10000, x2 (redundant) |
||||
* ucode is stored after env, so we got 0x120000. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x120000 |
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||
|
||||
#define CONFIG_FMAN_ENET |
||||
#define CONFIG_PHYLIB_10G |
||||
#define CONFIG_PHY_MARVELL /* there is a marvell phy */ |
||||
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_E1000 |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ |
||||
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 |
||||
#define CONFIG_SYS_TBIPA_VALUE 8 |
||||
#define CONFIG_PHYLIB /* recommended PHY management */ |
||||
#define CONFIG_ETHPRIME "FM1@DTSEC5" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* additionnal command line configuration. |
||||
*/ |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_NET |
||||
|
||||
/* we don't need flash support */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#undef CONFIG_CMD_IMLS |
||||
#undef CONFIG_CMD_FLASH |
||||
#undef CONFIG_FLASH_CFI_MTD |
||||
#undef CONFIG_JFFS2_CMDLINE |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
#define __USB_PHY_TYPE utmi |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ |
||||
#define CONFIG_KM_DEF_ENV "km-common=empty\0" |
||||
#endif |
||||
|
||||
#ifndef MTDIDS_DEFAULT |
||||
# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" |
||||
#endif /* MTDIDS_DEFAULT */ |
||||
|
||||
#ifndef MTDPARTS_DEFAULT |
||||
# define MTDPARTS_DEFAULT "mtdparts=" \ |
||||
"fsl_elbc_nand:" \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" |
||||
#endif /* MTDPARTS_DEFAULT */ |
||||
|
||||
/* architecture specific default bootargs */ |
||||
#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" |
||||
|
||||
/* FIXME: FDT_ADDR is unspecified */ |
||||
#define CONFIG_KM_DEF_ENV_CPU \ |
||||
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
|
||||
"cramfsloadfdt=" \
|
||||
"cramfsload ${fdt_addr_r} " \
|
||||
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
|
||||
"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
|
||||
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \
|
||||
"update=" \
|
||||
"sf probe 0;sf erase 0 +${filesize};" \
|
||||
"sf write ${load_addr_r} 0 ${filesize};\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_HW_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
|
||||
"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
|
||||
"usb_dr_mode=host\0" |
||||
|
||||
#define CONFIG_KM_NEW_ENV \ |
||||
"newenv=sf probe 0;" \
|
||||
"sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
|
||||
__stringify(CONFIG_ENV_TOTAL_SIZE)"\0" |
||||
|
||||
/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ |
||||
#ifndef CONFIG_KM_DEF_ARCH |
||||
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" |
||||
#endif |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_KM_DEF_ENV \
|
||||
CONFIG_KM_DEF_ARCH \
|
||||
CONFIG_KM_NEW_ENV \
|
||||
CONFIG_HW_ENV_SETTINGS \
|
||||
"EEprom_ivm=pca9547:70:9\0" \
|
||||
"" |
||||
|
||||
#endif /* _CONFIG_KMP204X_H */ |
||||
@ -0,0 +1,68 @@ |
||||
/*
|
||||
* (C) Copyright 2013 Keymile AG |
||||
* Valentin Longchamp <valentin.longchamp@keymile.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* KMLION1 */ |
||||
#if defined(CONFIG_KMLION1) |
||||
#define CONFIG_HOSTNAME kmlion1 |
||||
#define CONFIG_KM_BOARD_NAME "kmlion1" |
||||
|
||||
#else |
||||
#error ("Board not supported") |
||||
#endif |
||||
|
||||
#define CONFIG_KMP204X |
||||
|
||||
#include "km/kmp204x-common.h" |
||||
|
||||
#if defined(CONFIG_KMLION1) |
||||
/* App1 Local bus */ |
||||
#define CONFIG_SYS_LBAPP1_BASE 0xD0000000 |
||||
#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull |
||||
|
||||
#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \ |
||||
| BR_PS_8 /* Port Size 8 bits */ \
|
||||
| BR_DECC_OFF /* no error corr */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
|
||||
#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ |
||||
| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
|
||||
| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
|
||||
| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
|
||||
| OR_GPCM_TRLX /* relaxed tmgs */ \
|
||||
| OR_GPCM_EAD) /* extra bus clk cycles */ |
||||
/* Local bus app1 Base Address */ |
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM |
||||
/* Local bus app1 Options */ |
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM |
||||
|
||||
/* App2 Local bus */ |
||||
#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 |
||||
#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull |
||||
|
||||
#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ |
||||
| BR_PS_8 /* Port Size 8 bits */ \
|
||||
| BR_DECC_OFF /* no error corr */ \
|
||||
| BR_MS_GPCM /* MSEL = GPCM */ \
|
||||
| BR_V) /* valid */ |
||||
|
||||
#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ |
||||
| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
|
||||
| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
|
||||
| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
|
||||
| OR_GPCM_TRLX /* relaxed tmgs */ \
|
||||
| OR_GPCM_EAD) /* extra bus clk cycles */ |
||||
/* Local bus app2 Base Address */ |
||||
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM |
||||
/* Local bus app2 Options */ |
||||
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue