This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Grandegger <wg@denx.de>master
Masahiro Yamada
10 years ago
committed by
Tom Rini
parent
d2fd1d6623
commit
87882f5727
@ -1,9 +0,0 @@ |
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if TARGET_IPHASE4539 |
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config SYS_BOARD |
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default "iphase4539" |
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config SYS_CONFIG_NAME |
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default "IPHASE4539" |
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endif |
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@ -1,6 +0,0 @@ |
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IPHASE4539 BOARD |
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M: Wolfgang Grandegger <wg@denx.de> |
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S: Maintained |
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F: board/iphase4539/ |
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F: include/configs/IPHASE4539.h |
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F: configs/IPHASE4539_defconfig |
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@ -1,10 +0,0 @@ |
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := iphase4539.o flash.o
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@ -1,358 +0,0 @@ |
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This file contains basic information on the port of U-Boot to IPHASE4539 |
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(Interphase 4539 T1/E1/J1 PMC Communications Controller). |
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All the changes fit in the common U-Boot infrastructure, providing a new |
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IPHASE4539-specific entry in makefiles. To build U-Boot for IPHASE4539, |
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type "make IPHASE4539_config", edit the "include/config_IPHASE4539.h" |
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file if necessary, then type "make". |
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Common file modifications: |
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-------------------------- |
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The following common files have been modified by this project: |
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(starting from the ppcboot-1.1.5/ directory) |
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MAKEALL - IPHASE4539 entry added |
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Makefile - IPHASE4539_config entry added |
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New files: |
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---------- |
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The following new files have been added by this project: |
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(starting from the ppcboot-1.1.5/ directory) |
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board/iphase4539/ - board-specific directory |
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board/iphase4539/Makefile - board-specific makefile |
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board/iphase4539/config.mk - config file |
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board/iphase4539/flash.c - flash driver (for AM29LV033C) |
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board/iphase4539/ppcboot.lds - linker script |
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board/iphase4539/iphase4539.c - ioport and memory initialization |
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include/config_IPHASE4539.h - main configuration file |
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New configuration options: |
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-------------------------- |
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CONFIG_IPHASE4539 |
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Main board-specific option (should be defined for IPHASE4539). |
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Acceptance criteria tests: |
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-------------------------- |
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The following tests have been conducted to validate the port of U-Boot |
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to IPHASE4539: |
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1. Operation on serial console: |
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With SMC1 defined as console in the main configuration file, the U-Boot |
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output appeared on the serial terminal connected to the 2.5mm stereo jack |
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connector as follows: |
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------------------------------------------------------------------------------ |
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=> help |
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base - print or set address offset |
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bdinfo - print Board Info structure |
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bootm - boot application image from memory |
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bootp - boot image via network using BootP/TFTP protocol |
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bootd - boot default, i.e., run 'bootcmd' |
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cmp - memory compare |
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coninfo - print console devices and informations |
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cp - memory copy |
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crc32 - checksum calculation |
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dcache - enable or disable data cache |
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echo - echo args to console |
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erase - erase FLASH memory |
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flinfo - print FLASH memory information |
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go - start application at address 'addr' |
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help - print online help |
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icache - enable or disable instruction cache |
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iminfo - print header information for application image |
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loadb - load binary file over serial line (kermit mode) |
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loads - load S-Record file over serial line |
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loop - infinite loop on address range |
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md - memory display |
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mm - memory modify (auto-incrementing) |
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mtest - simple RAM test |
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mw - memory write (fill) |
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nm - memory modify (constant address) |
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printenv- print environment variables |
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protect - enable or disable FLASH write protection |
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rarpboot- boot image via network using RARP/TFTP protocol |
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reset - Perform RESET of the CPU |
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run - run commands in an environment variable |
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saveenv - save environment variables to persistent storage |
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setenv - set environment variables |
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sleep - delay execution for some time |
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source - run script from memory |
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tftpboot- boot image via network using TFTP protocol |
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and env variables ipaddr and serverip |
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version - print monitor version |
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? - alias for 'help' |
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=> |
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------------------------------------------------------------------------------ |
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2. Flash driver operation |
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The following sequence was performed to test the "flinfo" command: |
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------------------------------------------------------------------------------ |
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=> flinfo |
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Bank # 1: AMD AM29LV033C (32 Mbit, uniform sectors) |
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Size: 4 MB in 64 Sectors |
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Sector Start Addresses: |
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FF800000 (RO) FF810000 (RO) FF820000 FF830000 FF840000 |
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FF850000 FF860000 FF870000 FF880000 FF890000 |
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FF8A0000 FF8B0000 FF8C0000 FF8D0000 FF8E0000 |
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FF8F0000 FF900000 FF910000 FF920000 FF930000 |
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FF940000 FF950000 FF960000 FF970000 FF980000 |
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FF990000 FF9A0000 FF9B0000 FF9C0000 FF9D0000 |
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FF9E0000 FF9F0000 FFA00000 FFA10000 FFA20000 |
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FFA30000 FFA40000 FFA50000 FFA60000 FFA70000 |
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FFA80000 FFA90000 FFAA0000 FFAB0000 FFAC0000 |
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FFAD0000 FFAE0000 FFAF0000 FFB00000 (RO) FFB10000 (RO) |
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FFB20000 (RO) FFB30000 (RO) FFB40000 FFB50000 FFB60000 |
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FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000 |
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FFBC0000 FFBD0000 FFBE0000 FFBF0000 |
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------------------------------------------------------------------------------ |
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Note: the Hardware Configuration Word (HWC) of the 8260 is on the |
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first sector of the flash and should not be touched. The U-Boot |
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environment variables are stored on second sector and U-Boot |
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starts at the address 0xFFB00000. |
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The following sequence was performed to test the erase command: |
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------------------------------------------------------------------------------ |
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=> cp 0 ff880000 10 |
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Copy to Flash... done |
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=> md ff880000 20 |
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ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> erase ff880000 ff88ffff |
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Erase Flash from 0xff880000 to 0xff88ffff |
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.. done |
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Erased 1 sectors |
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=> md ff880000 |
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ff880000: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880010: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880020: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880030: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> cp 0 ff880000 10 |
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Copy to Flash... done |
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=> md ff880000 20 |
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ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> erase 1:8 |
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Erase Flash Sectors 8-8 in Bank # 1 |
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.. done |
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=> md ff880000 20 |
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ff880000: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880010: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880020: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880030: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> cp 0 ff880000 10 |
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Copy to Flash... done |
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=> cp 0 ff890000 10 |
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=> md ff880000 20 |
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ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> md ff890000 |
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ff890000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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ff890010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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ff890020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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ff890030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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ff890040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> erase 1:8-9 |
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Erase Flash Sectors 8-9 in Bank # 1 |
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.... done |
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=> md ff880000 20 |
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ff880000: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880010: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880020: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880030: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> md ff890000 |
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ff890000: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890010: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890020: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890030: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff890070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> |
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------------------------------------------------------------------------------ |
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The following sequence was performed to test the Flash programming commands: |
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------------------------------------------------------------------------------ |
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=> erase ff880000 ff88ffff |
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Erase Flash from 0xff880000 to 0xff88ffff |
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.. done |
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Erased 1 sectors |
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=> cp 0 ff880000 10 |
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Copy to Flash... done |
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=> md 0 20 |
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00000000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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00000010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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00000020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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00000030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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00000040: 3c83c000 2c040000 40823378 7c0000a6 <...,...@.3x|... |
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00000050: 60000030 7c1b03a6 3c00c000 600035ec `..0|...<...`.5. |
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00000060: 7c1a03a6 4c000064 00000000 00000000 |...L..d........ |
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00000070: 00000000 00000000 00000000 00000000 ................ |
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=> md ff880000 20 |
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ff880000: ff000000 60000000 60000000 7c7f1b78 ....`...`...|..x |
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ff880010: 7c9e2378 7cbd2b78 7cdc3378 7cfb3b78 |.#x|.+x|.3x|.;x |
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ff880020: 3b000000 4811e0f5 48003719 480036a5 ;...H...H.7.H.6. |
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ff880030: 480036f9 48003731 48005c5d 7c7a1b78 H.6.H.71H.\]|z.x |
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ff880040: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880050: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880060: ffffffff ffffffff ffffffff ffffffff ................ |
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ff880070: ffffffff ffffffff ffffffff ffffffff ................ |
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=> |
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------------------------------------------------------------------------------ |
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The following sequence was performed to test storage of the environment |
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variables in Flash: |
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------------------------------------------------------------------------------ |
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=> setenv foo bar |
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=> saveenv |
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Un-Protected 1 sectors |
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Erasing Flash... |
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.. done |
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Erased 1 sectors |
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Saving Environment to Flash... |
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Protected 1 sectors |
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=> reset |
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... |
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=> printenv |
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... |
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foo=bar |
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... |
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Environment size: 339/65532 bytes |
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=> |
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------------------------------------------------------------------------------ |
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The following sequence was performed to test image download and run over |
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Ethernet interface (both interfaces were tested): |
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------------------------------------------------------------------------------ |
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=> tftpboot 40000 hello_world.bin |
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ARP broadcast 1 |
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TFTP from server 10.0.0.1; our IP address is 10.0.0.8 |
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Filename 'hello_world.bin'. |
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Load address: 0x40000 |
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Loading: ############# |
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done |
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Bytes transferred = 65932 (1018c hex) |
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=> go 40004 |
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## Starting application at 0x00040004 ... |
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Hello World |
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argc = 1 |
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argv[0] = "40004" |
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argv[1] = "<NULL>" |
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Hit any key to exit ... |
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## Application terminated, rc = 0x0 |
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=> |
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------------------------------------------------------------------------------ |
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3. Known Problems |
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None for the moment. |
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---------------------------------------------------------------------------- |
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U-Boot and Linux for Interphase 4539 T1/E1/J1 PMC Communications Controller |
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---------------------------------------------------------------------------- |
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U-Boot: |
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Configure and make U-Boot: |
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$ cd <path>/u-boot |
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$ make IPHASE4539_config |
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$ make dep |
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$ make |
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$ cp -p u-boot.bin /tftpboot |
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Load u-boot.bin into the Flash memory at 0xffb00000. |
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Linux: |
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Configure and make Linux: |
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$ cd <patch>/linux-2.4 |
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$ make IPHASE4539_config |
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$ make oldconfig |
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$ make dep |
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$ make uImage |
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$ cp -p arch/powerpc/mbxboot/uImage /tftpboot |
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Load uImage via tftp and boot it. |
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Flash organisation: |
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The following preliminary layout of the Flash memory |
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is defined: |
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0xff800000 ( 0 - 64 kB): Hardware Configuration Word. |
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0xff810000 ( 64 kB - 128 kB): U-Boot Environment. |
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0xff820000 ( 128 kB - 3 MB): RAMdisk. |
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0xffb00000 ( 3 MB - 3328 kB): U-Boot. |
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0xffb40000 (3328 KB - 4 MB): Linux Kernel. |
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For further information concerning U-Boot and Linux please consult |
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the "DENX U-Boot and Linux Guide". |
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(C) 2002 Wolfgang Grandegger, DENX Software Engineering, wg@denx.de |
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=================================================================== |
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@ -1,474 +0,0 @@ |
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/*
|
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* (C) Copyright 2001 |
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
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* |
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* (C) Copyright 2002 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Adapted for Interphase 4539 by Wolfgang Grandegger <wg@denx.de>. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <flash.h> |
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#include <asm/io.h> |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; |
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extern int hwc_flash_size(void); |
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static ulong flash_get_size (u32 addr, flash_info_t *info); |
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static int flash_get_offsets (u32 base, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static void flash_reset (u32 addr); |
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#define out8(a,v) *(volatile unsigned char*)(a) = v |
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#define in8(a) *(volatile unsigned char*)(a) |
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#define in32(a) *(volatile unsigned long*)(a) |
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#define iobarrier_rw() eieio() |
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unsigned long flash_init (void) |
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{ |
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unsigned int i; |
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unsigned long flash_size = 0; |
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unsigned long bank_size; |
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unsigned int bank = 0; |
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/* Init: no FLASHes known */ |
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for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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flash_info[i].sector_count = 0; |
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flash_info[i].size = 0; |
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} |
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/* Initialise the BOOT Flash */ |
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if (bank == CONFIG_SYS_MAX_FLASH_BANKS) { |
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puts ("Warning: not all Flashes are initialised !"); |
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return flash_size; |
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} |
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bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank); |
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if (bank_size) { |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ |
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CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, |
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flash_info + bank); |
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#endif |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
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flash_info + bank); |
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#endif |
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|
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/* HWC protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_FLASH_BASE, |
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CONFIG_SYS_FLASH_BASE + 0x10000 - 1, |
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flash_info + bank); |
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|
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flash_size += bank_size; |
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bank++; |
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} else { |
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puts ("Warning: the BOOT Flash is not initialised !"); |
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} |
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|
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return flash_size; |
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} |
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|
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (u32 addr, flash_info_t *info) |
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{ |
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volatile uchar value; |
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#if 0 |
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int i; |
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#endif |
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|
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/* Write auto select command: read Manufacturer ID */ |
||||
out8(addr + 0x0555, 0xAA); |
||||
iobarrier_rw(); |
||||
udelay(10); |
||||
out8(addr + 0x02AA, 0x55); |
||||
iobarrier_rw(); |
||||
udelay(10); |
||||
out8(addr + 0x0555, 0x90); |
||||
iobarrier_rw(); |
||||
udelay(10); |
||||
|
||||
value = in8(addr); |
||||
iobarrier_rw(); |
||||
udelay(10); |
||||
switch (value | (value << 16)) { |
||||
case AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
|
||||
case FUJ_MANUFACT: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
flash_reset (addr); |
||||
return 0; |
||||
} |
||||
|
||||
value = in8(addr + 1); /* device ID */ |
||||
iobarrier_rw(); |
||||
|
||||
switch (value) { |
||||
case AMD_ID_LV033C: |
||||
info->flash_id += FLASH_AM033C; |
||||
info->size = hwc_flash_size(); |
||||
if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) { |
||||
printf("U-Boot supports only %d MB\n", |
||||
CONFIG_SYS_MAX_FLASH_SIZE); |
||||
info->size = CONFIG_SYS_MAX_FLASH_SIZE; |
||||
} |
||||
info->sector_count = info->size / 0x10000; |
||||
break; /* => 4 MB */ |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
flash_reset (addr); |
||||
return (0); /* => no or unknown flash */ |
||||
|
||||
} |
||||
|
||||
if (!flash_get_offsets (addr, info)) { |
||||
flash_reset (addr); |
||||
return 0; |
||||
} |
||||
|
||||
#if 0 |
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
||||
value = in8(info->start[i] + 2); |
||||
iobarrier_rw(); |
||||
info->protect[i] = (value & 1) != 0; |
||||
} |
||||
#endif |
||||
|
||||
/*
|
||||
* Reset bank to read mode |
||||
*/ |
||||
flash_reset (addr); |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
static int flash_get_offsets (u32 base, flash_info_t *info) |
||||
{ |
||||
unsigned int i, size; |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM033C: |
||||
/* set sector offsets for uniform sector type */ |
||||
size = info->size / info->sector_count; |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
info->start[i] = base + i * size; |
||||
} |
||||
break; |
||||
default: |
||||
return 0; |
||||
} |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
volatile u32 addr = info->start[0]; |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
if (s_first < 0 || s_first > s_last) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN || |
||||
info->flash_id > FLASH_AMD_COMP) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
out8(addr + 0x555, 0xAA); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x2AA, 0x55); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x555, 0x80); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x555, 0xAA); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x2AA, 0x55); |
||||
iobarrier_rw(); |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = info->start[sect]; |
||||
out8(addr, 0x30); |
||||
iobarrier_rw(); |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = info->start[l_sect]; |
||||
while ((in8(addr) & 0x80) != 0x80) { |
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
iobarrier_rw(); |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
flash_reset (info->start[0]); |
||||
|
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
volatile u32 addr = info->start[0]; |
||||
ulong start; |
||||
int flag, i; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((in32(dest) & data) != data) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
/* first, perform an unlock bypass command to speed up flash writes */ |
||||
out8(addr + 0x555, 0xAA); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x2AA, 0x55); |
||||
iobarrier_rw(); |
||||
out8(addr + 0x555, 0x20); |
||||
iobarrier_rw(); |
||||
|
||||
/* write each byte out */ |
||||
for (i = 0; i < 4; i++) { |
||||
char *data_ch = (char *)&data; |
||||
out8(addr, 0xA0); |
||||
iobarrier_rw(); |
||||
out8(dest+i, data_ch[i]); |
||||
iobarrier_rw(); |
||||
udelay(10); /* XXX */ |
||||
} |
||||
|
||||
/* we're done, now do an unlock bypass reset */ |
||||
out8(addr, 0x90); |
||||
iobarrier_rw(); |
||||
out8(addr, 0x00); |
||||
iobarrier_rw(); |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { |
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
iobarrier_rw(); |
||||
} |
||||
|
||||
flash_reset (addr); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* Reset bank to read mode |
||||
*/ |
||||
static void flash_reset (u32 addr) |
||||
{ |
||||
out8(addr, 0xF0); /* reset bank */ |
||||
iobarrier_rw(); |
||||
} |
||||
|
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM033C: printf ("AM29LV033C (32 Mbit, uniform sectors)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
if (info->size % 0x100000 == 0) { |
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size / 0x100000, info->sector_count); |
||||
} |
||||
else if (info->size % 0x400 == 0) { |
||||
printf (" Size: %ld KB in %d Sectors\n", |
||||
info->size / 0x400, info->sector_count); |
||||
} |
||||
else { |
||||
printf (" Size: %ld B in %d Sectors\n", |
||||
info->size, info->sector_count); |
||||
} |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
} |
||||
@ -1,408 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ioports.h> |
||||
#include <mpc8260.h> |
||||
#include <asm/io.h> |
||||
#include <asm/immap_8260.h> |
||||
|
||||
int hwc_flash_size (void); |
||||
int hwc_local_sdram_size (void); |
||||
int hwc_main_sdram_size (void); |
||||
int hwc_serial_number (void); |
||||
int hwc_mac_address (char *str); |
||||
int hwc_manufact_date (char *str); |
||||
int seeprom_read (int addr, uchar * data, int size); |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
* |
||||
* The port definitions are taken from the old firmware (see |
||||
* also SYS/H/4539.H): |
||||
* |
||||
* ppar psor pdir podr pdat |
||||
* PA: 0x02ffffff 0x02c00000 0xfc403fe6 0x00000000 0x02403fc0 |
||||
* PB: 0x0fffdeb0 0x000000b0 0x0f032347 0x00000000 0x0f000290 |
||||
* PC: 0x030ffa55 0x030f0040 0xbcf005ea 0x00000000 0xc0c0ba7d |
||||
* PD: 0x09c04e3c 0x01000e3c 0x0a7ff1c3 0x00000000 0x00ce0ae9 |
||||
*/ |
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA31 FCC1_TXENB SLAVE */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA30 FCC1_TXCLAV SLAVE */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA29 FCC1_TXSOC */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA28 FCC1_RXENB SLAVE */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA27 FCC1_RXSOC */ |
||||
{0, 1, 0, 1, 0, 0}, /* PA26 FCC1_RXCLAV SLAVE */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA25 FCC1_TXD0 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA24 FCC1_TXD1 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA23 FCC1_TXD2 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA22 FCC1_TXD3 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA21 FCC1_TXD4 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA20 FCC1_TXD5 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA19 FCC1_TXD6 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PA18 FCC1_TXD7 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA17 FCC1_RXD7 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA16 FCC1_RXD6 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA15 FCC1_RXD5 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA14 FCC1_RXD4 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA13 FCC1_RXD3 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA12 FCC1_RXD2 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA11 FCC1_RXD1 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PA10 FCC1_RXD0 */ |
||||
{0, 1, 1, 1, 0, 1}, /* PA9 TDMA1_L1TXD */ |
||||
{0, 1, 1, 0, 0, 0}, /* PA8 TDMA1_L1RXD */ |
||||
{0, 0, 0, 0, 0, 0}, /* PA7 CONFIG0 */ |
||||
{0, 1, 1, 0, 0, 1}, /* PA6 TDMA1_L1RSYNC */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA5 FCC2:RxAddr[2] */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA4 FCC2:RxAddr[1] */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA3 FCC2:RxAddr[0] */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA2 FCC2:TxAddr[0] */ |
||||
{0, 0, 0, 1, 0, 0}, /* PA1 FCC2:TxAddr[1] */ |
||||
{0, 0, 0, 1, 0, 0} /* PA0 FCC2:TxAddr[2] */ |
||||
}, |
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB31 FCC2_RXSOC */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB30 FCC2_TXSOC */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB29 FCC2_RXCLAV */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB28 CONFIG2 */ |
||||
{0, 1, 1, 0, 0, 1}, /* PB27 FCC2_TXD0 */ |
||||
{0, 1, 1, 0, 0, 0}, /* PB26 FCC2_TXD1 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB25 FCC2_TXD4 */ |
||||
{0, 1, 1, 0, 0, 1}, /* PB24 FCC2_TXD5 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB23 FCC2_TXD6 */ |
||||
{0, 1, 0, 1, 0, 1}, /* PB22 FCC2_TXD7 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PB21 FCC2_RXD7 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PB20 FCC2_RXD6 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PB19 FCC2_RXD5 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PB18 FCC2_RXD4 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB17 FCC3_RX_DV */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB16 FCC3_RX_ER */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB15 FCC3_TX_ER */ |
||||
{1, 1, 0, 1, 0, 0}, /* PB14 FCC3_TX_EN */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB13 FCC3_COL */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB12 FCC3_CRS */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB11 FCC3_RXD3 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB10 FCC3_RXD2 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB9 FCC3_RXD1 */ |
||||
{1, 1, 0, 0, 0, 0}, /* PB8 FCC3_RXD0 */ |
||||
{1, 1, 0, 1, 0, 1}, /* PB7 FCC3_TXD0 */ |
||||
{1, 1, 0, 1, 0, 1}, /* PB6 FCC3_TXD1 */ |
||||
{1, 1, 0, 1, 0, 1}, /* PB5 FCC3_TXD2 */ |
||||
{1, 1, 0, 1, 0, 1}, /* PB4 FCC3_TXD3 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB3 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB2 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB1 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PB0 */ |
||||
}, |
||||
/* Port C configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC31 CLK1 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC30 U1MASTER_N */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC29 CLK3 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC28 -MT90220_RST */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC27 CLK5 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC26 -QUADFALC_RST */ |
||||
{0, 1, 1, 1, 0, 1}, /* PC25 BRG4 */ |
||||
{1, 0, 0, 1, 0, 0}, /* PC24 MDIO */ |
||||
{1, 0, 0, 1, 0, 0}, /* PC23 MDC */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC22 CLK10 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC21 */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC20 CLK12 */ |
||||
{0, 1, 0, 0, 0, 1}, /* PC19 CLK13 */ |
||||
{1, 1, 0, 0, 0, 1}, /* PC18 CLK14 */ |
||||
{0, 1, 0, 0, 0, 0}, /* PC17 CLK15 */ |
||||
{1, 1, 0, 0, 0, 1}, /* PC16 CLK16 */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC15 FCC1_TXADDR0 SLAVE */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC14 FCC1_RXADDR0 SLAVE */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC13 FCC1_TXADDR1 SLAVE */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC12 FCC1_RXADDR1 SLAVE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC11 FCC2_RXD2 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC10 FCC2_RXD3 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC9 LTMODE */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC8 SELSYNC */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC7 FCC1_TXADDR2 SLAVE */ |
||||
{0, 1, 1, 0, 0, 0}, /* PC6 FCC1_RXADDR2 SLAVE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC5 FCC2_TXCLAV MASTER */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC4 FCC2_RXENB MASTER */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC3 FCC2_TXD2 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PC2 FCC2_TXD3 */ |
||||
{0, 0, 0, 0, 0, 1}, /* PC1 PTMC -PTEENB */ |
||||
{0, 0, 0, 1, 0, 1}, /* PC0 COMCLK_N */ |
||||
}, |
||||
/* Port D configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD31 -CAM_RST */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD30 FCC2_TXENB */ |
||||
{0, 1, 1, 0, 0, 0}, /* PD29 FCC1_RXADDR3 SLAVE */ |
||||
{0, 1, 1, 0, 0, 1}, /* PD28 TDMC1_L1TXD */ |
||||
{0, 1, 1, 0, 0, 0}, /* PD27 TDMC1_L1RXD */ |
||||
{0, 1, 1, 0, 0, 1}, /* PD26 TDMC1_L1RSYNC */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD25 LED0 -OFF */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD24 LED5 -OFF */ |
||||
{1, 0, 0, 1, 0, 1}, /* PD23 -LXT971_RST */ |
||||
{0, 1, 1, 0, 0, 1}, /* PD22 TDMA2_L1TXD */ |
||||
{0, 1, 1, 0, 0, 0}, /* PD21 TDMA2_L1RXD */ |
||||
{0, 1, 1, 0, 0, 1}, /* PD20 TDMA2_L1RSYNC */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD19 FCC2_TXADDR3 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD18 FCC2_RXADDR3 */ |
||||
{0, 1, 0, 1, 0, 0}, /* PD17 BRG2 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD16 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD15 PT2TO1 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD14 PT4TO3 */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD13 -SWMODE */ |
||||
{0, 0, 0, 1, 0, 1}, /* PD12 -PTMODE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD11 FCC2_RXD0 */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD10 FCC2_RXD1 */ |
||||
{1, 1, 0, 1, 0, 1}, /* PD9 SMC1_SMTXD */ |
||||
{1, 1, 0, 0, 0, 1}, /* PD8 SMC1_SMRXD */ |
||||
{0, 1, 1, 0, 0, 0}, /* PD7 FCC1_TXADDR3 SLAVE */ |
||||
{0, 0, 0, 1, 0, 0}, /* PD6 IMAMODE */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD5 CONFIG2 */ |
||||
{0, 1, 0, 1, 0, 0}, /* PD4 BRG8 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD3 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD2 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD1 */ |
||||
{0, 0, 0, 0, 0, 0}, /* PD0 */ |
||||
} |
||||
}; |
||||
|
||||
phys_size_t initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
||||
volatile memctl8260_t *memctl = &immap->im_memctl; |
||||
volatile uchar *base; |
||||
ulong maxsize; |
||||
int i; |
||||
|
||||
memctl->memc_psrt = CONFIG_SYS_PSRT; |
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
||||
|
||||
#ifndef CONFIG_SYS_RAMBOOT |
||||
immap->im_siu_conf.sc_ppc_acr = 0x00000026; |
||||
immap->im_siu_conf.sc_ppc_alrh = 0x01276345; |
||||
immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; |
||||
immap->im_siu_conf.sc_lcl_acr = 0x00000000; |
||||
immap->im_siu_conf.sc_lcl_alrh = 0x01234567; |
||||
immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF; |
||||
immap->im_siu_conf.sc_tescr1 = 0x00004000; |
||||
immap->im_siu_conf.sc_ltescr1 = 0x00004000; |
||||
|
||||
/* Init Main SDRAM */ |
||||
#define OP_VALUE 0x404A241A |
||||
#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); |
||||
base = (uchar *) CONFIG_SYS_SDRAM_BASE; |
||||
memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; |
||||
*base = 0xFF; |
||||
memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; |
||||
for (i = 0; i < 8; i++) |
||||
*base = 0xFF; |
||||
memctl->memc_psdmr = 0x18000000 | OP_VALUE_M; |
||||
*(base + 0x110) = 0xFF; |
||||
memctl->memc_psdmr = OP_VALUE; |
||||
memctl->memc_lsdmr = 0x4086A522; |
||||
*base = 0xFF; |
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be |
||||
* mapped by the controller. That means, that the initial mapping has |
||||
* to be (at least) twice as large as the maximum expected size. |
||||
*/ |
||||
maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2; |
||||
|
||||
maxsize = get_ram_size((long *)base, maxsize); |
||||
|
||||
memctl->memc_or1 |= ~(maxsize - 1); |
||||
|
||||
if (maxsize != hwc_main_sdram_size ()) |
||||
printf ("Oops: memory test has not found all memory!\n"); |
||||
#endif |
||||
|
||||
icache_enable (); |
||||
/* return total ram size of SDRAM */ |
||||
return (maxsize); |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char string[32]; |
||||
|
||||
hwc_manufact_date (string); |
||||
|
||||
printf ("Board: Interphase 4539 (#%d %s)\n", |
||||
hwc_serial_number (), |
||||
string); |
||||
|
||||
#ifdef DEBUG |
||||
printf ("Manufacturing date: %s\n", string); |
||||
printf ("Serial number : %d\n", hwc_serial_number ()); |
||||
printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20); |
||||
printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20); |
||||
printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20); |
||||
hwc_mac_address (string); |
||||
printf ("MAC address : %s\n", string); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
char *s, str[32]; |
||||
int num; |
||||
|
||||
if ((s = getenv ("serial#")) == NULL && |
||||
(num = hwc_serial_number ()) != -1) { |
||||
sprintf (str, "%06d", num); |
||||
setenv ("serial#", str); |
||||
} |
||||
if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) { |
||||
setenv ("ethaddr", str); |
||||
} |
||||
return (0); |
||||
} |
||||
|
||||
/***************************************************************
|
||||
* We take some basic Hardware Configuration Parameter from the |
||||
* Serial EEPROM conected to the PSpan bridge. We keep it as |
||||
* simple as possible. |
||||
*/ |
||||
int hwc_flash_size (void) |
||||
{ |
||||
uchar byte; |
||||
|
||||
if (!seeprom_read (0x40, &byte, sizeof (byte))) { |
||||
switch ((byte >> 2) & 0x3) { |
||||
case 0x1: |
||||
return 0x0400000; |
||||
break; |
||||
case 0x2: |
||||
return 0x0800000; |
||||
break; |
||||
case 0x3: |
||||
return 0x1000000; |
||||
default: |
||||
return 0x0100000; |
||||
} |
||||
} |
||||
return -1; |
||||
} |
||||
int hwc_local_sdram_size (void) |
||||
{ |
||||
uchar byte; |
||||
|
||||
if (!seeprom_read (0x40, &byte, sizeof (byte))) { |
||||
switch ((byte & 0x03)) { |
||||
case 0x1: |
||||
return 0x0800000; |
||||
case 0x2: |
||||
return 0x1000000; |
||||
default: |
||||
return 0; /* not present */ |
||||
} |
||||
} |
||||
return -1; |
||||
} |
||||
int hwc_main_sdram_size (void) |
||||
{ |
||||
uchar byte; |
||||
|
||||
if (!seeprom_read (0x41, &byte, sizeof (byte))) { |
||||
return 0x1000000 << ((byte >> 5) & 0x7); |
||||
} |
||||
return -1; |
||||
} |
||||
int hwc_serial_number (void) |
||||
{ |
||||
int sn = -1; |
||||
|
||||
if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) { |
||||
sn = cpu_to_le32 (sn); |
||||
} |
||||
return sn; |
||||
} |
||||
int hwc_mac_address (char *str) |
||||
{ |
||||
char mac[6]; |
||||
|
||||
if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) { |
||||
sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n", |
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
||||
} else { |
||||
strcpy (str, "ERROR"); |
||||
return -1; |
||||
} |
||||
return 0; |
||||
} |
||||
int hwc_manufact_date (char *str) |
||||
{ |
||||
uchar byte; |
||||
int value; |
||||
|
||||
if (seeprom_read (0x92, &byte, sizeof (byte))) |
||||
goto out; |
||||
value = byte; |
||||
if (seeprom_read (0x93, &byte, sizeof (byte))) |
||||
goto out; |
||||
value += byte << 8; |
||||
sprintf (str, "%02d/%02d/%04d", |
||||
value & 0x1F, (value >> 5) & 0xF, |
||||
1980 + ((value >> 9) & 0x1FF)); |
||||
return 0; |
||||
|
||||
out: |
||||
strcpy (str, "ERROR"); |
||||
return -1; |
||||
} |
||||
|
||||
#define PSPAN_ADDR 0xF0020000 |
||||
#define EEPROM_REG 0x408 |
||||
#define EEPROM_READ_CMD 0xA000 |
||||
#define PSPAN_WRITE(a,v) \ |
||||
*((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio() |
||||
#define PSPAN_READ(a) \ |
||||
*((volatile unsigned long *)(PSPAN_ADDR+(a))) |
||||
|
||||
int seeprom_read (int addr, uchar * data, int size) |
||||
{ |
||||
ulong val, cmd; |
||||
int i; |
||||
|
||||
for (i = 0; i < size; i++) { |
||||
|
||||
cmd = EEPROM_READ_CMD; |
||||
cmd |= ((addr + i) << 24) & 0xff000000; |
||||
|
||||
/* Wait for ACT to authorize write */ |
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) |
||||
eieio (); |
||||
|
||||
/* Write command */ |
||||
PSPAN_WRITE (EEPROM_REG, cmd); |
||||
|
||||
/* Wait for data to be valid */ |
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) |
||||
eieio (); |
||||
/* Do it twice, first read might be erratic */ |
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80) |
||||
eieio (); |
||||
|
||||
/* Read error */ |
||||
if (val & 0x00000040) { |
||||
return -1; |
||||
} else { |
||||
data[i] = (val >> 16) & 0xff; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC8260=y |
||||
CONFIG_TARGET_IPHASE4539=y |
||||
@ -1,328 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> |
||||
* |
||||
* This file is based on similar values for other boards found in |
||||
* other U-Boot config files, mainly tqm8260.h and mpc8260ads.h. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xffb00000 |
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* select serial console configuration |
||||
* |
||||
* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
* |
||||
* if CONFIG_CONS_NONE is defined, then the serial console routines must |
||||
* defined elsewhere (for example, on the cogent platform, there are serial |
||||
* ports on the motherboard which are used for the serial console - see |
||||
* cogent/cma101/serial.[ch]). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
||||
#undef CONFIG_CONS_NONE /* define if console on something else */ |
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* select ethernet configuration |
||||
* |
||||
* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
||||
* for FCC) |
||||
* |
||||
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
||||
* defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 3 /* which channel for ether */ |
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* - Rx-CLK is CLK14 |
||||
* - Tx-CLK is CLK16 |
||||
* - Select bus for bd/buffers (see 28-13) |
||||
* - Half duplex |
||||
*/ |
||||
# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) |
||||
# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16) |
||||
# define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
||||
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ |
||||
|
||||
/* other options */ |
||||
|
||||
#define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
||||
#define CONFIG_BAUDRATE 19200 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
|
||||
/*
|
||||
* select i2c support configuration |
||||
* |
||||
* Supported configurations are {none, software, hardware} drivers. |
||||
* If the software driver is chosen, there are some additional |
||||
* configuration items that the driver uses to drive the port pins. |
||||
*/ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
||||
#define CONFIG_SYS_I2C_SOFT_SPEED 400000 |
||||
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000) |
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0) |
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
||||
else iop->pdat &= ~0x00010000 |
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
||||
else iop->pdat &= ~0x00020000 |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */ |
||||
/* for versions < 2.4.5-pre5 */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0x04400000 |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration (Setup by the |
||||
* startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0. |
||||
*/ |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_FLASH_BASE 0xFF800000 |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */ |
||||
#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
/* Environment in FLASH, there is little space left in Serial EEPROM */ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words |
||||
* |
||||
* if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
||||
* defines for the various registers affected by the HRCW e.g. changing |
||||
* HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
||||
*/ |
||||
#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\ |
||||
( HRCW_L2CPC10 | HRCW_ISB110 ) |\
|
||||
( HRCW_MMR11 | HRCW_APPC10 ) |\
|
||||
( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
|
||||
) /* 0x14863245 */ |
||||
|
||||
/* no slaves */ |
||||
#define CONFIG_SYS_HRCW_SLAVE1 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE2 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE3 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE4 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE5 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE6 0 |
||||
#define CONFIG_SYS_HRCW_SLAVE7 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11 |
||||
*----------------------------------------------------------------------- |
||||
* HID0 also contains cache control. |
||||
* |
||||
* HID1 has only read-only information - nothing to set. |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
||||
HID0_IFEM|HID0_ABE) |
||||
#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) |
||||
#define CONFIG_SYS_HID2 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5 |
||||
*----------------------------------------------------------------------- |
||||
* turn on Checkstop Reset Enable |
||||
*/ |
||||
#define CONFIG_SYS_RMR RMR_CSRE |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_BCR 0xA01C0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_SIUMCR 0X4205C000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
||||
*/ |
||||
#if defined (CONFIG_WATCHDOG) |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
||||
#else |
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
||||
SYPCR_SWRI|SYPCR_SWP) |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40 |
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
||||
* and enable Time Counter |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
||||
* Periodic timer |
||||
*/ |
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8 |
||||
*----------------------------------------------------------------------- |
||||
* Ensure DFBRG is Divide by 16 |
||||
*/ |
||||
#define CONFIG_SYS_SCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_SYS_RCCR 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Init Memory Controller: |
||||
* |
||||
* Bank Bus Machine PortSz Device |
||||
* ---- --- ------- ------ ------ |
||||
* 0 60x GPCM 64 bit FLASH |
||||
* 1 60x SDRAM 64 bit SDRAM |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801) |
||||
#define CONFIG_SYS_OR0_PRELIM 0xFF800882 |
||||
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041) |
||||
#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0 |
||||
|
||||
#define CONFIG_SYS_PSDMR 0x404A241A |
||||
#define CONFIG_SYS_MPTPR 0x00007400 |
||||
#define CONFIG_SYS_PSRT 0x00000007 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue