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@ -19,32 +19,12 @@ |
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static int pci_ivybridge_probe(struct udevice *bus) |
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{ |
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struct pci_controller *hose = dev_get_uclass_priv(bus); |
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pci_dev_t dev; |
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u16 reg16; |
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if (!(gd->flags & GD_FLG_RELOC)) |
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return 0; |
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post_code(0x50); |
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bd82x6x_init_extra(); |
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post_code(0x51); |
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reg16 = 0xff; |
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dev = PCH_DEV; |
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reg16 = x86_pci_read_config16(dev, PCI_COMMAND); |
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
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x86_pci_write_config16(dev, PCI_COMMAND, reg16); |
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/*
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* Clear non-reserved bits in status register. |
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*/ |
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
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pci_write_bar32(hose, dev, 0, 0xf0000000); |
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post_code(0x52); |
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return 0; |
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} |
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