Tom Rini
10 years ago
commit
891b487098
@ -0,0 +1,29 @@ |
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Zynq SPI controller Device Tree Bindings |
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---------------------------------------- |
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|
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Required properties: |
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- compatible : Should be "xlnx,spi-zynq". |
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- reg : Physical base address and size of SPI registers map. |
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- status : Status will be disabled in dtsi and enabled in required dts. |
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- interrupt-parent : Must be core interrupt controller. |
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- interrupts : Property with a value describing the interrupt |
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number. |
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- clocks : Clock phandles (see clock bindings for details). |
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- clock-names : List of input clock names - "ref_clk", "pclk" |
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(See clock bindings for details). |
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- spi-max-frequency : Maximum SPI clocking speed of device in Hz |
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|
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Example: |
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spi@e0006000 { |
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compatible = "xlnx,zynq-spi"; |
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reg = <0xe0006000 0x1000>; |
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status = "disabled"; |
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interrupt-parent = <&intc>; |
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interrupts = <0 26 4>; |
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clocks = <&clkc 25>, <&clkc 34>; |
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clock-names = "ref_clk", "pclk"; |
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spi-max-frequency = <166666700>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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} ; |
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@ -1,284 +0,0 @@ |
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/*
|
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* Driver of Andes SPI Controller |
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* |
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* (C) Copyright 2011 Andes Technology |
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* Macpaul Lin <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <malloc.h> |
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#include <spi.h> |
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|
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#include <asm/io.h> |
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#include "andes_spi.h" |
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|
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void spi_init(void) |
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{ |
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/* do nothing */ |
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} |
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|
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static void andes_spi_spit_en(struct andes_spi_slave *ds) |
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{ |
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unsigned int dcr = readl(&ds->regs->dcr); |
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debug("%s: dcr: %x, write value: %x\n", |
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__func__, dcr, (dcr | ANDES_SPI_DCR_SPIT)); |
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writel((dcr | ANDES_SPI_DCR_SPIT), &ds->regs->dcr); |
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} |
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|
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct andes_spi_slave *ds; |
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if (!spi_cs_is_valid(bus, cs)) |
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return NULL; |
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ds = spi_alloc_slave(struct andes_spi_slave, bus, cs); |
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if (!ds) |
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return NULL; |
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ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE; |
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|
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/*
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* The hardware of andes_spi will set its frequency according |
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* to APB/AHB bus clock. Hence the hardware doesn't allow changing of |
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* requency and so the user requested speed is always ignored. |
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*/ |
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ds->freq = max_hz; |
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return &ds->slave; |
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} |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct andes_spi_slave *ds = to_andes_spi(slave); |
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free(ds); |
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} |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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struct andes_spi_slave *ds = to_andes_spi(slave); |
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unsigned int apb; |
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unsigned int baud; |
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/* Enable the SPI hardware */ |
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writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr); |
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udelay(1000); |
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|
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/* setup format */ |
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baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) & 0xFF; |
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/*
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* SPI_CLK = AHB bus clock / ((BAUD + 1)*2) |
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* BAUD = AHB bus clock / SPI_CLK / 2) - 1 |
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*/ |
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apb = (readl(&ds->regs->apb) & 0xffffff00) | baud; |
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writel(apb, &ds->regs->apb); |
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/* no interrupts */ |
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writel(0, &ds->regs->ie); |
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return 0; |
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} |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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struct andes_spi_slave *ds = to_andes_spi(slave); |
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|
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/* Disable the SPI hardware */ |
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writel(ANDES_SPI_CR_SPIRST, &ds->regs->cr); |
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} |
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static int andes_spi_read(struct spi_slave *slave, unsigned int len, |
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u8 *rxp, unsigned long flags) |
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{ |
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struct andes_spi_slave *ds = to_andes_spi(slave); |
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unsigned int i, left; |
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unsigned int data; |
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debug("%s: slave: %x, len: %d, rxp: %x, flags: %d\n", |
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__func__, slave, len, rxp, flags); |
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debug("%s: data: ", __func__); |
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while (len > 0) { |
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left = min(len, 4); |
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data = readl(&ds->regs->data); |
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debug(" "); |
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for (i = 0; i < left; i++) { |
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debug("%02x ", data & 0xff); |
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*rxp++ = data; |
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data >>= 8; |
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len--; |
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} |
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} |
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debug("\n"); |
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return 0; |
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} |
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static int andes_spi_write(struct spi_slave *slave, unsigned int wlen, |
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unsigned int rlen, const u8 *txp, unsigned long flags) |
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{ |
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struct andes_spi_slave *ds = to_andes_spi(slave); |
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unsigned int data; |
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unsigned int i, left; |
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unsigned int spit_enabled = 0; |
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debug("%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n", |
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__func__, slave, wlen, rlen, txp, flags); |
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/* The value of wlen and rlen wrote to register must minus 1 */ |
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if (rlen == 0) /* write only */ |
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writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) | |
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ANDES_SPI_DCR_RCNT(0), &ds->regs->dcr); |
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else /* write then read */ |
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writel(ANDES_SPI_DCR_MODE_WR | ANDES_SPI_DCR_WCNT(wlen-1) | |
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ANDES_SPI_DCR_RCNT(rlen-1), &ds->regs->dcr); |
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/* wait till SPIBSY is cleared */ |
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while (readl(&ds->regs->st) & ANDES_SPI_ST_SPIBSY) |
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; |
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/* data write process */ |
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debug("%s: txp: ", __func__); |
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while (wlen > 0) { |
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/* clear the data */ |
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data = 0; |
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/* data are usually be read 32bits once a time */ |
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left = min(wlen, 4); |
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for (i = 0; i < left; i++) { |
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debug("%x ", *txp); |
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data |= *txp++ << (i * 8); |
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wlen--; |
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} |
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debug("\n"); |
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debug("data: %08x\n", data); |
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debug("streg before write: %08x\n", readl(&ds->regs->st)); |
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/* wait till TXFULL is deasserted */ |
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while (readl(&ds->regs->st) & ANDES_SPI_ST_TXFEL) |
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; |
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writel(data, &ds->regs->data); |
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debug("streg after write: %08x\n", readl(&ds->regs->st)); |
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if (spit_enabled == 0) { |
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/* enable SPIT bit - trigger the tx and rx progress */ |
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andes_spi_spit_en(ds); |
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spit_enabled = 1; |
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} |
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} |
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debug("\n"); |
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return 0; |
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} |
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/*
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* spi_xfer: |
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* Since andes_spi doesn't support independent command transaction, |
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* that is, write and than read must be operated in continuous |
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* execution, there is no need to set dcr and trigger spit again in |
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* RX process. |
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*/ |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
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const void *dout, void *din, unsigned long flags) |
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{ |
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unsigned int len; |
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static int op_nextime; |
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static u8 tmp_cmd[5]; |
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static int tmp_wlen; |
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unsigned int i; |
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if (bitlen == 0) |
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/* Finish any previously submitted transfers */ |
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goto out; |
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if (bitlen % 8) { |
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/* Errors always terminate an ongoing transfer */ |
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flags |= SPI_XFER_END; |
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goto out; |
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} |
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len = bitlen / 8; |
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debug("%s: slave: %08x, bitlen: %d, dout: " |
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"%08x, din: %08x, flags: %d, len: %d\n", |
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__func__, slave, bitlen, dout, din, flags, len); |
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/*
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* Important: |
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* andes_spi's hardware doesn't support 2 data channel. The read |
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* and write cmd/data share the same register (data register). |
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* |
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* If a command has write and read transaction, you cannot do write |
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* this time and then do read on next time. |
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* |
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* A command writes first with a read response must indicating |
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* the read length in write operation. Hence the write action must |
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* be stored temporary and wait until the next read action has been |
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* arrived. Then we flush the write and read action out together. |
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*/ |
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if (!dout) { |
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if (op_nextime == 1) { |
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/* flags should be SPI_XFER_END, value is 2 */ |
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op_nextime = 0; |
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andes_spi_write(slave, tmp_wlen, len, tmp_cmd, flags); |
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} |
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return andes_spi_read(slave, len, din, flags); |
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} else if (!din) { |
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if (flags == SPI_XFER_BEGIN) { |
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/* store the write command and do operation next time */ |
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op_nextime = 1; |
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memset(tmp_cmd, 0, sizeof(tmp_cmd)); |
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memcpy(tmp_cmd, dout, len); |
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debug("%s: tmp_cmd: ", __func__); |
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for (i = 0; i < len; i++) |
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debug("%x ", *(tmp_cmd + i)); |
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debug("\n"); |
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tmp_wlen = len; |
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} else { |
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/*
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* flags should be (SPI_XFER_BEGIN | SPI_XFER_END), |
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* the value is 3. |
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*/ |
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if (op_nextime == 1) { |
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/* flags should be SPI_XFER_END, value is 2 */ |
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op_nextime = 0; |
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/* flags 3 implies write only */ |
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andes_spi_write(slave, tmp_wlen, 0, tmp_cmd, 3); |
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} |
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debug("flags: %x\n", flags); |
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return andes_spi_write(slave, len, 0, dout, flags); |
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} |
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} |
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out: |
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return 0; |
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} |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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return bus == 0 && cs == 0; |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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/* do nothing */ |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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/* do nothing */ |
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} |
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@ -1,115 +0,0 @@ |
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/*
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* Register definitions for the Andes SPI Controller |
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* |
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* (C) Copyright 2011 Andes Technology |
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* Macpaul Lin <macpaul@andestech.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ANDES_SPI_H |
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#define __ANDES_SPI_H |
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struct andes_spi_regs { |
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unsigned int apb; /* 0x00 - APB SPI interface setting */ |
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unsigned int pio; /* 0x04 - PIO reg */ |
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unsigned int cr; /* 0x08 - SPI Control reg */ |
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unsigned int st; /* 0x0c - SPI Status reg */ |
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unsigned int ie; /* 0x10 - Interrupt Enable reg */ |
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unsigned int ist; /* 0x14 - Interrupt Status reg */ |
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unsigned int dcr; /* 0x18 - data control reg */ |
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unsigned int data; /* 0x1c - data register */ |
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unsigned int ahb; /* 0x20 - AHB SPI interface setting */ |
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unsigned int ver; /* 0x3c - SPI version reg */ |
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}; |
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#define BIT(x) (1 << (x)) |
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/* 0x00 - APB SPI interface setting register */ |
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#define ANDES_SPI_APB_BAUD(x) (((x) & 0xff) < 0) |
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#define ANDES_SPI_APB_CSHT(x) (((x) & 0xf) < 16) |
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#define ANDES_SPI_APB_SPNTS BIT(20) /* 0: normal, 1: delay */ |
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#define ANDES_SPI_APB_CPHA BIT(24) /* 0: Sampling at odd edges */ |
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#define ANDES_SPI_APB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */ |
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#define ANDES_SPI_APB_MSSL BIT(26) /* 0: SPI Master, 1: slave */ |
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|
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/* 0x04 - PIO register */ |
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#define ANDES_SPI_PIO_MISO BIT(0) /* input value of pin MISO */ |
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#define ANDES_SPI_PIO_MOSI BIT(1) /* I/O value of pin MOSI */ |
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#define ANDES_SPI_PIO_SCK BIT(2) /* I/O value of pin SCK */ |
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#define ANDES_SPI_PIO_CS BIT(3) /* I/O value of pin CS */ |
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#define ANDES_SPI_PIO_PIOE BIT(4) /* Programming IO Enable */ |
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|
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/* 0x08 - SPI Control register */ |
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#define ANDES_SPI_CR_SPIRST BIT(0) /* SPI mode reset */ |
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#define ANDES_SPI_CR_RXFRST BIT(1) /* RxFIFO reset */ |
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#define ANDES_SPI_CR_TXFRST BIT(2) /* TxFIFO reset */ |
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#define ANDES_SPI_CR_RXFTH(x) (((x) & 0x1f) << 10) /* RxFIFO Threshold */ |
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#define ANDES_SPI_CR_TXFTH(x) (((x) & 0x1f) << 18) /* TxFIFO Threshold */ |
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|
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/* 0x0c - SPI Status register */ |
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#define ANDES_SPI_ST_SPIBSY BIT(0) /* SPI Transfer is active */ |
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#define ANDES_SPI_ST_RXFEM BIT(8) /* RxFIFO Empty Flag */ |
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#define ANDES_SPI_ST_RXFEL BIT(9) /* RxFIFO Full Flag */ |
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#define ANDES_SPI_ST_RXFVE(x) (((x) >> 10) & 0x1f) |
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#define ANDES_SPI_ST_TXFEM BIT(16) /* TxFIFO Empty Flag */ |
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#define ANDES_SPI_ST_TXFEL BIT(7) /* TxFIFO Full Flag */ |
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#define ANDES_SPI_ST_TXFVE(x) (((x) >> 18) & 0x1f) |
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|
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/* 0x10 - Interrupt Enable register */ |
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#define ANDES_SPI_IE_RXFORIE BIT(0) /* RxFIFO overrun intr */ |
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#define ANDES_SPI_IE_TXFURIE BIT(1) /* TxFOFO underrun intr */ |
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#define ANDES_SPI_IE_RXFTHIE BIT(2) /* RxFIFO threshold intr */ |
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#define ANDES_SPI_IE_TXFTHIE BIT(3) /* TxFIFO threshold intr */ |
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#define ANDES_SPI_IE_SPIEIE BIT(4) /* SPI transmit END intr */ |
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#define ANDES_SPI_IE_SPCFIE BIT(5) /* AHB/APB TxReq conflict */ |
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|
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/* 0x14 - Interrupt Status Register */ |
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#define ANDES_SPI_IST_RXFORI BIT(0) /* has RxFIFO overrun */ |
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#define ANDES_SPI_IST_TXFURI BIT(1) /* has TxFOFO underrun */ |
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#define ANDES_SPI_IST_RXFTHI BIT(2) /* has RxFIFO threshold */ |
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#define ANDES_SPI_IST_TXFTHI BIT(3) /* has TxFIFO threshold */ |
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#define ANDES_SPI_IST_SPIEI BIT(4) /* has SPI transmit END */ |
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#define ANDES_SPI_IST_SPCFI BIT(5) /* has AHB/APB TxReq conflict */ |
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|
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/* 0x18 - Data Control Register */ |
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#define ANDES_SPI_DCR_RCNT(x) (((x) & 0x3ff) << 0) |
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#define ANDES_SPI_DCR_DYCNT(x) (((x) & 0x7) << 12) |
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#define ANDES_SPI_DCR_WCNT(x) (((x) & 0x3ff) << 16) |
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#define ANDES_SPI_DCR_TRAMODE(x) (((x) & 0x7) << 28) |
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#define ANDES_SPI_DCR_SPIT BIT(31) /* SPI bus trigger */ |
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|
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#define ANDES_SPI_DCR_MODE_WRCON ANDES_SPI_DCR_TRAMODE(0) /* w/r at the same time */ |
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#define ANDES_SPI_DCR_MODE_WO ANDES_SPI_DCR_TRAMODE(1) /* write only */ |
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#define ANDES_SPI_DCR_MODE_RO ANDES_SPI_DCR_TRAMODE(2) /* read only */ |
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#define ANDES_SPI_DCR_MODE_WR ANDES_SPI_DCR_TRAMODE(3) /* write, read */ |
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#define ANDES_SPI_DCR_MODE_RW ANDES_SPI_DCR_TRAMODE(4) /* read, write */ |
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#define ANDES_SPI_DCR_MODE_WDR ANDES_SPI_DCR_TRAMODE(5) /* write, dummy, read */ |
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#define ANDES_SPI_DCR_MODE_RDW ANDES_SPI_DCR_TRAMODE(6) /* read, dummy, write */ |
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#define ANDES_SPI_DCR_MODE_RECEIVE ANDES_SPI_DCR_TRAMODE(7) /* receive */ |
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|
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/* 0x20 - AHB SPI interface setting register */ |
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#define ANDES_SPI_AHB_BAUD(x) (((x) & 0xff) < 0) |
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#define ANDES_SPI_AHB_CSHT(x) (((x) & 0xf) < 16) |
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#define ANDES_SPI_AHB_SPNTS BIT(20) /* 0: normal, 1: delay */ |
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#define ANDES_SPI_AHB_CPHA BIT(24) /* 0: Sampling at odd edges */ |
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#define ANDES_SPI_AHB_CPOL BIT(25) /* 0: SCK low, 1: SCK high */ |
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#define ANDES_SPI_AHB_MSSL BIT(26) /* only Master mode */ |
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|
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/* 0x3c - Version Register - (Year V.MAJOR.MINOR) */ |
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#define ANDES_SPI_VER_MINOR(x) (((x) >> 0) & 0xf) |
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#define ANDES_SPI_VER_MAJOR(x) (((x) >> 8) & 0xf) |
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#define ANDES_SPI_VER_YEAR(x) (((x) >> 16) & 0xf) |
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|
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struct andes_spi_slave { |
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struct spi_slave slave; |
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struct andes_spi_regs *regs; |
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unsigned int freq; |
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}; |
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|
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static inline struct andes_spi_slave *to_andes_spi(struct spi_slave *slave) |
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{ |
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return container_of(slave, struct andes_spi_slave, slave); |
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} |
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|
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#endif /* __ANDES_SPI_H */ |
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@ -1,121 +0,0 @@ |
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/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
|
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* |
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* Register definitions for the DaVinci SPI Controller |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _DAVINCI_SPI_H_ |
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#define _DAVINCI_SPI_H_ |
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|
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struct davinci_spi_regs { |
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dv_reg gcr0; /* 0x00 */ |
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dv_reg gcr1; /* 0x04 */ |
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dv_reg int0; /* 0x08 */ |
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dv_reg lvl; /* 0x0c */ |
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dv_reg flg; /* 0x10 */ |
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dv_reg pc0; /* 0x14 */ |
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dv_reg pc1; /* 0x18 */ |
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dv_reg pc2; /* 0x1c */ |
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dv_reg pc3; /* 0x20 */ |
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dv_reg pc4; /* 0x24 */ |
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dv_reg pc5; /* 0x28 */ |
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dv_reg rsvd[3]; |
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dv_reg dat0; /* 0x38 */ |
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dv_reg dat1; /* 0x3c */ |
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dv_reg buf; /* 0x40 */ |
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dv_reg emu; /* 0x44 */ |
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dv_reg delay; /* 0x48 */ |
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dv_reg def; /* 0x4c */ |
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dv_reg fmt0; /* 0x50 */ |
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dv_reg fmt1; /* 0x54 */ |
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dv_reg fmt2; /* 0x58 */ |
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dv_reg fmt3; /* 0x5c */ |
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dv_reg intvec0; /* 0x60 */ |
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dv_reg intvec1; /* 0x64 */ |
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}; |
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|
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#define BIT(x) (1 << (x)) |
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|
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/* SPIGCR0 */ |
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#define SPIGCR0_SPIENA_MASK 0x1 |
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#define SPIGCR0_SPIRST_MASK 0x0 |
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|
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/* SPIGCR0 */ |
||||
#define SPIGCR1_CLKMOD_MASK BIT(1) |
||||
#define SPIGCR1_MASTER_MASK BIT(0) |
||||
#define SPIGCR1_SPIENA_MASK BIT(24) |
||||
|
||||
/* SPIPC0 */ |
||||
#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */ |
||||
#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */ |
||||
#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ |
||||
#define SPIPC0_EN0FUN_MASK BIT(0) |
||||
|
||||
/* SPIFMT0 */ |
||||
#define SPIFMT_SHIFTDIR_SHIFT 20 |
||||
#define SPIFMT_POLARITY_SHIFT 17 |
||||
#define SPIFMT_PHASE_SHIFT 16 |
||||
#define SPIFMT_PRESCALE_SHIFT 8 |
||||
|
||||
/* SPIDAT1 */ |
||||
#define SPIDAT1_CSHOLD_SHIFT 28 |
||||
#define SPIDAT1_CSNR_SHIFT 16 |
||||
|
||||
/* SPIDELAY */ |
||||
#define SPI_C2TDELAY_SHIFT 24 |
||||
#define SPI_T2CDELAY_SHIFT 16 |
||||
|
||||
/* SPIBUF */ |
||||
#define SPIBUF_RXEMPTY_MASK BIT(31) |
||||
#define SPIBUF_TXFULL_MASK BIT(29) |
||||
|
||||
/* SPIDEF */ |
||||
#define SPIDEF_CSDEF0_MASK BIT(0) |
||||
|
||||
#define SPI0_BUS 0 |
||||
#define SPI0_BASE CONFIG_SYS_SPI_BASE |
||||
/*
|
||||
* Define default SPI0_NUM_CS as 1 for existing platforms that uses this |
||||
* driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS |
||||
* if more than one CS is supported and by defining CONFIG_SYS_SPI0. |
||||
*/ |
||||
#ifndef CONFIG_SYS_SPI0 |
||||
#define SPI0_NUM_CS 1 |
||||
#else |
||||
#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS |
||||
#endif |
||||
|
||||
/*
|
||||
* define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and |
||||
* CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus |
||||
*/ |
||||
#ifdef CONFIG_SYS_SPI1 |
||||
#define SPI1_BUS 1 |
||||
#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS |
||||
#define SPI1_BASE CONFIG_SYS_SPI1_BASE |
||||
#endif |
||||
|
||||
/*
|
||||
* define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and |
||||
* CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus |
||||
*/ |
||||
#ifdef CONFIG_SYS_SPI2 |
||||
#define SPI2_BUS 2 |
||||
#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS |
||||
#define SPI2_BASE CONFIG_SYS_SPI2_BASE |
||||
#endif |
||||
|
||||
struct davinci_spi_slave { |
||||
struct spi_slave slave; |
||||
struct davinci_spi_regs *regs; |
||||
unsigned int freq; |
||||
}; |
||||
|
||||
static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) |
||||
{ |
||||
return container_of(slave, struct davinci_spi_slave, slave); |
||||
} |
||||
|
||||
#endif /* _DAVINCI_SPI_H_ */ |
||||
@ -1,498 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2013 |
||||
* Faraday Technology Corporation. <http://www.faraday-tech.com/tw/>
|
||||
* Kuo-Jung Su <dantesu@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/compat.h> |
||||
#include <asm/io.h> |
||||
#include <malloc.h> |
||||
#include <spi.h> |
||||
|
||||
#ifndef CONFIG_FTSSP010_BASE_LIST |
||||
#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE } |
||||
#endif |
||||
|
||||
#ifndef CONFIG_FTSSP010_GPIO_BASE |
||||
#define CONFIG_FTSSP010_GPIO_BASE 0 |
||||
#endif |
||||
|
||||
#ifndef CONFIG_FTSSP010_GPIO_LIST |
||||
#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE } |
||||
#endif |
||||
|
||||
#ifndef CONFIG_FTSSP010_CLOCK |
||||
#define CONFIG_FTSSP010_CLOCK clk_get_rate("SSP"); |
||||
#endif |
||||
|
||||
#ifndef CONFIG_FTSSP010_TIMEOUT |
||||
#define CONFIG_FTSSP010_TIMEOUT 100 |
||||
#endif |
||||
|
||||
/* FTSSP010 chip registers */ |
||||
struct ftssp010_regs { |
||||
uint32_t cr[3];/* control register */ |
||||
uint32_t sr; /* status register */ |
||||
uint32_t icr; /* interrupt control register */ |
||||
uint32_t isr; /* interrupt status register */ |
||||
uint32_t dr; /* data register */ |
||||
uint32_t rsvd[17]; |
||||
uint32_t revr; /* revision register */ |
||||
uint32_t fear; /* feature register */ |
||||
}; |
||||
|
||||
/* Control Register 0 */ |
||||
#define CR0_FFMT_MASK (7 << 12) |
||||
#define CR0_FFMT_SSP (0 << 12) |
||||
#define CR0_FFMT_SPI (1 << 12) |
||||
#define CR0_FFMT_MICROWIRE (2 << 12) |
||||
#define CR0_FFMT_I2S (3 << 12) |
||||
#define CR0_FFMT_AC97 (4 << 12) |
||||
#define CR0_FLASH (1 << 11) |
||||
#define CR0_FSDIST(x) (((x) & 0x03) << 8) |
||||
#define CR0_LOOP (1 << 7) /* loopback mode */ |
||||
#define CR0_LSB (1 << 6) /* LSB */ |
||||
#define CR0_FSPO (1 << 5) /* fs atcive low (I2S only) */ |
||||
#define CR0_FSJUSTIFY (1 << 4) |
||||
#define CR0_OPM_SLAVE (0 << 2) |
||||
#define CR0_OPM_MASTER (3 << 2) |
||||
#define CR0_OPM_I2S_MSST (3 << 2) /* master stereo mode */ |
||||
#define CR0_OPM_I2S_MSMO (2 << 2) /* master mono mode */ |
||||
#define CR0_OPM_I2S_SLST (1 << 2) /* slave stereo mode */ |
||||
#define CR0_OPM_I2S_SLMO (0 << 2) /* slave mono mode */ |
||||
#define CR0_SCLKPO (1 << 1) /* clock polarity */ |
||||
#define CR0_SCLKPH (1 << 0) /* clock phase */ |
||||
|
||||
/* Control Register 1 */ |
||||
#define CR1_PDL(x) (((x) & 0xff) << 24) /* padding length */ |
||||
#define CR1_SDL(x) ((((x) - 1) & 0x1f) << 16) /* data length */ |
||||
#define CR1_DIV(x) (((x) - 1) & 0xffff) /* clock divider */ |
||||
|
||||
/* Control Register 2 */ |
||||
#define CR2_CS(x) (((x) & 3) << 10) /* CS/FS select */ |
||||
#define CR2_FS (1 << 9) /* CS/FS signal level */ |
||||
#define CR2_TXEN (1 << 8) /* tx enable */ |
||||
#define CR2_RXEN (1 << 7) /* rx enable */ |
||||
#define CR2_RESET (1 << 6) /* chip reset */ |
||||
#define CR2_TXFC (1 << 3) /* tx fifo Clear */ |
||||
#define CR2_RXFC (1 << 2) /* rx fifo Clear */ |
||||
#define CR2_TXDOE (1 << 1) /* tx data output enable */ |
||||
#define CR2_EN (1 << 0) /* chip enable */ |
||||
|
||||
/* Status Register */ |
||||
#define SR_RFF (1 << 0) /* rx fifo full */ |
||||
#define SR_TFNF (1 << 1) /* tx fifo not full */ |
||||
#define SR_BUSY (1 << 2) /* chip busy */ |
||||
#define SR_RFVE(reg) (((reg) >> 4) & 0x1f) /* rx fifo valid entries */ |
||||
#define SR_TFVE(reg) (((reg) >> 12) & 0x1f) /* tx fifo valid entries */ |
||||
|
||||
/* Feature Register */ |
||||
#define FEAR_BITS(reg) ((((reg) >> 0) & 0xff) + 1) /* data width */ |
||||
#define FEAR_RFSZ(reg) ((((reg) >> 8) & 0xff) + 1) /* rx fifo size */ |
||||
#define FEAR_TFSZ(reg) ((((reg) >> 16) & 0xff) + 1) /* tx fifo size */ |
||||
#define FEAR_AC97 (1 << 24) |
||||
#define FEAR_I2S (1 << 25) |
||||
#define FEAR_SPI_MWR (1 << 26) |
||||
#define FEAR_SSP (1 << 27) |
||||
#define FEAR_SPDIF (1 << 28) |
||||
|
||||
/* FTGPIO010 chip registers */ |
||||
struct ftgpio010_regs { |
||||
uint32_t out; /* 0x00: Data Output */ |
||||
uint32_t in; /* 0x04: Data Input */ |
||||
uint32_t dir; /* 0x08: Direction */ |
||||
uint32_t bypass; /* 0x0c: Bypass */ |
||||
uint32_t set; /* 0x10: Data Set */ |
||||
uint32_t clr; /* 0x14: Data Clear */ |
||||
uint32_t pull_up; /* 0x18: Pull-Up Enabled */ |
||||
uint32_t pull_st; /* 0x1c: Pull State (0=pull-down, 1=pull-up) */ |
||||
}; |
||||
|
||||
struct ftssp010_gpio { |
||||
struct ftgpio010_regs *regs; |
||||
uint32_t pin; |
||||
}; |
||||
|
||||
struct ftssp010_spi { |
||||
struct spi_slave slave; |
||||
struct ftssp010_gpio gpio; |
||||
struct ftssp010_regs *regs; |
||||
uint32_t fifo; |
||||
uint32_t mode; |
||||
uint32_t div; |
||||
uint32_t clk; |
||||
uint32_t speed; |
||||
uint32_t revision; |
||||
}; |
||||
|
||||
static inline struct ftssp010_spi *to_ftssp010_spi(struct spi_slave *slave) |
||||
{ |
||||
return container_of(slave, struct ftssp010_spi, slave); |
||||
} |
||||
|
||||
static int get_spi_chip(int bus, struct ftssp010_spi *chip) |
||||
{ |
||||
uint32_t fear, base[] = CONFIG_FTSSP010_BASE_LIST; |
||||
|
||||
if (bus >= ARRAY_SIZE(base) || !base[bus]) |
||||
return -1; |
||||
|
||||
chip->regs = (struct ftssp010_regs *)base[bus]; |
||||
|
||||
chip->revision = readl(&chip->regs->revr); |
||||
|
||||
fear = readl(&chip->regs->fear); |
||||
chip->fifo = min_t(uint32_t, FEAR_TFSZ(fear), FEAR_RFSZ(fear)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int get_spi_gpio(int bus, struct ftssp010_gpio *chip) |
||||
{ |
||||
uint32_t base[] = CONFIG_FTSSP010_GPIO_LIST; |
||||
|
||||
if (bus >= ARRAY_SIZE(base) || !base[bus]) |
||||
return -1; |
||||
|
||||
chip->regs = (struct ftgpio010_regs *)(base[bus] & 0xfff00000); |
||||
chip->pin = base[bus] & 0x1f; |
||||
|
||||
/* make it an output pin */ |
||||
setbits_le32(&chip->regs->dir, 1 << chip->pin); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ftssp010_wait(struct ftssp010_spi *chip) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
ulong t; |
||||
|
||||
/* wait until device idle */ |
||||
for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { |
||||
if (!(readl(®s->sr) & SR_BUSY)) |
||||
return 0; |
||||
} |
||||
|
||||
puts("ftspi010: busy timeout\n"); |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
static int ftssp010_wait_tx(struct ftssp010_spi *chip) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
ulong t; |
||||
|
||||
/* wait until tx fifo not full */ |
||||
for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { |
||||
if (readl(®s->sr) & SR_TFNF) |
||||
return 0; |
||||
} |
||||
|
||||
puts("ftssp010: tx timeout\n"); |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
static int ftssp010_wait_rx(struct ftssp010_spi *chip) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
ulong t; |
||||
|
||||
/* wait until rx fifo not empty */ |
||||
for (t = get_timer(0); get_timer(t) < CONFIG_FTSSP010_TIMEOUT; ) { |
||||
if (SR_RFVE(readl(®s->sr))) |
||||
return 0; |
||||
} |
||||
|
||||
puts("ftssp010: rx timeout\n"); |
||||
|
||||
return -1; |
||||
} |
||||
|
||||
static int ftssp010_spi_work_transfer_v2(struct ftssp010_spi *chip, |
||||
const void *tx_buf, void *rx_buf, int len, uint flags) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
const uint8_t *txb = tx_buf; |
||||
uint8_t *rxb = rx_buf; |
||||
|
||||
while (len > 0) { |
||||
int i, depth = min(chip->fifo >> 2, len); |
||||
uint32_t xmsk = 0; |
||||
|
||||
if (tx_buf) { |
||||
for (i = 0; i < depth; ++i) { |
||||
ftssp010_wait_tx(chip); |
||||
writel(*txb++, ®s->dr); |
||||
} |
||||
xmsk |= CR2_TXEN | CR2_TXDOE; |
||||
if ((readl(®s->cr[2]) & xmsk) != xmsk) |
||||
setbits_le32(®s->cr[2], xmsk); |
||||
} |
||||
if (rx_buf) { |
||||
xmsk |= CR2_RXEN; |
||||
if ((readl(®s->cr[2]) & xmsk) != xmsk) |
||||
setbits_le32(®s->cr[2], xmsk); |
||||
for (i = 0; i < depth; ++i) { |
||||
ftssp010_wait_rx(chip); |
||||
*rxb++ = (uint8_t)readl(®s->dr); |
||||
} |
||||
} |
||||
|
||||
len -= depth; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int ftssp010_spi_work_transfer_v1(struct ftssp010_spi *chip, |
||||
const void *tx_buf, void *rx_buf, int len, uint flags) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
const uint8_t *txb = tx_buf; |
||||
uint8_t *rxb = rx_buf; |
||||
|
||||
while (len > 0) { |
||||
int i, depth = min(chip->fifo >> 2, len); |
||||
uint32_t tmp; |
||||
|
||||
for (i = 0; i < depth; ++i) { |
||||
ftssp010_wait_tx(chip); |
||||
writel(txb ? (*txb++) : 0, ®s->dr); |
||||
} |
||||
for (i = 0; i < depth; ++i) { |
||||
ftssp010_wait_rx(chip); |
||||
tmp = readl(®s->dr); |
||||
if (rxb) |
||||
*rxb++ = (uint8_t)tmp; |
||||
} |
||||
|
||||
len -= depth; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void ftssp010_cs_set(struct ftssp010_spi *chip, int high) |
||||
{ |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
struct ftssp010_gpio *gpio = &chip->gpio; |
||||
uint32_t mask; |
||||
|
||||
/* cs pull high/low */ |
||||
if (chip->revision >= 0x11900) { |
||||
mask = CR2_CS(chip->slave.cs) | (high ? CR2_FS : 0); |
||||
writel(mask, ®s->cr[2]); |
||||
} else if (gpio->regs) { |
||||
mask = 1 << gpio->pin; |
||||
if (high) |
||||
writel(mask, &gpio->regs->set); |
||||
else |
||||
writel(mask, &gpio->regs->clr); |
||||
} |
||||
|
||||
/* extra delay for signal propagation */ |
||||
udelay_masked(1); |
||||
} |
||||
|
||||
/*
|
||||
* Determine if a SPI chipselect is valid. |
||||
* This function is provided by the board if the low-level SPI driver |
||||
* needs it to determine if a given chipselect is actually valid. |
||||
* |
||||
* Returns: 1 if bus:cs identifies a valid chip on this board, 0 |
||||
* otherwise. |
||||
*/ |
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
||||
{ |
||||
struct ftssp010_spi chip; |
||||
|
||||
if (get_spi_chip(bus, &chip)) |
||||
return 0; |
||||
|
||||
if (!cs) |
||||
return 1; |
||||
else if ((cs < 4) && (chip.revision >= 0x11900)) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Activate a SPI chipselect. |
||||
* This function is provided by the board code when using a driver |
||||
* that can't control its chipselects automatically (e.g. |
||||
* common/soft_spi.c). When called, it should activate the chip select |
||||
* to the device identified by "slave". |
||||
*/ |
||||
void spi_cs_activate(struct spi_slave *slave) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
|
||||
/* cs pull */ |
||||
if (chip->mode & SPI_CS_HIGH) |
||||
ftssp010_cs_set(chip, 1); |
||||
else |
||||
ftssp010_cs_set(chip, 0); |
||||
|
||||
/* chip enable + fifo clear */ |
||||
setbits_le32(®s->cr[2], CR2_EN | CR2_TXFC | CR2_RXFC); |
||||
} |
||||
|
||||
/*
|
||||
* Deactivate a SPI chipselect. |
||||
* This function is provided by the board code when using a driver |
||||
* that can't control its chipselects automatically (e.g. |
||||
* common/soft_spi.c). When called, it should deactivate the chip |
||||
* select to the device identified by "slave". |
||||
*/ |
||||
void spi_cs_deactivate(struct spi_slave *slave) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
|
||||
/* wait until chip idle */ |
||||
ftssp010_wait(chip); |
||||
|
||||
/* cs pull */ |
||||
if (chip->mode & SPI_CS_HIGH) |
||||
ftssp010_cs_set(chip, 0); |
||||
else |
||||
ftssp010_cs_set(chip, 1); |
||||
} |
||||
|
||||
void spi_init(void) |
||||
{ |
||||
/* nothing to do */ |
||||
} |
||||
|
||||
struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) |
||||
{ |
||||
struct ftssp010_spi *chip; |
||||
|
||||
if (mode & SPI_3WIRE) { |
||||
puts("ftssp010: can't do 3-wire\n"); |
||||
return NULL; |
||||
} |
||||
|
||||
if (mode & SPI_SLAVE) { |
||||
puts("ftssp010: can't do slave mode\n"); |
||||
return NULL; |
||||
} |
||||
|
||||
if (mode & SPI_PREAMBLE) { |
||||
puts("ftssp010: can't skip preamble bytes\n"); |
||||
return NULL; |
||||
} |
||||
|
||||
if (!spi_cs_is_valid(bus, cs)) { |
||||
puts("ftssp010: invalid (bus, cs)\n"); |
||||
return NULL; |
||||
} |
||||
|
||||
chip = spi_alloc_slave(struct ftssp010_spi, bus, cs); |
||||
if (!chip) |
||||
return NULL; |
||||
|
||||
if (get_spi_chip(bus, chip)) |
||||
goto free_out; |
||||
|
||||
if (chip->revision < 0x11900 && get_spi_gpio(bus, &chip->gpio)) { |
||||
puts("ftssp010: Before revision 1.19.0, its clock & cs are\n" |
||||
"controlled by tx engine which is not synced with rx engine,\n" |
||||
"so the clock & cs might be shutdown before rx engine\n" |
||||
"finishs its jobs.\n" |
||||
"If possible, please add a dedicated gpio for it.\n"); |
||||
} |
||||
|
||||
chip->mode = mode; |
||||
chip->clk = CONFIG_FTSSP010_CLOCK; |
||||
chip->div = 2; |
||||
if (max_hz) { |
||||
while (chip->div < 0xffff) { |
||||
if ((chip->clk / (2 * chip->div)) <= max_hz) |
||||
break; |
||||
chip->div += 1; |
||||
} |
||||
} |
||||
chip->speed = chip->clk / (2 * chip->div); |
||||
|
||||
return &chip->slave; |
||||
|
||||
free_out: |
||||
free(chip); |
||||
return NULL; |
||||
} |
||||
|
||||
void spi_free_slave(struct spi_slave *slave) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
|
||||
free(chip); |
||||
} |
||||
|
||||
int spi_claim_bus(struct spi_slave *slave) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
|
||||
writel(CR1_SDL(8) | CR1_DIV(chip->div), ®s->cr[1]); |
||||
|
||||
if (chip->revision >= 0x11900) { |
||||
writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO | CR0_FLASH, |
||||
®s->cr[0]); |
||||
writel(CR2_TXFC | CR2_RXFC, |
||||
®s->cr[2]); |
||||
} else { |
||||
writel(CR0_OPM_MASTER | CR0_FFMT_SPI | CR0_FSPO, |
||||
®s->cr[0]); |
||||
writel(CR2_TXFC | CR2_RXFC | CR2_EN | CR2_TXDOE, |
||||
®s->cr[2]); |
||||
} |
||||
|
||||
if (chip->mode & SPI_LOOP) |
||||
setbits_le32(®s->cr[0], CR0_LOOP); |
||||
|
||||
if (chip->mode & SPI_CPOL) |
||||
setbits_le32(®s->cr[0], CR0_SCLKPO); |
||||
|
||||
if (chip->mode & SPI_CPHA) |
||||
setbits_le32(®s->cr[0], CR0_SCLKPH); |
||||
|
||||
spi_cs_deactivate(slave); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void spi_release_bus(struct spi_slave *slave) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
struct ftssp010_regs *regs = chip->regs; |
||||
|
||||
writel(0, ®s->cr[2]); |
||||
} |
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
||||
const void *dout, void *din, unsigned long flags) |
||||
{ |
||||
struct ftssp010_spi *chip = to_ftssp010_spi(slave); |
||||
uint32_t len = bitlen >> 3; |
||||
|
||||
if (flags & SPI_XFER_BEGIN) |
||||
spi_cs_activate(slave); |
||||
|
||||
if (chip->revision >= 0x11900) |
||||
ftssp010_spi_work_transfer_v2(chip, dout, din, len, flags); |
||||
else |
||||
ftssp010_spi_work_transfer_v1(chip, dout, din, len, flags); |
||||
|
||||
if (flags & SPI_XFER_END) |
||||
spi_cs_deactivate(slave); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,245 +0,0 @@ |
||||
/*
|
||||
* Opencore tiny_spi driver |
||||
* |
||||
* http://opencores.org/project,tiny_spi
|
||||
* |
||||
* based on bfin_spi.c |
||||
* Copyright (c) 2005-2008 Analog Devices Inc. |
||||
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <malloc.h> |
||||
#include <spi.h> |
||||
#include <asm/gpio.h> |
||||
|
||||
#define TINY_SPI_STATUS_TXE 0x1 |
||||
#define TINY_SPI_STATUS_TXR 0x2 |
||||
|
||||
struct tiny_spi_regs { |
||||
unsigned rxdata; /* Rx data reg */ |
||||
unsigned txdata; /* Tx data reg */ |
||||
unsigned status; /* Status reg */ |
||||
unsigned control; /* Control reg */ |
||||
unsigned baud; /* Baud reg */ |
||||
}; |
||||
|
||||
struct tiny_spi_host { |
||||
uint base; |
||||
uint freq; |
||||
uint baudwidth; |
||||
}; |
||||
static const struct tiny_spi_host tiny_spi_host_list[] = |
||||
CONFIG_SYS_TINY_SPI_LIST; |
||||
|
||||
struct tiny_spi_slave { |
||||
struct spi_slave slave; |
||||
const struct tiny_spi_host *host; |
||||
uint mode; |
||||
uint baud; |
||||
uint flg; |
||||
}; |
||||
#define to_tiny_spi_slave(s) container_of(s, struct tiny_spi_slave, slave) |
||||
|
||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
||||
{ |
||||
return bus < ARRAY_SIZE(tiny_spi_host_list) && gpio_is_valid(cs); |
||||
} |
||||
|
||||
void spi_cs_activate(struct spi_slave *slave) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
unsigned int cs = slave->cs; |
||||
|
||||
gpio_set_value(cs, tiny_spi->flg); |
||||
debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); |
||||
} |
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
unsigned int cs = slave->cs; |
||||
|
||||
gpio_set_value(cs, !tiny_spi->flg); |
||||
debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs)); |
||||
} |
||||
|
||||
void spi_set_speed(struct spi_slave *slave, uint hz) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
const struct tiny_spi_host *host = tiny_spi->host; |
||||
|
||||
tiny_spi->baud = min(DIV_ROUND_UP(host->freq, hz * 2), |
||||
(1 << host->baudwidth)) - 1; |
||||
debug("%s: speed %u actual %u\n", __func__, hz, |
||||
host->freq / ((tiny_spi->baud + 1) * 2)); |
||||
} |
||||
|
||||
void spi_init(void) |
||||
{ |
||||
} |
||||
|
||||
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
||||
unsigned int hz, unsigned int mode) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi; |
||||
|
||||
if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, "tiny_spi")) |
||||
return NULL; |
||||
|
||||
tiny_spi = spi_alloc_slave(struct tiny_spi_slave, bus, cs); |
||||
if (!tiny_spi) |
||||
return NULL; |
||||
|
||||
tiny_spi->host = &tiny_spi_host_list[bus]; |
||||
tiny_spi->mode = mode & (SPI_CPOL | SPI_CPHA); |
||||
tiny_spi->flg = mode & SPI_CS_HIGH ? 1 : 0; |
||||
spi_set_speed(&tiny_spi->slave, hz); |
||||
|
||||
debug("%s: bus:%i cs:%i base:%lx\n", __func__, |
||||
bus, cs, tiny_spi->host->base); |
||||
return &tiny_spi->slave; |
||||
} |
||||
|
||||
void spi_free_slave(struct spi_slave *slave) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
|
||||
gpio_free(slave->cs); |
||||
free(tiny_spi); |
||||
} |
||||
|
||||
int spi_claim_bus(struct spi_slave *slave) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
struct tiny_spi_regs *regs = (void *)tiny_spi->host->base; |
||||
|
||||
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); |
||||
gpio_direction_output(slave->cs, !tiny_spi->flg); |
||||
writel(tiny_spi->mode, ®s->control); |
||||
writel(tiny_spi->baud, ®s->baud); |
||||
return 0; |
||||
} |
||||
|
||||
void spi_release_bus(struct spi_slave *slave) |
||||
{ |
||||
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); |
||||
} |
||||
|
||||
#ifndef CONFIG_TINY_SPI_IDLE_VAL |
||||
# define CONFIG_TINY_SPI_IDLE_VAL 0xff |
||||
#endif |
||||
|
||||
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
||||
void *din, unsigned long flags) |
||||
{ |
||||
struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave); |
||||
struct tiny_spi_regs *regs = (void *)tiny_spi->host->base; |
||||
const u8 *txp = dout; |
||||
u8 *rxp = din; |
||||
uint bytes = bitlen / 8; |
||||
uint i; |
||||
|
||||
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, |
||||
slave->bus, slave->cs, bitlen, bytes, flags); |
||||
if (bitlen == 0) |
||||
goto done; |
||||
|
||||
/* assume to do 8 bits transfers */ |
||||
if (bitlen % 8) { |
||||
flags |= SPI_XFER_END; |
||||
goto done; |
||||
} |
||||
|
||||
if (flags & SPI_XFER_BEGIN) |
||||
spi_cs_activate(slave); |
||||
|
||||
/* we need to tighten the transfer loop */ |
||||
if (txp && rxp) { |
||||
writeb(*txp++, ®s->txdata); |
||||
if (bytes > 1) { |
||||
writeb(*txp++, ®s->txdata); |
||||
for (i = 2; i < bytes; i++) { |
||||
u8 rx, tx = *txp++; |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
rx = readb(®s->txdata); |
||||
writeb(tx, ®s->txdata); |
||||
*rxp++ = rx; |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
*rxp++ = readb(®s->txdata); |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXE)) |
||||
; |
||||
*rxp++ = readb(®s->rxdata); |
||||
} else if (rxp) { |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, ®s->txdata); |
||||
if (bytes > 1) { |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, |
||||
®s->txdata); |
||||
for (i = 2; i < bytes; i++) { |
||||
u8 rx; |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
rx = readb(®s->txdata); |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, |
||||
®s->txdata); |
||||
*rxp++ = rx; |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
*rxp++ = readb(®s->txdata); |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXE)) |
||||
; |
||||
*rxp++ = readb(®s->rxdata); |
||||
} else if (txp) { |
||||
writeb(*txp++, ®s->txdata); |
||||
if (bytes > 1) { |
||||
writeb(*txp++, ®s->txdata); |
||||
for (i = 2; i < bytes; i++) { |
||||
u8 tx = *txp++; |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
writeb(tx, ®s->txdata); |
||||
} |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXE)) |
||||
; |
||||
} else { |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, ®s->txdata); |
||||
if (bytes > 1) { |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, |
||||
®s->txdata); |
||||
for (i = 2; i < bytes; i++) { |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXR)) |
||||
; |
||||
writeb(CONFIG_TINY_SPI_IDLE_VAL, |
||||
®s->txdata); |
||||
} |
||||
} |
||||
while (!(readb(®s->status) & |
||||
TINY_SPI_STATUS_TXE)) |
||||
; |
||||
} |
||||
|
||||
done: |
||||
if (flags & SPI_XFER_END) |
||||
spi_cs_deactivate(slave); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,138 +0,0 @@ |
||||
/*
|
||||
* Xilinx SPI driver |
||||
* |
||||
* XPS/AXI bus interface |
||||
* |
||||
* based on bfin_spi.c, by way of altera_spi.c |
||||
* Copyright (c) 2005-2008 Analog Devices Inc. |
||||
* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw> |
||||
* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca> |
||||
* Copyright (c) 2012 Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* [0]: http://www.xilinx.com/support/documentation
|
||||
* |
||||
* [S]: [0]/ip_documentation/xps_spi.pdf |
||||
* [0]/ip_documentation/axi_spi_ds742.pdf |
||||
*/ |
||||
#ifndef _XILINX_SPI_ |
||||
#define _XILINX_SPI_ |
||||
|
||||
#include <asm/types.h> |
||||
#include <asm/io.h> |
||||
|
||||
/*
|
||||
* Xilinx SPI Register Definition |
||||
* |
||||
* [1]: [0]/ip_documentation/xps_spi.pdf |
||||
* page 8, Register Descriptions |
||||
* [2]: [0]/ip_documentation/axi_spi_ds742.pdf |
||||
* page 7, Register Overview Table |
||||
*/ |
||||
struct xilinx_spi_reg { |
||||
u32 __space0__[7]; |
||||
u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */ |
||||
u32 ipisr; /* IP Interrupt Status Register (IPISR) */ |
||||
u32 __space1__; |
||||
u32 ipier; /* IP Interrupt Enable Register (IPIER) */ |
||||
u32 __space2__[5]; |
||||
u32 srr; /* Softare Reset Register (SRR) */ |
||||
u32 __space3__[7]; |
||||
u32 spicr; /* SPI Control Register (SPICR) */ |
||||
u32 spisr; /* SPI Status Register (SPISR) */ |
||||
u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */ |
||||
u32 spidrr; /* SPI Data Receive Register (SPIDRR) */ |
||||
u32 spissr; /* SPI Slave Select Register (SPISSR) */ |
||||
u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */ |
||||
u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */ |
||||
}; |
||||
|
||||
/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */ |
||||
#define DGIER_GIE (1 << 31) |
||||
|
||||
/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */ |
||||
#define IPISR_DRR_NOT_EMPTY (1 << 8) |
||||
#define IPISR_SLAVE_SELECT (1 << 7) |
||||
#define IPISR_TXF_HALF_EMPTY (1 << 6) |
||||
#define IPISR_DRR_OVERRUN (1 << 5) |
||||
#define IPISR_DRR_FULL (1 << 4) |
||||
#define IPISR_DTR_UNDERRUN (1 << 3) |
||||
#define IPISR_DTR_EMPTY (1 << 2) |
||||
#define IPISR_SLAVE_MODF (1 << 1) |
||||
#define IPISR_MODF (1 << 0) |
||||
|
||||
/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */ |
||||
#define IPIER_DRR_NOT_EMPTY (1 << 8) |
||||
#define IPIER_SLAVE_SELECT (1 << 7) |
||||
#define IPIER_TXF_HALF_EMPTY (1 << 6) |
||||
#define IPIER_DRR_OVERRUN (1 << 5) |
||||
#define IPIER_DRR_FULL (1 << 4) |
||||
#define IPIER_DTR_UNDERRUN (1 << 3) |
||||
#define IPIER_DTR_EMPTY (1 << 2) |
||||
#define IPIER_SLAVE_MODF (1 << 1) |
||||
#define IPIER_MODF (1 << 0) |
||||
|
||||
/* Softare Reset Register (srr), [1] p9, [2] p8 */ |
||||
#define SRR_RESET_CODE 0x0000000A |
||||
|
||||
/* SPI Control Register (spicr), [1] p9, [2] p8 */ |
||||
#define SPICR_LSB_FIRST (1 << 9) |
||||
#define SPICR_MASTER_INHIBIT (1 << 8) |
||||
#define SPICR_MANUAL_SS (1 << 7) |
||||
#define SPICR_RXFIFO_RESEST (1 << 6) |
||||
#define SPICR_TXFIFO_RESEST (1 << 5) |
||||
#define SPICR_CPHA (1 << 4) |
||||
#define SPICR_CPOL (1 << 3) |
||||
#define SPICR_MASTER_MODE (1 << 2) |
||||
#define SPICR_SPE (1 << 1) |
||||
#define SPICR_LOOP (1 << 0) |
||||
|
||||
/* SPI Status Register (spisr), [1] p11, [2] p10 */ |
||||
#define SPISR_SLAVE_MODE_SELECT (1 << 5) |
||||
#define SPISR_MODF (1 << 4) |
||||
#define SPISR_TX_FULL (1 << 3) |
||||
#define SPISR_TX_EMPTY (1 << 2) |
||||
#define SPISR_RX_FULL (1 << 1) |
||||
#define SPISR_RX_EMPTY (1 << 0) |
||||
|
||||
/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */ |
||||
#define SPIDTR_8BIT_MASK (0xff << 0) |
||||
#define SPIDTR_16BIT_MASK (0xffff << 0) |
||||
#define SPIDTR_32BIT_MASK (0xffffffff << 0) |
||||
|
||||
/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */ |
||||
#define SPIDRR_8BIT_MASK (0xff << 0) |
||||
#define SPIDRR_16BIT_MASK (0xffff << 0) |
||||
#define SPIDRR_32BIT_MASK (0xffffffff << 0) |
||||
|
||||
/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */ |
||||
#define SPISSR_MASK(cs) (1 << (cs)) |
||||
#define SPISSR_ACT(cs) ~SPISSR_MASK(cs) |
||||
#define SPISSR_OFF ~0UL |
||||
|
||||
/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */ |
||||
#define SPITFOR_OCYVAL_POS 0 |
||||
#define SPITFOR_OCYVAL_MASK (0xf << SPITFOR_OCYVAL_POS) |
||||
|
||||
/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */ |
||||
#define SPIRFOR_OCYVAL_POS 0 |
||||
#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS) |
||||
|
||||
/* SPI Software Reset Register (ssr) */ |
||||
#define SPISSR_RESET_VALUE 0x0a |
||||
|
||||
struct xilinx_spi_slave { |
||||
struct spi_slave slave; |
||||
struct xilinx_spi_reg *regs; |
||||
unsigned int freq; |
||||
unsigned int mode; |
||||
}; |
||||
|
||||
static inline struct xilinx_spi_slave *to_xilinx_spi_slave( |
||||
struct spi_slave *slave) |
||||
{ |
||||
return container_of(slave, struct xilinx_spi_slave, slave); |
||||
} |
||||
|
||||
#endif /* _XILINX_SPI_ */ |
||||
Loading…
Reference in new issue