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exynos: Update origen and smdkv310 to use common tzpc_init

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Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
master
Inderpal Singh 11 years ago committed by Minkyu Kang
parent b5f9756f7f
commit 8a00061e20
5 changed files with 8 additions and 125 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 44
      board/samsung/origen/lowlevel_init.S
  2. 25
      board/samsung/origen/origen_setup.h
  3. 60
      board/samsung/smdkv310/lowlevel_init.S
  4. 2
      include/configs/origen.h
  5. 2
      include/configs/smdkv310.h

44
board/samsung/origen/lowlevel_init.S
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@ -87,12 +87,14 @@ lowlevel_init:
1:
/* for UART */
bl uart_asm_init
bl arch_cpu_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
bl arch_cpu_init
bl tzpc_init
exit_wakeup:
@ -353,45 +355,3 @@ uart_asm_init:
nop
nop
/* Setting TZPC[TrustZone Protection Controller] */
tzpc_init:
ldr r0, =TZPC0_BASE
mov r1, #R0SIZE
str r1, [r0]
mov r1, #DECPROTXSET
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC1_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC2_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC3_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC4_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
ldr r0, =TZPC5_BASE
str r1, [r0, #TZPC_DECPROT0SET_OFFSET]
str r1, [r0, #TZPC_DECPROT1SET_OFFSET]
str r1, [r0, #TZPC_DECPROT2SET_OFFSET]
str r1, [r0, #TZPC_DECPROT3SET_OFFSET]
mov pc, lr

25
board/samsung/origen/origen_setup.h
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@ -121,19 +121,6 @@
#define UBRDIV_OFFSET 0x28
#define UFRACVAL_OFFSET 0x2C
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10110000
#define TZPC1_BASE 0x10120000
#define TZPC2_BASE 0x10130000
#define TZPC3_BASE 0x10140000
#define TZPC4_BASE 0x10150000
#define TZPC5_BASE 0x10160000
#define TZPC_DECPROT0SET_OFFSET 0x804
#define TZPC_DECPROT1SET_OFFSET 0x810
#define TZPC_DECPROT2SET_OFFSET 0x81C
#define TZPC_DECPROT3SET_OFFSET 0x828
/* CLK_SRC_CPU */
#define MUX_HPM_SEL_MOUTAPLL 0x0
#define MUX_HPM_SEL_SCLKMPLL 0x1
@ -617,16 +604,4 @@
* UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
*/
#define UFRACVAL_VAL 0x4
/*
* TZPC Register Value :
* R0SIZE: 0x0 : Size of secured ram
*/
#define R0SIZE 0x0
/*
* TZPC Decode Protection Register Value :
* DECPROTXSET: 0xFF : Set Decode region to non-secure
*/
#define DECPROTXSET 0xFF
#endif

60
board/samsung/smdkv310/lowlevel_init.S
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@ -85,12 +85,14 @@ lowlevel_init:
1:
/* for UART */
bl uart_asm_init
bl arch_cpu_init
bl tzpc_init
pop {pc}
wakeup_reset:
bl system_clock_init
bl mem_ctrl_asm_init
bl arch_cpu_init
bl tzpc_init
exit_wakeup:
@ -410,61 +412,3 @@ uart_asm_init:
nop
nop
nop
/* Setting TZPC[TrustZone Protection Controller] */
tzpc_init:
ldr r0, =0x10110000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10120000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10130000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10140000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10150000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
ldr r0, =0x10160000
mov r1, #0x0
str r1, [r0]
mov r1, #0xff
str r1, [r0, #0x0804]
str r1, [r0, #0x0810]
str r1, [r0, #0x081C]
str r1, [r0, #0x0828]
mov pc, lr

2
include/configs/origen.h
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@ -96,6 +96,8 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_TEXT_BASE 0x02021410
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */

2
include/configs/smdkv310.h
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@ -95,6 +95,8 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR 0x00002488
#define CONFIG_SPL_TEXT_BASE 0x02021410
#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
/* Miscellaneous configurable options */

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