Add support for Analogue & Micro Rattler boards. Tested on Rattler8248. * Patch by Andre Renaud, 08 Nov 2004: Fix watchdog support in common/lcd.c * Patch by Marc Leeman, 05 Nov 2003: Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU bug only affects the XPC8245 processorsmaster
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384cc68744
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#
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# (C) Copyright 2001-2005
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,30 @@ |
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#
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# (C) Copyright 2001-2005
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Rattler series boards by Analogue & Micro
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#
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,231 @@ |
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/*
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* Copyright (C) 2004 Arabella Software Ltd. |
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* Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* Support for Analogue&Micro Rattler boards family. |
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* Tested on Rattler8248. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc8260.h> |
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#include <ioports.h> |
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/*
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* I/O Port configuration table |
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* |
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* if conf is 1, then that port pin will be configured at boot time |
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* according to the five values podr/pdir/ppar/psor/pdat for that entry |
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*/ |
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#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) |
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#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) |
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const iop_conf_t iop_conf_tab[4][32] = { |
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/* Port A */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ |
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/* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ |
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/* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ |
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/* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ |
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/* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ |
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/* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ |
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/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ |
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/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ |
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/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ |
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/* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ |
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/* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ |
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/* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ |
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/* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ |
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/* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ |
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/* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ |
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/* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ |
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/* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ |
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/* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ |
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/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ |
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/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ |
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/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ |
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/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ |
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ |
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ |
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ |
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/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ |
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/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ |
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/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ |
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/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ |
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ |
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ |
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/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ |
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}, |
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/* Port B */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
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/* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
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/* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
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/* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
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/* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
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/* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
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/* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
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/* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
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/* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
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/* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
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/* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
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/* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
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/* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
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/* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ |
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}, |
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/* Port C */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ |
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ |
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/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ |
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/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ |
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ |
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ |
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ |
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ |
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ |
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/* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ |
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/* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ |
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/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ |
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/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ |
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/* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ |
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/* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ |
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/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ |
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ |
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ |
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ |
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ |
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ |
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ |
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/* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ |
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/* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ |
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ |
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ |
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/* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ |
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/* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ |
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ |
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ |
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ |
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ |
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}, |
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/* Port D */ |
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{ /* conf ppar psor pdir podr pdat */ |
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ |
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ |
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/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ |
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/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ |
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/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ |
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/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ |
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ |
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ |
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ |
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ |
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ |
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ |
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ |
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ |
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/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ |
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/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ |
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/* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ |
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/* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ |
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
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/* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ |
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/* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ |
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ |
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/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ |
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/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ |
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ |
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ |
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ |
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} |
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}; |
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long int initdram(int board_type) |
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{ |
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long int msize = CFG_SDRAM_SIZE; |
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#ifndef CFG_RAMBOOT |
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volatile immap_t *immap = (immap_t *)CFG_IMMR; |
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volatile memctl8260_t *memctl = &immap->im_memctl; |
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vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; |
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uchar c = 0xFF; |
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uint psdmr = CFG_PSDMR; |
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int i; |
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immap->im_siu_conf.sc_ppc_acr = 0x02; |
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immap->im_siu_conf.sc_ppc_alrh = 0x30126745; |
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immap->im_siu_conf.sc_tescr1 = 0x00004000; |
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memctl->memc_mptpr = CFG_MPTPR; |
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/* Initialise 60x bus SDRAM */ |
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memctl->memc_psrt = CFG_PSRT; |
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memctl->memc_or1 = CFG_SDRAM_OR; |
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memctl->memc_br1 = CFG_SDRAM_BR; |
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memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ |
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*ramaddr = c; |
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memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ |
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for (i = 0; i < 8; i++) |
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*ramaddr = c; |
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memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ |
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*ramaddr = c; |
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memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ |
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*ramaddr = c; |
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#endif /* !CFG_RAMBOOT */ |
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/* Return total 60x bus SDRAM size */ |
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return msize * 1024 * 1024; |
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} |
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int checkboard(void) |
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{ |
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vu_char *bcsr = (vu_char *)CFG_BCSR; |
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printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); |
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return 0; |
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} |
@ -0,0 +1,122 @@ |
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/* |
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* (C) Copyright 2001-2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Modified by Yuli Barcohen <yuli@arabellasw.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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cpu/mpc8260/start.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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. = ALIGN(16); |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
@ -0,0 +1,272 @@ |
||||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd. |
||||
* Yuli Barcohen <yuli@arabellasw.com> |
||||
* |
||||
* U-Boot configuration for Analogue&Micro Rattler boards. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#ifdef CONFIG_MPC8248 |
||||
#define CPU_ID_STR "MPC8248" |
||||
#else |
||||
#define CONFIG_MPC8260 |
||||
#define CPU_ID_STR "MPC8250" |
||||
#endif /* CONFIG_MPC8248 */ |
||||
|
||||
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */ |
||||
|
||||
#undef DEBUG |
||||
|
||||
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
/*
|
||||
* Select serial console configuration |
||||
* |
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
||||
* for SCC). |
||||
*/ |
||||
#define CONFIG_CONS_ON_SMC /* Console is on SMC */ |
||||
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ |
||||
#undef CONFIG_CONS_NONE /* It's not on external UART */ |
||||
#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ |
||||
|
||||
/*
|
||||
* Select ethernet configuration |
||||
* |
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, |
||||
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for |
||||
* SCC, 1-3 for FCC) |
||||
* |
||||
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines |
||||
* must be defined elsewhere (as for the console), or CFG_CMD_NET must |
||||
* be removed from CONFIG_COMMANDS to remove support for networking. |
||||
*/ |
||||
#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ |
||||
#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */ |
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC |
||||
|
||||
#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 1) |
||||
|
||||
/* - Rx clock is CLK11
|
||||
* - Tx clock is CLK10 |
||||
* - BDs/buffers on 60x bus |
||||
* - Full duplex |
||||
*/ |
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) |
||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) |
||||
#define CFG_CPMFCR_RAMTYPE 0 |
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
||||
|
||||
#elif (CONFIG_ETHER_INDEX == 2) |
||||
|
||||
/* - Rx clock is CLK15
|
||||
* - Tx clock is CLK14 |
||||
* - BDs/buffers on 60x bus |
||||
* - Full duplex |
||||
*/ |
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14) |
||||
#define CFG_CPMFCR_RAMTYPE 0 |
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
||||
|
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ |
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications |
||||
*/ |
||||
#define MDIO_PORT 2 /* Port C */ |
||||
#define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
||||
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
||||
#define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
||||
else iop->pdat &= ~0x00400000 |
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \ |
||||
else iop->pdat &= ~0x00800000 |
||||
|
||||
#define MIIDELAY udelay(1) |
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */ |
||||
|
||||
#ifndef CONFIG_8260_CLKIN |
||||
#define CONFIG_8260_CLKIN 100000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 38400 |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_ECHO \
|
||||
| CFG_CMD_IMMAP \
|
||||
| CFG_CMD_JFFS2 \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_PING \
|
||||
) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
||||
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
||||
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
||||
#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
||||
#endif |
||||
|
||||
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ |
||||
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
#define CFG_FLASH_BASE 0xFE000000 |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_DIRECT_FLASH_TFTP |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS |
||||
#define CFG_JFFS2_FIRST_SECTOR 16 |
||||
#define CFG_JFFS2_SORT_FRAGMENTS |
||||
#endif /* CFG_CMD_JFFS2 */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_SECT_SIZE 0x10000 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
||||
#endif /* CFG_ENV_IS_IN_FLASH */ |
||||
|
||||
#define CFG_DEFAULT_IMMR 0xFF010000 |
||||
|
||||
#define CFG_IMMR 0xF0000000 |
||||
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_SDRAM_SIZE 32 |
||||
#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041) |
||||
#define CFG_SDRAM_OR 0xFE002EC0 |
||||
|
||||
#define CFG_BCSR 0xFC000000 |
||||
|
||||
/* Hard reset configuration word */ |
||||
#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ |
||||
/* No slaves */ |
||||
#define CFG_HRCW_SLAVE1 0 |
||||
#define CFG_HRCW_SLAVE2 0 |
||||
#define CFG_HRCW_SLAVE3 0 |
||||
#define CFG_HRCW_SLAVE4 0 |
||||
#define CFG_HRCW_SLAVE5 0 |
||||
#define CFG_HRCW_SLAVE6 0 |
||||
#define CFG_HRCW_SLAVE7 0 |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) |
||||
|
||||
#define CFG_HID2 0 |
||||
|
||||
#define CFG_SIUMCR 0x0E04C000 |
||||
#define CFG_SYPCR 0xFFFFFFC3 |
||||
#define CFG_BCR 0x00000000 |
||||
#define CFG_SCCR SCCR_DFBRG01 |
||||
|
||||
#define CFG_RMR RMR_CSRE |
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
||||
#define CFG_RCCR 0 |
||||
|
||||
#define CFG_PSDMR 0x8249A452 |
||||
#define CFG_PSRT 0x1F |
||||
#define CFG_MPTPR 0x2000 |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001) |
||||
#define CFG_OR0_PRELIM 0xFF001ED6 |
||||
#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) |
||||
#define CFG_OR7_PRELIM 0xFFFF87F6 |
||||
|
||||
#define CFG_RESET_ADDRESS 0xC0000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue