Some of the Intel ME code is common to several Intel CPUs. Move it into a common location. Add a header file for report_platform.c also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [squashed in http://patchwork.ozlabs.org/patch/598372/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>master
Simon Glass
8 years ago
committed by
Bin Meng
parent
2a605d4d88
commit
8b900a4175
@ -0,0 +1,373 @@ |
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/*
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* From Coreboot src/southbridge/intel/bd82x6x/me.h |
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* |
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* Coreboot copies lots of code around. Here we are trying to keep the common |
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* code in a separate file to reduce code duplication and hopefully make it |
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* easier to add new platform. |
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* |
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* Copyright (C) 2016 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ASM_ME_COMMON_H |
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#define __ASM_ME_COMMON_H |
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#include <linux/compiler.h> |
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#include <linux/types.h> |
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#include <pci.h> |
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#define MCHBAR_PEI_VERSION 0x5034 |
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#define ME_RETRY 100000 /* 1 second */ |
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#define ME_DELAY 10 /* 10 us */ |
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/*
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* Management Engine PCI registers |
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*/ |
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#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */ |
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#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ |
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#define PCI_ME_HFS 0x40 |
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#define ME_HFS_CWS_RESET 0 |
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#define ME_HFS_CWS_INIT 1 |
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#define ME_HFS_CWS_REC 2 |
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#define ME_HFS_CWS_NORMAL 5 |
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#define ME_HFS_CWS_WAIT 6 |
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#define ME_HFS_CWS_TRANS 7 |
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#define ME_HFS_CWS_INVALID 8 |
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#define ME_HFS_STATE_PREBOOT 0 |
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#define ME_HFS_STATE_M0_UMA 1 |
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#define ME_HFS_STATE_M3 4 |
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#define ME_HFS_STATE_M0 5 |
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#define ME_HFS_STATE_BRINGUP 6 |
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#define ME_HFS_STATE_ERROR 7 |
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#define ME_HFS_ERROR_NONE 0 |
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#define ME_HFS_ERROR_UNCAT 1 |
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#define ME_HFS_ERROR_IMAGE 3 |
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#define ME_HFS_ERROR_DEBUG 4 |
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#define ME_HFS_MODE_NORMAL 0 |
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#define ME_HFS_MODE_DEBUG 2 |
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#define ME_HFS_MODE_DIS 3 |
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#define ME_HFS_MODE_OVER_JMPR 4 |
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#define ME_HFS_MODE_OVER_MEI 5 |
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#define ME_HFS_BIOS_DRAM_ACK 1 |
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#define ME_HFS_ACK_NO_DID 0 |
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#define ME_HFS_ACK_RESET 1 |
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#define ME_HFS_ACK_PWR_CYCLE 2 |
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#define ME_HFS_ACK_S3 3 |
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#define ME_HFS_ACK_S4 4 |
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#define ME_HFS_ACK_S5 5 |
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#define ME_HFS_ACK_GBL_RESET 6 |
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#define ME_HFS_ACK_CONTINUE 7 |
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struct me_hfs { |
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u32 working_state:4; |
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u32 mfg_mode:1; |
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u32 fpt_bad:1; |
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u32 operation_state:3; |
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u32 fw_init_complete:1; |
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u32 ft_bup_ld_flr:1; |
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u32 update_in_progress:1; |
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u32 error_code:4; |
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u32 operation_mode:4; |
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u32 reserved:4; |
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u32 boot_options_present:1; |
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u32 ack_data:3; |
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u32 bios_msg_ack:4; |
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} __packed; |
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#define PCI_ME_UMA 0x44 |
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struct me_uma { |
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u32 size:6; |
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u32 reserved_1:10; |
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u32 valid:1; |
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u32 reserved_0:14; |
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u32 set_to_one:1; |
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} __packed; |
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#define PCI_ME_H_GS 0x4c |
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#define ME_INIT_DONE 1 |
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#define ME_INIT_STATUS_SUCCESS 0 |
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#define ME_INIT_STATUS_NOMEM 1 |
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#define ME_INIT_STATUS_ERROR 2 |
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struct me_did { |
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u32 uma_base:16; |
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u32 reserved:7; |
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u32 rapid_start:1; /* Broadwell only */ |
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u32 status:4; |
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u32 init_done:4; |
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} __packed; |
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#define PCI_ME_GMES 0x48 |
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#define ME_GMES_PHASE_ROM 0 |
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#define ME_GMES_PHASE_BUP 1 |
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#define ME_GMES_PHASE_UKERNEL 2 |
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#define ME_GMES_PHASE_POLICY 3 |
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#define ME_GMES_PHASE_MODULE 4 |
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#define ME_GMES_PHASE_UNKNOWN 5 |
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#define ME_GMES_PHASE_HOST 6 |
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struct me_gmes { |
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u32 bist_in_prog:1; |
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u32 icc_prog_sts:2; |
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u32 invoke_mebx:1; |
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u32 cpu_replaced_sts:1; |
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u32 mbp_rdy:1; |
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u32 mfs_failure:1; |
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u32 warm_rst_req_for_df:1; |
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u32 cpu_replaced_valid:1; |
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u32 reserved_1:2; |
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u32 fw_upd_ipu:1; |
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u32 reserved_2:4; |
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u32 current_state:8; |
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u32 current_pmevent:4; |
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u32 progress_code:4; |
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} __packed; |
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#define PCI_ME_HERES 0xbc |
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#define PCI_ME_EXT_SHA1 0x00 |
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#define PCI_ME_EXT_SHA256 0x02 |
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#define PCI_ME_HER(x) (0xc0+(4*(x))) |
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struct me_heres { |
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u32 extend_reg_algorithm:4; |
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u32 reserved:26; |
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u32 extend_feature_present:1; |
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u32 extend_reg_valid:1; |
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} __packed; |
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/*
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* Management Engine MEI registers |
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*/ |
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#define MEI_H_CB_WW 0x00 |
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#define MEI_H_CSR 0x04 |
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#define MEI_ME_CB_RW 0x08 |
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#define MEI_ME_CSR_HA 0x0c |
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struct mei_csr { |
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u32 interrupt_enable:1; |
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u32 interrupt_status:1; |
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u32 interrupt_generate:1; |
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u32 ready:1; |
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u32 reset:1; |
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u32 reserved:3; |
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u32 buffer_read_ptr:8; |
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u32 buffer_write_ptr:8; |
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u32 buffer_depth:8; |
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} __packed; |
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#define MEI_ADDRESS_CORE 0x01 |
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#define MEI_ADDRESS_AMT 0x02 |
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#define MEI_ADDRESS_RESERVED 0x03 |
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#define MEI_ADDRESS_WDT 0x04 |
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#define MEI_ADDRESS_MKHI 0x07 |
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#define MEI_ADDRESS_ICC 0x08 |
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#define MEI_ADDRESS_THERMAL 0x09 |
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#define MEI_HOST_ADDRESS 0 |
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struct mei_header { |
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u32 client_address:8; |
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u32 host_address:8; |
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u32 length:9; |
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u32 reserved:6; |
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u32 is_complete:1; |
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} __packed; |
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#define MKHI_GROUP_ID_CBM 0x00 |
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#define MKHI_GROUP_ID_FWCAPS 0x03 |
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#define MKHI_GROUP_ID_MDES 0x08 |
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#define MKHI_GROUP_ID_GEN 0xff |
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#define MKHI_GET_FW_VERSION 0x02 |
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#define MKHI_END_OF_POST 0x0c |
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#define MKHI_FEATURE_OVERRIDE 0x14 |
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/* Ivybridge only: */ |
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#define MKHI_GLOBAL_RESET 0x0b |
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#define MKHI_FWCAPS_GET_RULE 0x02 |
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#define MKHI_MDES_ENABLE 0x09 |
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/* Broadwell only: */ |
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#define MKHI_GLOBAL_RESET 0x0b |
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#define MKHI_FWCAPS_GET_RULE 0x02 |
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#define MKHI_GROUP_ID_HMRFPO 0x05 |
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#define MKHI_HMRFPO_LOCK 0x02 |
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#define MKHI_HMRFPO_LOCK_NOACK 0x05 |
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#define MKHI_MDES_ENABLE 0x09 |
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#define MKHI_END_OF_POST_NOACK 0x1a |
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struct mkhi_header { |
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u32 group_id:8; |
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u32 command:7; |
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u32 is_response:1; |
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u32 reserved:8; |
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u32 result:8; |
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} __packed; |
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struct me_fw_version { |
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u16 code_minor; |
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u16 code_major; |
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u16 code_build_number; |
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u16 code_hot_fix; |
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u16 recovery_minor; |
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u16 recovery_major; |
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u16 recovery_build_number; |
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u16 recovery_hot_fix; |
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} __packed; |
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#define HECI_EOP_STATUS_SUCCESS 0x0 |
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#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 |
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#define CBM_RR_GLOBAL_RESET 0x01 |
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#define GLOBAL_RESET_BIOS_MRC 0x01 |
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#define GLOBAL_RESET_BIOS_POST 0x02 |
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#define GLOBAL_RESET_MEBX 0x03 |
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struct me_global_reset { |
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u8 request_origin; |
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u8 reset_type; |
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} __packed; |
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enum me_bios_path { |
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ME_NORMAL_BIOS_PATH, |
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ME_S3WAKE_BIOS_PATH, |
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ME_ERROR_BIOS_PATH, |
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ME_RECOVERY_BIOS_PATH, |
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ME_DISABLE_BIOS_PATH, |
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ME_FIRMWARE_UPDATE_BIOS_PATH, |
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}; |
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struct __packed mefwcaps_sku { |
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u32 full_net:1; |
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u32 std_net:1; |
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u32 manageability:1; |
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u32 small_business:1; |
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u32 l3manageability:1; |
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u32 intel_at:1; |
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u32 intel_cls:1; |
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u32 reserved:3; |
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u32 intel_mpc:1; |
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u32 icc_over_clocking:1; |
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u32 pavp:1; |
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u32 reserved_1:4; |
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u32 ipv6:1; |
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u32 kvm:1; |
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u32 och:1; |
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u32 vlan:1; |
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u32 tls:1; |
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u32 reserved_4:1; |
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u32 wlan:1; |
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u32 reserved_5:8; |
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}; |
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struct __packed tdt_state_flag { |
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u16 lock_state:1; |
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u16 authenticate_module:1; |
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u16 s3authentication:1; |
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u16 flash_wear_out:1; |
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u16 flash_variable_security:1; |
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u16 wwan3gpresent:1; /* ivybridge only */ |
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u16 wwan3goob:1; /* ivybridge only */ |
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u16 reserved:9; |
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}; |
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struct __packed tdt_state_info { |
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u8 state; |
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u8 last_theft_trigger; |
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struct tdt_state_flag flags; |
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}; |
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struct __packed mbp_rom_bist_data { |
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u16 device_id; |
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u16 fuse_test_flags; |
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u32 umchid[4]; |
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}; |
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struct __packed mbp_platform_key { |
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u32 key[8]; |
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}; |
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struct __packed mbp_header { |
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u32 mbp_size:8; |
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u32 num_entries:8; |
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u32 rsvd:16; |
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}; |
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struct __packed mbp_item_header { |
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u32 app_id:8; |
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u32 item_id:8; |
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u32 length:8; |
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u32 rsvd:8; |
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}; |
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struct __packed me_fwcaps { |
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u32 id; |
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u8 length; |
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struct mefwcaps_sku caps_sku; |
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u8 reserved[3]; |
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}; |
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/**
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* intel_me_status() - Check Intel Management Engine status |
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* |
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* @me_dev: Management engine PCI device |
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*/ |
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void intel_me_status(struct udevice *me_dev); |
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/**
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* intel_early_me_init() - Early Intel Management Engine init |
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* |
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* @me_dev: Management engine PCI device |
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* @return 0 if OK, -ve on error |
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*/ |
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int intel_early_me_init(struct udevice *me_dev); |
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/**
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* intel_early_me_uma_size() - Get UMA size from the Intel Management Engine |
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* |
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* @me_dev: Management engine PCI device |
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* @return UMA size if OK, -EINVAL on error |
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*/ |
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int intel_early_me_uma_size(struct udevice *me_dev); |
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/**
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* intel_early_me_init_done() - Complete Intel Management Engine init |
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* |
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* @dev: Northbridge device |
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* @me_dev: Management engine PCI device |
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* @status: Status result (ME_INIT_...) |
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* @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT |
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* if ME did not respond |
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*/ |
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int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, |
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uint status); |
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int intel_me_hsio_version(struct udevice *dev, uint16_t *version, |
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uint16_t *checksum); |
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static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr, |
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int offset) |
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{ |
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u32 dword; |
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dm_pci_read_config32(me_dev, offset, &dword); |
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memcpy(ptr, &dword, sizeof(dword)); |
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} |
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static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr, |
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int offset) |
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{ |
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u32 dword = 0; |
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memcpy(&dword, ptr, sizeof(dword)); |
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dm_pci_write_config32(me_dev, offset, dword); |
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} |
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#endif |
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@ -0,0 +1,19 @@ |
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/*
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* Copyright (c) 2016 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __ARCH_REPORT_PLATFORM_H |
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#define __ARCH_REPORT_PLATFORM_H |
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/**
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* report_platform_info() - Report platform information |
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* |
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* This reports information about the CPU and chipset. |
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* |
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* @dev: Northbridge device |
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*/ |
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void report_platform_info(struct udevice *dev); |
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#endif |
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Reference in new issue