Tom Rini
11 years ago
commit
8b906a9f0b
@ -0,0 +1,754 @@ |
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/*
|
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* Copyright (c) 2011-12 The Chromium OS Authors. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but without any warranty; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* This file is derived from the flashrom project. |
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*/ |
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|
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#include <common.h> |
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#include <malloc.h> |
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#include <spi.h> |
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#include <pci.h> |
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#include <pci_ids.h> |
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#include <asm/io.h> |
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#include "ich.h" |
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#define SPI_OPCODE_WREN 0x06 |
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#define SPI_OPCODE_FAST_READ 0x0b |
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struct ich_ctlr { |
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pci_dev_t dev; /* PCI device number */ |
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int ich_version; /* Controller version, 7 or 9 */ |
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int ichspi_lock; |
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int locked; |
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uint8_t *opmenu; |
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int menubytes; |
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void *base; /* Base of register set */ |
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uint16_t *preop; |
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uint16_t *optype; |
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uint32_t *addr; |
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uint8_t *data; |
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unsigned databytes; |
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uint8_t *status; |
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uint16_t *control; |
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uint32_t *bbar; |
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uint32_t *pr; /* only for ich9 */ |
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uint8_t *speed; /* pointer to speed control */ |
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ulong max_speed; /* Maximum bus speed in MHz */ |
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}; |
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struct ich_ctlr ctlr; |
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static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) |
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{ |
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return container_of(slave, struct ich_spi_slave, slave); |
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} |
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static unsigned int ich_reg(const void *addr) |
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{ |
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return (unsigned)(addr - ctlr.base) & 0xffff; |
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} |
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static u8 ich_readb(const void *addr) |
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{ |
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u8 value = readb(addr); |
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debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); |
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return value; |
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} |
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static u16 ich_readw(const void *addr) |
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{ |
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u16 value = readw(addr); |
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debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); |
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return value; |
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} |
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static u32 ich_readl(const void *addr) |
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{ |
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u32 value = readl(addr); |
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debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); |
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return value; |
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} |
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static void ich_writeb(u8 value, void *addr) |
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{ |
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writeb(value, addr); |
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debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); |
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} |
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static void ich_writew(u16 value, void *addr) |
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{ |
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writew(value, addr); |
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debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); |
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} |
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static void ich_writel(u32 value, void *addr) |
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{ |
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writel(value, addr); |
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debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); |
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} |
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static void write_reg(const void *value, void *dest, uint32_t size) |
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{ |
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memcpy_toio(dest, value, size); |
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} |
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static void read_reg(const void *src, void *value, uint32_t size) |
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{ |
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memcpy_fromio(value, src, size); |
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} |
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static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) |
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{ |
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const uint32_t bbar_mask = 0x00ffff00; |
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uint32_t ichspi_bbar; |
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minaddr &= bbar_mask; |
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ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; |
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ichspi_bbar |= minaddr; |
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ich_writel(ichspi_bbar, ctlr->bbar); |
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} |
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int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
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{ |
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puts("spi_cs_is_valid used but not implemented\n"); |
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return 0; |
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} |
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct ich_spi_slave *ich; |
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ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); |
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if (!ich) { |
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puts("ICH SPI: Out of memory\n"); |
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return NULL; |
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} |
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/*
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* Yes this controller can only write a small number of bytes at |
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* once! The limit is typically 64 bytes. |
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*/ |
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ich->slave.max_write_size = ctlr.databytes; |
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ich->speed = max_hz; |
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return &ich->slave; |
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} |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct ich_spi_slave *ich = to_ich_spi(slave); |
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free(ich); |
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} |
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/*
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* Check if this device ID matches one of supported Intel PCH devices. |
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* |
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* Return the ICH version if there is a match, or zero otherwise. |
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*/ |
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static int get_ich_version(uint16_t device_id) |
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{ |
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if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) |
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return 7; |
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if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && |
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device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || |
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(device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && |
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device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) |
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return 9; |
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return 0; |
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} |
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/* @return 1 if the SPI flash supports the 33MHz speed */ |
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static int ich9_can_do_33mhz(pci_dev_t dev) |
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{ |
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u32 fdod, speed; |
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/* Observe SPI Descriptor Component Section 0 */ |
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pci_write_config_dword(dev, 0xb0, 0x1000); |
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/* Extract the Write/Erase SPI Frequency from descriptor */ |
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pci_read_config_dword(dev, 0xb4, &fdod); |
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/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ |
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speed = (fdod >> 21) & 7; |
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return speed == 1; |
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} |
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static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) |
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{ |
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int last_bus = pci_last_busno(); |
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int bus; |
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if (last_bus == -1) { |
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debug("No PCI busses?\n"); |
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return -1; |
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} |
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for (bus = 0; bus <= last_bus; bus++) { |
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uint16_t vendor_id, device_id; |
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uint32_t ids; |
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pci_dev_t dev; |
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dev = PCI_BDF(bus, 31, 0); |
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pci_read_config_dword(dev, 0, &ids); |
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vendor_id = ids; |
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device_id = ids >> 16; |
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if (vendor_id == PCI_VENDOR_ID_INTEL) { |
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*devp = dev; |
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*ich_versionp = get_ich_version(device_id); |
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return 0; |
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} |
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} |
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debug("ICH SPI: No ICH found.\n"); |
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return -1; |
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} |
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static int ich_init_controller(struct ich_ctlr *ctlr) |
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{ |
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uint8_t *rcrb; /* Root Complex Register Block */ |
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uint32_t rcba; /* Root Complex Base Address */ |
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pci_read_config_dword(ctlr->dev, 0xf0, &rcba); |
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
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rcrb = (uint8_t *)(rcba & 0xffffc000); |
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if (ctlr->ich_version == 7) { |
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struct ich7_spi_regs *ich7_spi; |
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ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); |
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ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; |
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ctlr->opmenu = ich7_spi->opmenu; |
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ctlr->menubytes = sizeof(ich7_spi->opmenu); |
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ctlr->optype = &ich7_spi->optype; |
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ctlr->addr = &ich7_spi->spia; |
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ctlr->data = (uint8_t *)ich7_spi->spid; |
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ctlr->databytes = sizeof(ich7_spi->spid); |
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ctlr->status = (uint8_t *)&ich7_spi->spis; |
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ctlr->control = &ich7_spi->spic; |
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ctlr->bbar = &ich7_spi->bbar; |
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ctlr->preop = &ich7_spi->preop; |
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ctlr->base = ich7_spi; |
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} else if (ctlr->ich_version == 9) { |
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struct ich9_spi_regs *ich9_spi; |
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ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); |
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ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
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ctlr->opmenu = ich9_spi->opmenu; |
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ctlr->menubytes = sizeof(ich9_spi->opmenu); |
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ctlr->optype = &ich9_spi->optype; |
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ctlr->addr = &ich9_spi->faddr; |
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ctlr->data = (uint8_t *)ich9_spi->fdata; |
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ctlr->databytes = sizeof(ich9_spi->fdata); |
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ctlr->status = &ich9_spi->ssfs; |
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ctlr->control = (uint16_t *)ich9_spi->ssfc; |
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ctlr->speed = ich9_spi->ssfc + 2; |
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ctlr->bbar = &ich9_spi->bbar; |
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ctlr->preop = &ich9_spi->preop; |
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ctlr->pr = &ich9_spi->pr[0]; |
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ctlr->base = ich9_spi; |
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} else { |
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debug("ICH SPI: Unrecognized ICH version %d.\n", |
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ctlr->ich_version); |
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return -1; |
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} |
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debug("ICH SPI: Version %d detected\n", ctlr->ich_version); |
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/* Work out the maximum speed we can support */ |
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ctlr->max_speed = 20000000; |
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if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) |
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ctlr->max_speed = 33000000; |
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ich_set_bbar(ctlr, 0); |
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return 0; |
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} |
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void spi_init(void) |
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{ |
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uint8_t bios_cntl; |
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if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { |
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printf("ICH SPI: Cannot find device\n"); |
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return; |
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} |
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if (ich_init_controller(&ctlr)) { |
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printf("ICH SPI: Cannot setup controller\n"); |
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return; |
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} |
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/*
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* Disable the BIOS write protect so write commands are allowed. On |
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* v9, deassert SMM BIOS Write Protect Disable. |
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*/ |
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pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); |
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if (ctlr.ich_version == 9) |
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bios_cntl &= ~(1 << 5); |
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pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); |
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} |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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/* Handled by ICH automatically. */ |
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return 0; |
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} |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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/* Handled by ICH automatically. */ |
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} |
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void spi_cs_activate(struct spi_slave *slave) |
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{ |
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/* Handled by ICH automatically. */ |
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} |
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void spi_cs_deactivate(struct spi_slave *slave) |
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{ |
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/* Handled by ICH automatically. */ |
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} |
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static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) |
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{ |
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trans->out += bytes; |
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trans->bytesout -= bytes; |
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} |
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static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) |
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{ |
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trans->in += bytes; |
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trans->bytesin -= bytes; |
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} |
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static void spi_setup_type(struct spi_trans *trans, int data_bytes) |
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{ |
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trans->type = 0xFF; |
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/* Try to guess spi type from read/write sizes. */ |
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if (trans->bytesin == 0) { |
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if (trans->bytesout + data_bytes > 4) |
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/*
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* If bytesin = 0 and bytesout > 4, we presume this is |
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* a write data operation, which is accompanied by an |
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* address. |
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*/ |
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
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else |
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
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return; |
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} |
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if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
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return; |
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} |
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if (trans->bytesout == 4) /* and bytesin is > 0 */ |
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
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/* Fast read command is called with 5 bytes instead of 4 */ |
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if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
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--trans->bytesout; |
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} |
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} |
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static int spi_setup_opcode(struct spi_trans *trans) |
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{ |
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uint16_t optypes; |
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uint8_t opmenu[ctlr.menubytes]; |
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trans->opcode = trans->out[0]; |
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spi_use_out(trans, 1); |
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if (!ctlr.ichspi_lock) { |
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/* The lock is off, so just use index 0. */ |
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ich_writeb(trans->opcode, ctlr.opmenu); |
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optypes = ich_readw(ctlr.optype); |
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optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
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ich_writew(optypes, ctlr.optype); |
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return 0; |
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} else { |
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/* The lock is on. See if what we need is on the menu. */ |
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uint8_t optype; |
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uint16_t opcode_index; |
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/* Write Enable is handled as atomic prefix */ |
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if (trans->opcode == SPI_OPCODE_WREN) |
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return 0; |
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read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); |
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for (opcode_index = 0; opcode_index < ctlr.menubytes; |
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opcode_index++) { |
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if (opmenu[opcode_index] == trans->opcode) |
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break; |
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} |
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if (opcode_index == ctlr.menubytes) { |
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printf("ICH SPI: Opcode %x not found\n", |
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trans->opcode); |
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return -1; |
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} |
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optypes = ich_readw(ctlr.optype); |
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optype = (optypes >> (opcode_index * 2)) & 0x3; |
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
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trans->bytesout >= 3) { |
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/* We guessed wrong earlier. Fix it up. */ |
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trans->type = optype; |
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} |
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if (optype != trans->type) { |
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printf("ICH SPI: Transaction doesn't fit type %d\n", |
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optype); |
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return -1; |
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} |
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return opcode_index; |
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} |
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} |
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|
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static int spi_setup_offset(struct spi_trans *trans) |
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{ |
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/* Separate the SPI address and data. */ |
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switch (trans->type) { |
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case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
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case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
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return 0; |
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case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
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case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
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trans->offset = ((uint32_t)trans->out[0] << 16) | |
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((uint32_t)trans->out[1] << 8) | |
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((uint32_t)trans->out[2] << 0); |
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spi_use_out(trans, 3); |
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return 1; |
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default: |
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printf("Unrecognized SPI transaction type %#x\n", trans->type); |
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return -1; |
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} |
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} |
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|
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/*
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set |
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* below is True) or 0. In case the wait was for the bit(s) to set - write |
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* those bits back, which would cause resetting them. |
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* |
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* Return the last read status value on success or -1 on failure. |
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*/ |
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static int ich_status_poll(u16 bitmask, int wait_til_set) |
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{ |
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int timeout = 600000; /* This will result in 6s */ |
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u16 status = 0; |
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|
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while (timeout--) { |
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status = ich_readw(ctlr.status); |
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if (wait_til_set ^ ((status & bitmask) == 0)) { |
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if (wait_til_set) |
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ich_writew((status & bitmask), ctlr.status); |
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return status; |
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} |
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udelay(10); |
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} |
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|
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printf("ICH SPI: SCIP timeout, read %x, expected %x\n", |
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status, bitmask); |
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return -1; |
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} |
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|
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/*
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int spi_xfer(struct spi_slave *slave, const void *dout, |
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unsigned int bitsout, void *din, unsigned int bitsin) |
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*/ |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, |
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void *din, unsigned long flags) |
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{ |
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struct ich_spi_slave *ich = to_ich_spi(slave); |
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uint16_t control; |
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int16_t opcode_index; |
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int with_address; |
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int status; |
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int bytes = bitlen / 8; |
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struct spi_trans *trans = &ich->trans; |
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unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); |
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int using_cmd = 0; |
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/* Align read transactions to 64-byte boundaries */ |
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char buff[ctlr.databytes]; |
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|
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/* Ee don't support writing partial bytes. */ |
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if (bitlen % 8) { |
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debug("ICH SPI: Accessing partial bytes not supported\n"); |
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return -1; |
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} |
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|
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/* An empty end transaction can be ignored */ |
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if (type == SPI_XFER_END && !dout && !din) |
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return 0; |
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|
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if (type & SPI_XFER_BEGIN) |
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memset(trans, '\0', sizeof(*trans)); |
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|
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/* Dp we need to come back later to finish it? */ |
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if (dout && type == SPI_XFER_BEGIN) { |
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if (bytes > ICH_MAX_CMD_LEN) { |
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debug("ICH SPI: Command length limit exceeded\n"); |
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return -1; |
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} |
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memcpy(trans->cmd, dout, bytes); |
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trans->cmd_len = bytes; |
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debug("ICH SPI: Saved %d bytes\n", bytes); |
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return 0; |
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} |
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|
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/*
|
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* We process a 'middle' spi_xfer() call, which has no |
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* SPI_XFER_BEGIN/END, as an independent transaction as if it had |
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* an end. We therefore repeat the command. This is because ICH |
||||
* seems to have no support for this, or because interest (in digging |
||||
* out the details and creating a special case in the code) is low. |
||||
*/ |
||||
if (trans->cmd_len) { |
||||
trans->out = trans->cmd; |
||||
trans->bytesout = trans->cmd_len; |
||||
using_cmd = 1; |
||||
debug("ICH SPI: Using %d bytes\n", trans->cmd_len); |
||||
} else { |
||||
trans->out = dout; |
||||
trans->bytesout = dout ? bytes : 0; |
||||
} |
||||
|
||||
trans->in = din; |
||||
trans->bytesin = din ? bytes : 0; |
||||
|
||||
/* There has to always at least be an opcode. */ |
||||
if (!trans->bytesout) { |
||||
debug("ICH SPI: No opcode for transfer\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (ich_status_poll(SPIS_SCIP, 0) == -1) |
||||
return -1; |
||||
|
||||
ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); |
||||
|
||||
spi_setup_type(trans, using_cmd ? bytes : 0); |
||||
opcode_index = spi_setup_opcode(trans); |
||||
if (opcode_index < 0) |
||||
return -1; |
||||
with_address = spi_setup_offset(trans); |
||||
if (with_address < 0) |
||||
return -1; |
||||
|
||||
if (trans->opcode == SPI_OPCODE_WREN) { |
||||
/*
|
||||
* Treat Write Enable as Atomic Pre-Op if possible |
||||
* in order to prevent the Management Engine from |
||||
* issuing a transaction between WREN and DATA. |
||||
*/ |
||||
if (!ctlr.ichspi_lock) |
||||
ich_writew(trans->opcode, ctlr.preop); |
||||
return 0; |
||||
} |
||||
|
||||
if (ctlr.speed && ctlr.max_speed >= 33000000) { |
||||
int byte; |
||||
|
||||
byte = ich_readb(ctlr.speed); |
||||
if (ich->speed >= 33000000) |
||||
byte |= SSFC_SCF_33MHZ; |
||||
else |
||||
byte &= ~SSFC_SCF_33MHZ; |
||||
ich_writeb(byte, ctlr.speed); |
||||
} |
||||
|
||||
/* See if we have used up the command data */ |
||||
if (using_cmd && dout && bytes) { |
||||
trans->out = dout; |
||||
trans->bytesout = bytes; |
||||
debug("ICH SPI: Moving to data, %d bytes\n", bytes); |
||||
} |
||||
|
||||
/* Preset control fields */ |
||||
control = ich_readw(ctlr.control); |
||||
control &= ~SSFC_RESERVED; |
||||
control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
||||
|
||||
/* Issue atomic preop cycle if needed */ |
||||
if (ich_readw(ctlr.preop)) |
||||
control |= SPIC_ACS; |
||||
|
||||
if (!trans->bytesout && !trans->bytesin) { |
||||
/* SPI addresses are 24 bit only */ |
||||
if (with_address) |
||||
ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); |
||||
|
||||
/*
|
||||
* This is a 'no data' command (like Write Enable), its |
||||
* bitesout size was 1, decremented to zero while executing |
||||
* spi_setup_opcode() above. Tell the chip to send the |
||||
* command. |
||||
*/ |
||||
ich_writew(control, ctlr.control); |
||||
|
||||
/* wait for the result */ |
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
||||
if (status == -1) |
||||
return -1; |
||||
|
||||
if (status & SPIS_FCERR) { |
||||
debug("ICH SPI: Command transaction error\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Check if this is a write command atempting to transfer more bytes |
||||
* than the controller can handle. Iterations for writes are not |
||||
* supported here because each SPI write command needs to be preceded |
||||
* and followed by other SPI commands, and this sequence is controlled |
||||
* by the SPI chip driver. |
||||
*/ |
||||
if (trans->bytesout > ctlr.databytes) { |
||||
debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Read or write up to databytes bytes at a time until everything has |
||||
* been sent. |
||||
*/ |
||||
while (trans->bytesout || trans->bytesin) { |
||||
uint32_t data_length; |
||||
uint32_t aligned_offset; |
||||
uint32_t diff; |
||||
|
||||
aligned_offset = trans->offset & ~(ctlr.databytes - 1); |
||||
diff = trans->offset - aligned_offset; |
||||
|
||||
/* SPI addresses are 24 bit only */ |
||||
ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr); |
||||
|
||||
if (trans->bytesout) |
||||
data_length = min(trans->bytesout, ctlr.databytes); |
||||
else |
||||
data_length = min(trans->bytesin, ctlr.databytes); |
||||
|
||||
/* Program data into FDATA0 to N */ |
||||
if (trans->bytesout) { |
||||
write_reg(trans->out, ctlr.data, data_length); |
||||
spi_use_out(trans, data_length); |
||||
if (with_address) |
||||
trans->offset += data_length; |
||||
} |
||||
|
||||
/* Add proper control fields' values */ |
||||
control &= ~((ctlr.databytes - 1) << 8); |
||||
control |= SPIC_DS; |
||||
control |= (data_length - 1) << 8; |
||||
|
||||
/* write it */ |
||||
ich_writew(control, ctlr.control); |
||||
|
||||
/* Wait for Cycle Done Status or Flash Cycle Error. */ |
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
||||
if (status == -1) |
||||
return -1; |
||||
|
||||
if (status & SPIS_FCERR) { |
||||
debug("ICH SPI: Data transaction error\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (trans->bytesin) { |
||||
if (diff) { |
||||
data_length -= diff; |
||||
read_reg(ctlr.data, buff, ctlr.databytes); |
||||
memcpy(trans->in, buff + diff, data_length); |
||||
} else { |
||||
read_reg(ctlr.data, trans->in, data_length); |
||||
} |
||||
spi_use_in(trans, data_length); |
||||
if (with_address) |
||||
trans->offset += data_length; |
||||
} |
||||
} |
||||
|
||||
/* Clear atomic preop now that xfer is done */ |
||||
ich_writew(0, ctlr.preop); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* This uses the SPI controller from the Intel Cougar Point and Panther Point |
||||
* PCH to write-protect portions of the SPI flash until reboot. The changes |
||||
* don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's |
||||
* done elsewhere. |
||||
*/ |
||||
int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) |
||||
{ |
||||
uint32_t tmplong; |
||||
uint32_t upper_limit; |
||||
|
||||
if (!ctlr.pr) { |
||||
printf("%s: operation not supported on this chipset\n", |
||||
__func__); |
||||
return -1; |
||||
} |
||||
|
||||
if (length == 0 || |
||||
lower_limit > (0xFFFFFFFFUL - length) + 1 || |
||||
hint < 0 || hint > 4) { |
||||
printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, |
||||
lower_limit, length, hint); |
||||
return -1; |
||||
} |
||||
|
||||
upper_limit = lower_limit + length - 1; |
||||
|
||||
/*
|
||||
* Determine bits to write, as follows: |
||||
* 31 Write-protection enable (includes erase operation) |
||||
* 30:29 reserved |
||||
* 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) |
||||
* 15 Read-protection enable |
||||
* 14:13 reserved |
||||
* 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) |
||||
*/ |
||||
tmplong = 0x80000000 | |
||||
((upper_limit & 0x01fff000) << 4) | |
||||
((lower_limit & 0x01fff000) >> 12); |
||||
|
||||
printf("%s: writing 0x%08x to %p\n", __func__, tmplong, |
||||
&ctlr.pr[hint]); |
||||
ctlr.pr[hint] = tmplong; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,143 @@ |
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but without any warranty; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* This file is derived from the flashrom project. |
||||
*/ |
||||
|
||||
struct ich7_spi_regs { |
||||
uint16_t spis; |
||||
uint16_t spic; |
||||
uint32_t spia; |
||||
uint64_t spid[8]; |
||||
uint64_t _pad; |
||||
uint32_t bbar; |
||||
uint16_t preop; |
||||
uint16_t optype; |
||||
uint8_t opmenu[8]; |
||||
} __packed; |
||||
|
||||
struct ich9_spi_regs { |
||||
uint32_t bfpr; /* 0x00 */ |
||||
uint16_t hsfs; |
||||
uint16_t hsfc; |
||||
uint32_t faddr; |
||||
uint32_t _reserved0; |
||||
uint32_t fdata[16]; /* 0x10 */ |
||||
uint32_t frap; /* 0x50 */ |
||||
uint32_t freg[5]; |
||||
uint32_t _reserved1[3]; |
||||
uint32_t pr[5]; /* 0x74 */ |
||||
uint32_t _reserved2[2]; |
||||
uint8_t ssfs; /* 0x90 */ |
||||
uint8_t ssfc[3]; |
||||
uint16_t preop; /* 0x94 */ |
||||
uint16_t optype; |
||||
uint8_t opmenu[8]; /* 0x98 */ |
||||
uint32_t bbar; |
||||
uint8_t _reserved3[12]; |
||||
uint32_t fdoc; |
||||
uint32_t fdod; |
||||
uint8_t _reserved4[8]; |
||||
uint32_t afc; |
||||
uint32_t lvscc; |
||||
uint32_t uvscc; |
||||
uint8_t _reserved5[4]; |
||||
uint32_t fpb; |
||||
uint8_t _reserved6[28]; |
||||
uint32_t srdl; |
||||
uint32_t srdc; |
||||
uint32_t srd; |
||||
} __packed; |
||||
|
||||
enum { |
||||
SPIS_SCIP = 0x0001, |
||||
SPIS_GRANT = 0x0002, |
||||
SPIS_CDS = 0x0004, |
||||
SPIS_FCERR = 0x0008, |
||||
SSFS_AEL = 0x0010, |
||||
SPIS_LOCK = 0x8000, |
||||
SPIS_RESERVED_MASK = 0x7ff0, |
||||
SSFS_RESERVED_MASK = 0x7fe2 |
||||
}; |
||||
|
||||
enum { |
||||
SPIC_SCGO = 0x000002, |
||||
SPIC_ACS = 0x000004, |
||||
SPIC_SPOP = 0x000008, |
||||
SPIC_DBC = 0x003f00, |
||||
SPIC_DS = 0x004000, |
||||
SPIC_SME = 0x008000, |
||||
SSFC_SCF_MASK = 0x070000, |
||||
SSFC_RESERVED = 0xf80000, |
||||
|
||||
/* Mask for speed byte, biuts 23:16 of SSFC */ |
||||
SSFC_SCF_33MHZ = 0x01, |
||||
}; |
||||
|
||||
enum { |
||||
HSFS_FDONE = 0x0001, |
||||
HSFS_FCERR = 0x0002, |
||||
HSFS_AEL = 0x0004, |
||||
HSFS_BERASE_MASK = 0x0018, |
||||
HSFS_BERASE_SHIFT = 3, |
||||
HSFS_SCIP = 0x0020, |
||||
HSFS_FDOPSS = 0x2000, |
||||
HSFS_FDV = 0x4000, |
||||
HSFS_FLOCKDN = 0x8000 |
||||
}; |
||||
|
||||
enum { |
||||
HSFC_FGO = 0x0001, |
||||
HSFC_FCYCLE_MASK = 0x0006, |
||||
HSFC_FCYCLE_SHIFT = 1, |
||||
HSFC_FDBC_MASK = 0x3f00, |
||||
HSFC_FDBC_SHIFT = 8, |
||||
HSFC_FSMIE = 0x8000 |
||||
}; |
||||
|
||||
enum { |
||||
SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
||||
SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
||||
SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
||||
SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
||||
}; |
||||
|
||||
enum { |
||||
ICH_MAX_CMD_LEN = 5, |
||||
}; |
||||
|
||||
struct spi_trans { |
||||
uint8_t cmd[ICH_MAX_CMD_LEN]; |
||||
int cmd_len; |
||||
const uint8_t *out; |
||||
uint32_t bytesout; |
||||
uint8_t *in; |
||||
uint32_t bytesin; |
||||
uint8_t type; |
||||
uint8_t opcode; |
||||
uint32_t offset; |
||||
}; |
||||
|
||||
struct ich_spi_slave { |
||||
struct spi_slave slave; |
||||
struct spi_trans trans; /* current transaction in progress */ |
||||
int speed; /* SPI speed in Hz */ |
||||
}; |
||||
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but without any warranty; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <spi.h> |
||||
|
||||
void *spi_do_alloc_slave(int offset, int size, unsigned int bus, |
||||
unsigned int cs) |
||||
{ |
||||
struct spi_slave *slave; |
||||
void *ptr; |
||||
|
||||
ptr = malloc(size); |
||||
if (ptr) { |
||||
memset(ptr, '\0', size); |
||||
slave = (struct spi_slave *)(ptr + offset); |
||||
slave->bus = bus; |
||||
slave->cs = cs; |
||||
} |
||||
|
||||
return ptr; |
||||
} |
||||
Loading…
Reference in new issue