The features list: - Boot from NOR Flash - DDR2 266MHz hardcoded configuration - Local bus NOR Flash R/W operation - I2C, UART, MII and RTC - eTSEC0/1 support - PCI host Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>master
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1 @@ |
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,132 @@ |
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* |
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* Author: Scott Wood <scottwood@freescale.com> |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <i2c.h> |
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#if defined(CONFIG_OF_LIBFDT) |
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#include <libfdt.h> |
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#endif |
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#include <pci.h> |
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#include <mpc83xx.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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volatile immap_t *im = (immap_t *)CFG_IMMR; |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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gd->flags |= GD_FLG_SILENT; |
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return 0; |
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} |
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static u8 read_board_info(void) |
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{ |
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u8 val8; |
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i2c_set_bus_num(0); |
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if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) |
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return val8; |
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else |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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static const char * const rev_str[] = { |
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"0.0", |
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"0.1", |
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"1.0", |
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"1.1", |
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"<unknown>", |
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}; |
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u8 info; |
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int i; |
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info = read_board_info(); |
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i = (!info) ? 4: info & 0x03; |
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printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]); |
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return 0; |
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} |
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static struct pci_region pci_regions[] = { |
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{ |
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bus_start: CFG_PCI_MEM_BASE, |
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phys_start: CFG_PCI_MEM_PHYS, |
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size: CFG_PCI_MEM_SIZE, |
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
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}, |
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{ |
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bus_start: CFG_PCI_MMIO_BASE, |
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phys_start: CFG_PCI_MMIO_PHYS, |
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size: CFG_PCI_MMIO_SIZE, |
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flags: PCI_REGION_MEM |
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}, |
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{ |
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bus_start: CFG_PCI_IO_BASE, |
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phys_start: CFG_PCI_IO_PHYS, |
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size: CFG_PCI_IO_SIZE, |
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flags: PCI_REGION_IO |
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} |
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}; |
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void pci_init_board(void) |
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{ |
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volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
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struct pci_region *reg[] = { pci_regions }; |
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int warmboot; |
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/* Enable all 3 PCI_CLK_OUTPUTs. */ |
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clk->occr |= 0xe0000000; |
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/*
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* Configure PCI Local Access Windows |
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*/ |
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pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; |
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
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pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; |
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; |
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warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; |
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mpc83xx_pci_init(1, reg, warmboot); |
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} |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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} |
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#endif |
@ -0,0 +1,120 @@ |
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* |
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* Authors: Nick.Spence@freescale.com |
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* Wilson.Lo@freescale.com |
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* scottwood@freescale.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc83xx.h> |
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#include <spd_sdram.h> |
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#include <asm/bitops.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static void resume_from_sleep(void) |
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{ |
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u32 magic = *(u32 *)0; |
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typedef void (*func_t)(void); |
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func_t resume = *(func_t *)4; |
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if (magic == 0xf5153ae5) |
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resume(); |
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gd->flags &= ~GD_FLG_SILENT; |
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puts("\nResume from sleep failed: bad magic word\n"); |
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} |
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/* Fixed sdram init -- doesn't use serial presence detect.
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* |
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* This is useful for faster booting in configs where the RAM is unlikely |
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* to be changed, or for things like NAND booting where space is tight. |
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*/ |
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static long fixed_sdram(void) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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u32 msize = CFG_DDR_SIZE * 1024 * 1024; |
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u32 msize_log2 = __ilog2(msize); |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; |
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); |
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im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; |
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], |
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* or the DDR2 controller may fail to initialize correctly. |
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*/ |
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udelay(50000); |
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im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; |
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; |
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/* Currently we use only one CS, so disable the other bank. */ |
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im->ddr.cs_config[1] = 0; |
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im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; |
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI; |
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else |
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_mode2 = CFG_DDR_MODE2; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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sync(); |
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/* enable DDR controller */ |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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sync(); |
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return msize; |
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} |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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u32 msize; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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/* DDR SDRAM */ |
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msize = fixed_sdram(); |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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resume_from_sleep(); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return msize; |
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} |
@ -0,0 +1,80 @@ |
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Freescale MPC8315ERDB Board |
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----------------------------------------- |
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1. Board Switches and Jumpers |
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S3 is used to set CFG_RESET_SOURCE. |
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To boot the image at 0xFE000000 in NOR flash, use these DIP |
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switche settings for S3 S4: |
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+------+ +------+ |
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| | | **** | |
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| **** | | | |
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+------+ ON +------+ ON |
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4321 4321 |
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(where the '*' indicates the position of the tab of the switch.) |
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2. Memory Map |
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The memory map looks like this: |
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0x0000_0000 0x07ff_ffff DDR 128M |
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0x8000_0000 0x8fff_ffff PCI MEM 256M |
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0x9000_0000 0x9fff_ffff PCI_MMIO 256M |
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0xe000_0000 0xe00f_ffff IMMR 1M |
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0xe030_0000 0xe03f_ffff PCI IO 1M |
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0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K |
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0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M |
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3. Definitions |
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3.1 Explanation of NEW definitions in: |
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include/configs/MPC8315ERDB.h |
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CONFIG_MPC83xx MPC83xx family |
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CONFIG_MPC831x MPC831x specific |
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CONFIG_MPC8315 MPC8315 specific |
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CONFIG_MPC8315ERDB MPC8315ERDB board specific |
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4. Compilation |
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Assuming you're using BASH (or similar) as your shell: |
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export CROSS_COMPILE=your-cross-compiler-prefix- |
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make distclean |
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make MPC8315ERDB_config |
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make all |
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|
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5. Downloading and Flashing Images |
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5.1 Reflash U-boot Image using U-boot |
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tftp 40000 u-boot.bin |
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protect off all |
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erase fe000000 fe1fffff |
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cp.b 40000 fe000000 xxxx |
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protect on all |
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|
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You have to supply the correct byte count with 'xxxx' |
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from the TFTP result log. |
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|
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5.2 Downloading and Booting Linux Kernel |
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|
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Ensure that all networking-related environment variables are set |
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properly (including ipaddr, serverip, gatewayip (if needed), |
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netmask, ethaddr, eth1addr, rootpath (if using NFS root), |
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fdtfile, and bootfile). |
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|
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Then, do one of the following, depending on whether you |
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want an NFS root or a ramdisk root: |
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|
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=>run nfsboot |
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or |
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=>run ramboot |
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|
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6 Notes |
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|
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Booting from NAND flash is not yet supported. |
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The console baudrate for MPC8315ERDB is 115200bps. |
@ -0,0 +1,547 @@ |
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/*
|
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* Copyright (C) 2007 Freescale Semiconductor, Inc. |
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* |
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* Dave Liu <daveliu@freescale.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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|
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#undef DEBUG |
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|
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/*
|
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* High Level Configuration Options |
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*/ |
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#define CONFIG_E300 1 /* E300 family */ |
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#define CONFIG_MPC83XX 1 /* MPC83xx family */ |
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#define CONFIG_MPC831X 1 /* MPC831x CPU family */ |
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#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ |
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#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ |
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|
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/*
|
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* System Clock Setup |
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*/ |
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#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
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|
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/*
|
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* Hardware Reset Configuration Word |
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* if CLKIN is 66.66MHz, then |
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* CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz |
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*/ |
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#define CFG_HRCW_LOW (\ |
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
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HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
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HRCWL_SVCOD_DIV_2 |\
|
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HRCWL_CSB_TO_CLKIN_2X1 |\
|
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HRCWL_CORE_TO_CSB_3X1) |
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#define CFG_HRCW_HIGH (\ |
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HRCWH_PCI_HOST |\
|
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HRCWH_PCI1_ARBITER_ENABLE |\
|
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HRCWH_CORE_ENABLE |\
|
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HRCWH_FROM_0X00000100 |\
|
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HRCWH_BOOTSEQ_DISABLE |\
|
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HRCWH_SW_WATCHDOG_DISABLE |\
|
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HRCWH_ROM_LOC_LOCAL_16BIT |\
|
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HRCWH_RL_EXT_LEGACY |\
|
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HRCWH_TSEC1M_IN_RGMII |\
|
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HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
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HRCWH_LALE_NORMAL) |
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|
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/*
|
||||
* System IO Config |
||||
*/ |
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#define CFG_SICRH 0x00000000 |
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#define CFG_SICRL 0x00000000 /* 3.3V, no delay */ |
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|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
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|
||||
/*
|
||||
* IMMR new address |
||||
*/ |
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#define CFG_IMMR 0xE0000000 |
||||
|
||||
/*
|
||||
* Arbiter Setup |
||||
*/ |
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
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#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
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#define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ |
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|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ |
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#define CFG_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
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#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
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#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ |
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| DDRCDR_PZ_LOZ \
|
||||
| DDRCDR_NZ_LOZ \
|
||||
| DDRCDR_ODT \
|
||||
| DDRCDR_Q_DRN ) |
||||
/* 0x7b880001 */ |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
* consist of two chips HY5PS12621BFP-C4 from HYNIX |
||||
*/ |
||||
#define CFG_DDR_SIZE 128 /* MB */ |
||||
#define CFG_DDR_CS0_BNDS 0x00000007 |
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#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ |
||||
| 0x00010000 /* ODT_WR to CSn */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) |
||||
/* 0x80010102 */ |
||||
#define CFG_DDR_TIMING_3 0x00000000 |
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#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ |
||||
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
|
||||
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) |
||||
/* 0x00220802 */ |
||||
#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
||||
| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
|
||||
| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) |
||||
/* 0x39356222 */ |
||||
#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
||||
| ( 4 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
|
||||
| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
||||
/* 0x121048c7 */ |
||||
#define CFG_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
||||
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
||||
/* 0x03600100 */ |
||||
#define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ |
||||
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
|
||||
| SDRAM_CFG_32_BE ) |
||||
/* 0x43080000 */ |
||||
#define CFG_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
||||
#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ |
||||
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) |
||||
/* ODT 150ohm CL=3, AL=1 on SDRAM */ |
||||
#define CFG_DDR_MODE2 0x00000000 |
||||
|
||||
/*
|
||||
* Memory test |
||||
*/ |
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00040000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00140000 |
||||
|
||||
/*
|
||||
* The reserved memory |
||||
*/ |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup |
||||
*/ |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ |
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) |
||||
#define CFG_LBC_LBCR 0x00040000 |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
|
||||
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ |
||||
#define CFG_FLASH_SIZE 8 /* FLASH size is 8M */ |
||||
|
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ |
||||
|
||||
#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ |
||||
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
|
||||
| BR_V ) /* valid */ |
||||
#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ |
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_0b11 \
|
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 \
|
||||
| OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD ) |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
/*
|
||||
* NAND Flash on the Local Bus |
||||
*/ |
||||
#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
|
||||
#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */ |
||||
#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR ) |
||||
/* 0xFFFF8396 */ |
||||
|
||||
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* Pass open firmware flat tree */ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
|
||||
/*
|
||||
* Board info - revision and where boot from |
||||
*/ |
||||
#define CFG_I2C_PCF8574A_ADDR 0x39 |
||||
|
||||
/*
|
||||
* Config on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI_MEM_BASE 0x80000000 |
||||
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE |
||||
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE |
||||
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI_IO_BASE 0xE0300000 |
||||
#define CFG_PCI_IO_PHYS 0xE0300000 |
||||
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ |
||||
|
||||
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE |
||||
#define CFG_PCI_SLV_MEM_BUS 0x00000000 |
||||
#define CFG_PCI_SLV_MEM_SIZE 0x80000000 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#define CONFIG_EEPRO100 |
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* TSEC |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) |
||||
|
||||
/*
|
||||
* TSEC ethernet configuration |
||||
*/ |
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_TSEC1 1 |
||||
#define CONFIG_TSEC1_NAME "eTSEC0" |
||||
#define CONFIG_TSEC2 1 |
||||
#define CONFIG_TSEC2_NAME "eTSEC1" |
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC1_FLAGS TSEC_GIGABIT |
||||
#define TSEC2_FLAGS TSEC_GIGABIT |
||||
|
||||
/* Options are: eTSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "eTSEC1" |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_PCI |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#undef CONFIG_CMD_ENV |
||||
#undef CONFIG_CMD_LOADS |
||||
#endif |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Core HID Setup |
||||
*/ |
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/*
|
||||
* MMU Setup |
||||
*/ |
||||
|
||||
/* DDR: cache cacheable */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
|
||||
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ |
||||
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ |
||||
#define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */ |
||||
#define CFG_IBAT3L (CFG_INIT_RAM_ADDR | BATL_PP_10) |
||||
#define CFG_IBAT3U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/* PCI MEM space: cacheable */ |
||||
#define CFG_IBAT4L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT4U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
|
||||
/* PCI MMIO space: cache-inhibit and guarded */ |
||||
#define CFG_IBAT5L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ |
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT5U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
|
||||
#define CFG_IBAT6L 0 |
||||
#define CFG_IBAT6U 0 |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
|
||||
#define CFG_IBAT7L 0 |
||||
#define CFG_IBAT7U 0 |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_ETHADDR 04:00:00:00:00:0A |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 04:00:00:00:00:0B |
||||
#endif |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=1000000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=mpc8315erdb.dtb\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue