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@ -95,7 +95,7 @@ void pci_init_board(void) |
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
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SET_STD_PCI_INFO(pci_info[num], 1); |
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pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); |
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printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", |
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printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", |
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pci_32 ? 32 : 64, |
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pcix ? "PCIX" : "PCI", |
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pci_spd_norm ? ">=" : "<=", |
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@ -106,7 +106,7 @@ void pci_init_board(void) |
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first_free_busno = fsl_pci_init_port(&pci_info[num++], |
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&pci1_hose, first_free_busno); |
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} else { |
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printf(" PCI1: disabled\n"); |
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printf("PCI1: disabled\n"); |
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} |
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#elif defined CONFIG_MPC8548 |
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/* PCI1 not present on MPC8572 */ |
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@ -119,12 +119,12 @@ void pci_init_board(void) |
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { |
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SET_STD_PCIE_INFO(pci_info[num], 1); |
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); |
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printf(" PCIE1 connected as %s\n", |
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printf("PCIE1: connected as %s\n", |
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pcie_ep ? "Endpoint" : "Root Complex"); |
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first_free_busno = fsl_pci_init_port(&pci_info[num++], |
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&pcie1_hose, first_free_busno); |
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} else { |
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printf(" PCIE1: disabled\n"); |
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printf("PCIE1: disabled\n"); |
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} |
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#else |
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); |
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@ -136,12 +136,12 @@ void pci_init_board(void) |
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { |
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SET_STD_PCIE_INFO(pci_info[num], 2); |
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); |
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printf(" PCIE2 connected as %s\n", |
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printf("PCIE2: connected as %s\n", |
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pcie_ep ? "Endpoint" : "Root Complex"); |
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first_free_busno = fsl_pci_init_port(&pci_info[num++], |
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&pcie2_hose, first_free_busno); |
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} else { |
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printf(" PCIE2: disabled\n"); |
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printf("PCIE2: disabled\n"); |
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} |
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#else |
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); |
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@ -153,12 +153,12 @@ void pci_init_board(void) |
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if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { |
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SET_STD_PCIE_INFO(pci_info[num], 3); |
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pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); |
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printf(" PCIE3 connected as %s\n", |
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printf("PCIE3: connected as %s\n", |
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pcie_ep ? "Endpoint" : "Root Complex"); |
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first_free_busno = fsl_pci_init_port(&pci_info[num++], |
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&pcie3_hose, first_free_busno); |
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} else { |
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printf(" PCIE3: disabled\n"); |
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printf("PCIE3: disabled\n"); |
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} |
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#else |
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setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); |
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