The Amlogic Meson SoCs embeds a specific Power Domain dedicated to the Video Processing Unit. This patch implements support for this power domain in preparation of the future support for the Video display support in U-Boot. This driver will depend on changes in the clock driver to handle the setup of the VPU and VAPB clocks configured from DT using assigned-clocks entries. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>lime2-spi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic Meson VPU Power Domain Controller driver |
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* |
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* Copyright (c) 2018 BayLibre, SAS. |
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* Author: Neil Armstrong <narmstrong@baylibre.com> |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <power-domain-uclass.h> |
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#include <regmap.h> |
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#include <syscon.h> |
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#include <reset.h> |
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#include <clk.h> |
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/* AO Offsets */ |
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#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) |
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#define GEN_PWR_VPU_HDMI BIT(8) |
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#define GEN_PWR_VPU_HDMI_ISO BIT(9) |
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/* HHI Offsets */ |
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#define HHI_MEM_PD_REG0 (0x40 << 2) |
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#define HHI_VPU_MEM_PD_REG0 (0x41 << 2) |
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#define HHI_VPU_MEM_PD_REG1 (0x42 << 2) |
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struct meson_gx_pwrc_vpu_priv { |
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struct regmap *regmap_ao; |
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struct regmap *regmap_hhi; |
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struct reset_ctl_bulk resets; |
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struct clk_bulk clks; |
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}; |
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static int meson_gx_pwrc_vpu_request(struct power_domain *power_domain) |
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{ |
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return 0; |
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} |
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static int meson_gx_pwrc_vpu_free(struct power_domain *power_domain) |
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{ |
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return 0; |
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} |
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static int meson_gx_pwrc_vpu_on(struct power_domain *power_domain) |
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{ |
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struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev); |
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int i, ret; |
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regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, |
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GEN_PWR_VPU_HDMI, 0); |
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udelay(20); |
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/* Power Up Memories */ |
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for (i = 0; i < 32; i += 2) { |
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regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0, |
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0x3 << i, 0); |
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udelay(5); |
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} |
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for (i = 0; i < 32; i += 2) { |
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regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1, |
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0x3 << i, 0); |
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udelay(5); |
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} |
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for (i = 8; i < 16; i++) { |
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regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0, |
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BIT(i), 0); |
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udelay(5); |
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} |
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udelay(20); |
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ret = reset_assert_bulk(&priv->resets); |
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if (ret) |
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return ret; |
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regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, |
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GEN_PWR_VPU_HDMI_ISO, 0); |
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ret = reset_deassert_bulk(&priv->resets); |
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if (ret) |
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return ret; |
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ret = clk_enable_bulk(&priv->clks); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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static int meson_gx_pwrc_vpu_off(struct power_domain *power_domain) |
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{ |
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struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(power_domain->dev); |
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int i; |
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regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, |
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GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO); |
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udelay(20); |
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/* Power Down Memories */ |
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for (i = 0; i < 32; i += 2) { |
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regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG0, |
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0x3 << i, 0x3 << i); |
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udelay(5); |
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} |
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for (i = 0; i < 32; i += 2) { |
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regmap_update_bits(priv->regmap_hhi, HHI_VPU_MEM_PD_REG1, |
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0x3 << i, 0x3 << i); |
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udelay(5); |
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} |
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for (i = 8; i < 16; i++) { |
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regmap_update_bits(priv->regmap_hhi, HHI_MEM_PD_REG0, |
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BIT(i), BIT(i)); |
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udelay(5); |
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} |
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udelay(20); |
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regmap_update_bits(priv->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, |
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GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI); |
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mdelay(20); |
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clk_disable_bulk(&priv->clks); |
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return 0; |
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} |
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static int meson_gx_pwrc_vpu_of_xlate(struct power_domain *power_domain, |
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struct ofnode_phandle_args *args) |
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{ |
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/* #power-domain-cells is 0 */ |
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if (args->args_count != 0) { |
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debug("Invalid args_count: %d\n", args->args_count); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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struct power_domain_ops meson_gx_pwrc_vpu_ops = { |
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.free = meson_gx_pwrc_vpu_free, |
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.off = meson_gx_pwrc_vpu_off, |
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.on = meson_gx_pwrc_vpu_on, |
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.request = meson_gx_pwrc_vpu_request, |
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.of_xlate = meson_gx_pwrc_vpu_of_xlate, |
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}; |
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static const struct udevice_id meson_gx_pwrc_vpu_ids[] = { |
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{ .compatible = "amlogic,meson-gx-pwrc-vpu" }, |
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{ } |
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}; |
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static int meson_gx_pwrc_vpu_probe(struct udevice *dev) |
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{ |
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struct meson_gx_pwrc_vpu_priv *priv = dev_get_priv(dev); |
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u32 hhi_phandle; |
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ofnode hhi_node; |
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int ret; |
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priv->regmap_ao = syscon_node_to_regmap(dev_get_parent(dev)->node); |
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if (IS_ERR(priv->regmap_ao)) |
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return PTR_ERR(priv->regmap_ao); |
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ret = ofnode_read_u32(dev->node, "amlogic,hhi-sysctrl", |
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&hhi_phandle); |
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if (ret) |
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return ret; |
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hhi_node = ofnode_get_by_phandle(hhi_phandle); |
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if (!ofnode_valid(hhi_node)) |
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return -EINVAL; |
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priv->regmap_hhi = syscon_node_to_regmap(hhi_node); |
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if (IS_ERR(priv->regmap_hhi)) |
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return PTR_ERR(priv->regmap_hhi); |
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ret = reset_get_bulk(dev, &priv->resets); |
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if (ret) |
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return ret; |
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ret = clk_get_bulk(dev, &priv->clks); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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U_BOOT_DRIVER(meson_gx_pwrc_vpu) = { |
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.name = "meson_gx_pwrc_vpu", |
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.id = UCLASS_POWER_DOMAIN, |
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.of_match = meson_gx_pwrc_vpu_ids, |
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.probe = meson_gx_pwrc_vpu_probe, |
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.ops = &meson_gx_pwrc_vpu_ops, |
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.priv_auto_alloc_size = sizeof(struct meson_gx_pwrc_vpu_priv), |
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}; |
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