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@ -98,83 +98,10 @@ Configuration Options: |
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CONFIG_SYS_MAX_NAND_DEVICE |
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The maximum number of NAND devices you want to support. |
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NAND Interface: |
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#define NAND_WAIT_READY(nand) |
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Wait until the NAND flash is ready. Typically this would be a |
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loop waiting for the READY/BUSY line from the flash to indicate it |
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it is ready. |
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#define WRITE_NAND_COMMAND(d, adr) |
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Write the command byte `d' to the flash at `adr' with the |
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CLE (command latch enable) line true. If your board uses writes to |
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different addresses to control CLE and ALE, you can modify `adr' |
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to be the appropriate address here. If your board uses I/O registers |
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to control them, it is probably better to let NAND_CTL_SETCLE() |
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and company do it. |
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#define WRITE_NAND_ADDRESS(d, adr) |
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Write the address byte `d' to the flash at `adr' with the |
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ALE (address latch enable) line true. If your board uses writes to |
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different addresses to control CLE and ALE, you can modify `adr' |
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to be the appropriate address here. If your board uses I/O registers |
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to control them, it is probably better to let NAND_CTL_SETALE() |
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and company do it. |
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#define WRITE_NAND(d, adr) |
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Write the data byte `d' to the flash at `adr' with the |
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ALE and CLE lines false. If your board uses writes to |
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different addresses to control CLE and ALE, you can modify `adr' |
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to be the appropriate address here. If your board uses I/O registers |
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to control them, it is probably better to let NAND_CTL_CLRALE() |
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and company do it. |
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#define READ_NAND(adr) |
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Read a data byte from the flash at `adr' with the |
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ALE and CLE lines false. If your board uses reads from |
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different addresses to control CLE and ALE, you can modify `adr' |
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to be the appropriate address here. If your board uses I/O registers |
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to control them, it is probably better to let NAND_CTL_CLRALE() |
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and company do it. |
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#define NAND_DISABLE_CE(nand) |
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Set CE (Chip Enable) low to enable the NAND flash. |
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#define NAND_ENABLE_CE(nand) |
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Set CE (Chip Enable) high to disable the NAND flash. |
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#define NAND_CTL_CLRALE(nandptr) |
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Set ALE (address latch enable) low. If ALE control is handled by |
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WRITE_NAND_ADDRESS() this can be empty. |
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#define NAND_CTL_SETALE(nandptr) |
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Set ALE (address latch enable) high. If ALE control is handled by |
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WRITE_NAND_ADDRESS() this can be empty. |
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#define NAND_CTL_CLRCLE(nandptr) |
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Set CLE (command latch enable) low. If CLE control is handled by |
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WRITE_NAND_ADDRESS() this can be empty. |
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#define NAND_CTL_SETCLE(nandptr) |
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Set CLE (command latch enable) high. If CLE control is handled by |
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WRITE_NAND_ADDRESS() this can be empty. |
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More Definitions: |
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These definitions are needed in the board configuration for now, but |
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may really belong in a header file. |
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TODO: Figure which ones are truly configuration settings and rename |
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them to CONFIG_SYS_NAND_... and move the rest somewhere appropriate. |
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#define SECTORSIZE 512 |
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#define ADDR_COLUMN 1 |
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#define ADDR_PAGE 2 |
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#define ADDR_COLUMN_PAGE 3 |
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#define NAND_ChipID_UNKNOWN 0x00 |
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#define NAND_MAX_FLOORS 1 |
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#define CONFIG_SYS_NAND_MAX_CHIPS 1 |
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#define CONFIG_SYS_DAVINCI_BROKEN_ECC |
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CONFIG_SYS_NAND_MAX_CHIPS |
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The maximum number of NAND chips per device to be supported. |
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CONFIG_SYS_DAVINCI_BROKEN_ECC |
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Versions of U-Boot <= 1.3.3 and Montavista Linux kernels |
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generated bogus ECCs on large-page NAND. Both large and small page |
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NAND ECCs were incompatible with the Linux davinci git tree (since |
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@ -186,27 +113,17 @@ More Definitions: |
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NOTE: |
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===== |
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We now use a complete rewrite of the NAND code based on what is in |
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2.6.12 Linux kernel. |
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The old NAND handling code has been re-factored and is now confined |
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to only board-specific files and - unfortunately - to the DoC code |
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(see below). A new configuration variable has been introduced: |
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CONFIG_NAND_LEGACY, which has to be defined in the board config file if |
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that board uses legacy code. |
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The necessary changes have been made to all affected boards, and no |
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build breakage has been introduced, except for NETTA and NETTA_ISDN |
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targets from MAKEALL. This is due to the fact that these two boards |
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use JFFS, which has been adopted to use the new NAND, and at the same |
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time use NAND in legacy mode. The breakage will disappear when the |
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board-specific code is changed to the new NAND. |
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The current NAND implementation is based on what is in recent |
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Linux kernels. The old legacy implementation has been disabled, |
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and will be removed soon. |
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As mentioned above, the legacy code is still used by the DoC subsystem. |
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The consequence of this is that the legacy NAND can't be removed from |
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the tree until the DoC is ported to use the new NAND support (or boards |
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with DoC will break). |
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If you have board code which used CONFIG_NAND_LEGACY, you'll need |
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to convert to the current NAND interface for it to continue to work. |
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The Disk On Chip driver is currently broken and has been for some time. |
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There is a driver in drivers/mtd/nand, taken from Linux, that works with |
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the current NAND system but has not yet been adapted to the u-boot |
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environment. |
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Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 |
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