Tom Rini
6 years ago
commit
8e9801c283
@ -0,0 +1,138 @@ |
||||
/* |
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include "imx6sx-sdb.dtsi" |
||||
|
||||
/ { |
||||
model = "Freescale i.MX6 SoloX SDB RevB Board"; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
clock-frequency = <100000>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_i2c1>; |
||||
status = "okay"; |
||||
|
||||
pmic: pfuze100@8 { |
||||
compatible = "fsl,pfuze200"; |
||||
reg = <0x08>; |
||||
|
||||
regulators { |
||||
sw1a_reg: sw1ab { |
||||
regulator-min-microvolt = <300000>; |
||||
regulator-max-microvolt = <1875000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
regulator-ramp-delay = <6250>; |
||||
}; |
||||
|
||||
sw2_reg: sw2 { |
||||
regulator-min-microvolt = <800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
sw3a_reg: sw3a { |
||||
regulator-min-microvolt = <400000>; |
||||
regulator-max-microvolt = <1975000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
sw3b_reg: sw3b { |
||||
regulator-min-microvolt = <400000>; |
||||
regulator-max-microvolt = <1975000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
swbst_reg: swbst { |
||||
regulator-min-microvolt = <5000000>; |
||||
regulator-max-microvolt = <5150000>; |
||||
}; |
||||
|
||||
snvs_reg: vsnvs { |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <3000000>; |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vref_reg: vrefddr { |
||||
regulator-boot-on; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vgen1_reg: vgen1 { |
||||
regulator-min-microvolt = <800000>; |
||||
regulator-max-microvolt = <1550000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vgen2_reg: vgen2 { |
||||
regulator-min-microvolt = <800000>; |
||||
regulator-max-microvolt = <1550000>; |
||||
}; |
||||
|
||||
vgen3_reg: vgen3 { |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vgen4_reg: vgen4 { |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vgen5_reg: vgen5 { |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
vgen6_reg: vgen6 { |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-always-on; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&qspi2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_qspi2>; |
||||
status = "okay"; |
||||
|
||||
flash0: n25q256a@0 { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "micron,n25q256a", "jedec,spi-nor"; |
||||
spi-max-frequency = <29000000>; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
flash1: n25q256a@1 { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "micron,n25q256a", "jedec,spi-nor"; |
||||
spi-max-frequency = <29000000>; |
||||
reg = <1>; |
||||
}; |
||||
}; |
||||
|
||||
®_arm { |
||||
vin-supply = <&sw1a_reg>; |
||||
}; |
||||
|
||||
®_soc { |
||||
vin-supply = <&sw1a_reg>; |
||||
}; |
||||
@ -0,0 +1,612 @@ |
||||
/* |
||||
* Copyright (C) 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include <dt-bindings/input/input.h> |
||||
#include "imx6sx.dtsi" |
||||
|
||||
/ { |
||||
model = "Freescale i.MX6 SoloX SDB Board"; |
||||
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; |
||||
|
||||
chosen { |
||||
stdout-path = &uart1; |
||||
}; |
||||
|
||||
memory { |
||||
reg = <0x80000000 0x40000000>; |
||||
}; |
||||
|
||||
backlight { |
||||
compatible = "pwm-backlight"; |
||||
pwms = <&pwm3 0 5000000>; |
||||
brightness-levels = <0 4 8 16 32 64 128 255>; |
||||
default-brightness-level = <6>; |
||||
}; |
||||
|
||||
gpio-keys { |
||||
compatible = "gpio-keys"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_gpio_keys>; |
||||
|
||||
volume-up { |
||||
label = "Volume Up"; |
||||
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; |
||||
linux,code = <KEY_VOLUMEUP>; |
||||
}; |
||||
|
||||
volume-down { |
||||
label = "Volume Down"; |
||||
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
||||
linux,code = <KEY_VOLUMEDOWN>; |
||||
}; |
||||
}; |
||||
|
||||
regulators { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
vcc_sd3: regulator@0 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <0>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_vcc_sd3>; |
||||
regulator-name = "VCC_SD3"; |
||||
regulator-min-microvolt = <3000000>; |
||||
regulator-max-microvolt = <3000000>; |
||||
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
reg_usb_otg1_vbus: regulator@1 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <1>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usb_otg1>; |
||||
regulator-name = "usb_otg1_vbus"; |
||||
regulator-min-microvolt = <5000000>; |
||||
regulator-max-microvolt = <5000000>; |
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
reg_usb_otg2_vbus: regulator@2 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <2>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usb_otg2>; |
||||
regulator-name = "usb_otg2_vbus"; |
||||
regulator-min-microvolt = <5000000>; |
||||
regulator-max-microvolt = <5000000>; |
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
reg_psu_5v: regulator@3 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <3>; |
||||
regulator-name = "PSU-5V0"; |
||||
regulator-min-microvolt = <5000000>; |
||||
regulator-max-microvolt = <5000000>; |
||||
}; |
||||
|
||||
reg_lcd_3v3: regulator@4 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <4>; |
||||
regulator-name = "lcd-3v3"; |
||||
gpio = <&gpio3 27 0>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
reg_peri_3v3: regulator@5 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <5>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_peri_3v3>; |
||||
regulator-name = "peri_3v3"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
reg_enet_3v3: regulator@6 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <6>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_enet_3v3>; |
||||
regulator-name = "enet_3v3"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; |
||||
}; |
||||
}; |
||||
|
||||
sound { |
||||
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; |
||||
model = "wm8962-audio"; |
||||
ssi-controller = <&ssi2>; |
||||
audio-codec = <&codec>; |
||||
audio-routing = |
||||
"Headphone Jack", "HPOUTL", |
||||
"Headphone Jack", "HPOUTR", |
||||
"Ext Spk", "SPKOUTL", |
||||
"Ext Spk", "SPKOUTR", |
||||
"AMIC", "MICBIAS", |
||||
"IN3R", "AMIC"; |
||||
mux-int-port = <2>; |
||||
mux-ext-port = <6>; |
||||
}; |
||||
}; |
||||
|
||||
&audmux { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_audmux>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fec1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_enet1>; |
||||
phy-supply = <®_enet_3v3>; |
||||
phy-mode = "rgmii"; |
||||
phy-handle = <ðphy1>; |
||||
status = "okay"; |
||||
|
||||
mdio { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
ethphy1: ethernet-phy@1 { |
||||
reg = <1>; |
||||
}; |
||||
|
||||
ethphy2: ethernet-phy@2 { |
||||
reg = <2>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&fec2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_enet2>; |
||||
phy-mode = "rgmii"; |
||||
phy-handle = <ðphy2>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c3 { |
||||
clock-frequency = <100000>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_i2c3>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&i2c4 { |
||||
clock-frequency = <100000>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_i2c4>; |
||||
status = "okay"; |
||||
|
||||
codec: wm8962@1a { |
||||
compatible = "wlf,wm8962"; |
||||
reg = <0x1a>; |
||||
clocks = <&clks IMX6SX_CLK_AUDIO>; |
||||
DCVDD-supply = <&vgen4_reg>; |
||||
DBVDD-supply = <&vgen4_reg>; |
||||
AVDD-supply = <&vgen4_reg>; |
||||
CPVDD-supply = <&vgen4_reg>; |
||||
MICVDD-supply = <&vgen3_reg>; |
||||
PLLVDD-supply = <&vgen4_reg>; |
||||
SPKVDD1-supply = <®_psu_5v>; |
||||
SPKVDD2-supply = <®_psu_5v>; |
||||
}; |
||||
}; |
||||
|
||||
&lcdif1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_lcd>; |
||||
lcd-supply = <®_lcd_3v3>; |
||||
display = <&display0>; |
||||
status = "okay"; |
||||
|
||||
display0: display0 { |
||||
bits-per-pixel = <16>; |
||||
bus-width = <24>; |
||||
|
||||
display-timings { |
||||
native-mode = <&timing0>; |
||||
timing0: timing0 { |
||||
clock-frequency = <33500000>; |
||||
hactive = <800>; |
||||
vactive = <480>; |
||||
hback-porch = <89>; |
||||
hfront-porch = <164>; |
||||
vback-porch = <23>; |
||||
vfront-porch = <10>; |
||||
hsync-len = <10>; |
||||
vsync-len = <10>; |
||||
hsync-active = <0>; |
||||
vsync-active = <0>; |
||||
de-active = <1>; |
||||
pixelclk-active = <0>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pwm3 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_pwm3>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&snvs_poweroff { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&sai1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_sai1>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
&ssi2 { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_uart1>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart5 { /* for bluetooth */ |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_uart5>; |
||||
uart-has-rtscts; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbotg1 { |
||||
vbus-supply = <®_usb_otg1_vbus>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbotg2 { |
||||
vbus-supply = <®_usb_otg2_vbus>; |
||||
dr_mode = "host"; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbphy1 { |
||||
fsl,tx-d-cal = <106>; |
||||
}; |
||||
|
||||
&usbphy2 { |
||||
fsl,tx-d-cal = <106>; |
||||
}; |
||||
|
||||
&usdhc2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usdhc2>; |
||||
non-removable; |
||||
no-1-8-v; |
||||
keep-power-in-suspend; |
||||
wakeup-source; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usdhc3 { |
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
||||
pinctrl-0 = <&pinctrl_usdhc3>; |
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
||||
bus-width = <8>; |
||||
cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; |
||||
keep-power-in-suspend; |
||||
wakeup-source; |
||||
vmmc-supply = <&vcc_sd3>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usdhc4 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usdhc4>; |
||||
cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>; |
||||
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&wdog1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_wdog>; |
||||
fsl,ext-reset-output; |
||||
}; |
||||
|
||||
&iomuxc { |
||||
imx6x-sdb { |
||||
pinctrl_audmux: audmuxgrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 |
||||
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0 |
||||
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0 |
||||
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0 |
||||
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_enet1: enet1grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 |
||||
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 |
||||
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 |
||||
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 |
||||
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 |
||||
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 |
||||
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 |
||||
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 |
||||
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 |
||||
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_enet_3v3: enet3v3grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_enet2: enet2grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 |
||||
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 |
||||
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 |
||||
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 |
||||
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 |
||||
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 |
||||
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 |
||||
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 |
||||
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 |
||||
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 |
||||
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 |
||||
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_gpio_keys: gpio_keysgrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 |
||||
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c1: i2c1grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 |
||||
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c3: i2c3grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 |
||||
MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c4: i2c4grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 |
||||
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_lcd: lcdgrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 |
||||
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_peri_3v3: peri3v3grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_pwm3: pwm3grp-1 { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_qspi2: qspi2grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 |
||||
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1 |
||||
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1 |
||||
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1 |
||||
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1 |
||||
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1 |
||||
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1 |
||||
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1 |
||||
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1 |
||||
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1 |
||||
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1 |
||||
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_vcc_sd3: vccsd3grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_sai1: sai1grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 |
||||
MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 |
||||
MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 |
||||
MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 |
||||
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart1: uart1grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 |
||||
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart5: uart5grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 |
||||
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 |
||||
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 |
||||
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usb_otg1: usbotg1grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usb_otg2: usbot2ggrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc2: usdhc2grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 |
||||
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 |
||||
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 |
||||
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 |
||||
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 |
||||
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc3: usdhc3grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 |
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 |
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 |
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 |
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 |
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 |
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 |
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 |
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 |
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 |
||||
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ |
||||
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 |
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 |
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 |
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 |
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 |
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 |
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 |
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 |
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 |
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 |
||||
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 |
||||
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 |
||||
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 |
||||
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 |
||||
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 |
||||
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 |
||||
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 |
||||
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 |
||||
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc4: usdhc4grp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 |
||||
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 |
||||
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 |
||||
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 |
||||
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 |
||||
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 |
||||
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ |
||||
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_wdog: wdoggrp { |
||||
fsl,pins = < |
||||
MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 |
||||
>; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,11 @@ |
||||
if TARGET_SKSIMX6 |
||||
|
||||
config SYS_BOARD |
||||
default "sksimx6" |
||||
|
||||
config SYS_VENDOR |
||||
default "sks-kinkel" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "sksimx6" |
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
SKS-Kinkel sksimx6 |
||||
M: Stefano Babic <sbabic@denx.de> |
||||
S: Maintained |
||||
F: board/sks-kinkel/sksimx6/ |
||||
F: include/configs/sksimx6.h |
||||
F: configs/sksimx6_defconfig |
||||
@ -0,0 +1,3 @@ |
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
obj-y := sksimx6.o
|
||||
@ -0,0 +1,426 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Stefano Babic <sbabic@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <linux/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/mach-imx/iomux-v3.h> |
||||
#include <asm/mach-imx/video.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <spl.h> |
||||
#include <netdev.h> |
||||
#include <miiphy.h> |
||||
#include <micrel.h> |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <fuse.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
||||
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
||||
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = { |
||||
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const gpios_pads[] = { |
||||
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const usdhc2_pads[] = { |
||||
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ |
||||
}; |
||||
|
||||
static iomux_v3_cfg_t const enet_pads[] = { |
||||
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | |
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | |
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | |
||||
MUX_PAD_CTRL(ENET_PAD_CTRL)), |
||||
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
}; |
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = { |
||||
/* pin 35 - 1 (PHY_AD2) on reset */ |
||||
IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 32 - 1 - (MODE0) all */ |
||||
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 31 - 1 - (MODE1) all */ |
||||
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 28 - 1 - (MODE2) all */ |
||||
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 27 - 1 - (MODE3) all */ |
||||
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ |
||||
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
/* pin 42 PHY nRST */ |
||||
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
||||
}; |
||||
|
||||
static int mx6_rgmii_rework(struct phy_device *phydev) |
||||
{ |
||||
|
||||
/* min rx data delay */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, |
||||
0x0); |
||||
/* min tx data delay */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, |
||||
0x0); |
||||
/* max rx/tx clock delay, min rx/tx control */ |
||||
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, |
||||
0xf0f0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
mx6_rgmii_rework(phydev); |
||||
|
||||
if (phydev->drv->config) |
||||
return phydev->drv->config(phydev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define ENET_NRST IMX_GPIO_NR(1, 25) |
||||
|
||||
void setup_iomux_enet(void) |
||||
{ |
||||
SETUP_IOMUX_PADS(enet_pads); |
||||
|
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
uint32_t base = IMX_FEC_BASE; |
||||
struct mii_dev *bus = NULL; |
||||
struct phy_device *phydev = NULL; |
||||
int ret; |
||||
|
||||
setup_iomux_enet(); |
||||
|
||||
bus = fec_get_miibus(base, -1); |
||||
if (!bus) |
||||
return -EINVAL; |
||||
/* scan phy */ |
||||
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), |
||||
PHY_INTERFACE_MODE_RGMII); |
||||
|
||||
if (!phydev) { |
||||
ret = -EINVAL; |
||||
goto free_bus; |
||||
} |
||||
ret = fec_probe(bis, -1, base, bus, phydev); |
||||
if (ret) |
||||
goto free_phydev; |
||||
|
||||
return 0; |
||||
|
||||
free_phydev: |
||||
free(phydev); |
||||
free_bus: |
||||
free(bus); |
||||
return ret; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
SETUP_IOMUX_PADS(uart1_pads); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
/* Take in reset the ATMega processor */ |
||||
SETUP_IOMUX_PADS(gpios_pads); |
||||
gpio_direction_output(IMX_GPIO_NR(5, 4), 0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = imx_ddr_size(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
struct fsl_esdhc_cfg usdhc_cfg[1] = { |
||||
{USDHC2_BASE_ADDR, 0}, |
||||
}; |
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0) |
||||
int board_mmc_getcd(struct mmc *mmc) |
||||
{ |
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
||||
int ret = 0; |
||||
|
||||
if (cfg->esdhc_base == USDHC2_BASE_ADDR) |
||||
ret = 1; |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret; |
||||
|
||||
SETUP_IOMUX_PADS(usdhc2_pads); |
||||
gpio_direction_input(USDHC2_CD_GPIO); |
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
||||
usdhc_cfg[0].max_bus_width = 4; |
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
||||
if (ret) { |
||||
printf("Warning: failed to initialize mmc dev \n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) |
||||
#include <asm/arch/mx6-ddr.h> |
||||
|
||||
/*
|
||||
* Driving strength: |
||||
* 0x30 == 40 Ohm |
||||
* 0x28 == 48 Ohm |
||||
*/ |
||||
#define IMX6SDL_DRIVE_STRENGTH 0x230 |
||||
|
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ |
||||
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { |
||||
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_cas = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_ras = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_reset = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdba2 = 0x00000000, |
||||
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH, |
||||
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ |
||||
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { |
||||
.grp_ddr_type = 0x000c0000, |
||||
.grp_ddrmode_ctl = 0x00020000, |
||||
.grp_ddrpke = 0x00000000, |
||||
.grp_addds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_ddrmode = 0x00020000, |
||||
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH, |
||||
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH, |
||||
}; |
||||
|
||||
/* MT41K128M16JT-125 */ |
||||
static struct mx6_ddr3_cfg mt41k128m16jt_125 = { |
||||
/* quad = 1066, duallite = 800 */ |
||||
.mem_speed = 1066, |
||||
.density = 2, |
||||
.width = 16, |
||||
.banks = 8, |
||||
.rowaddr = 14, |
||||
.coladdr = 10, |
||||
.pagesz = 2, |
||||
.trcd = 1375, |
||||
.trcmin = 4875, |
||||
.trasmin = 3500, |
||||
.SRT = 0, |
||||
}; |
||||
|
||||
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { |
||||
.p0_mpwldectrl0 = 0x0043004E, |
||||
.p0_mpwldectrl1 = 0x003D003F, |
||||
.p1_mpwldectrl0 = 0x00230021, |
||||
.p1_mpwldectrl1 = 0x0028003E, |
||||
.p0_mpdgctrl0 = 0x42580250, |
||||
.p0_mpdgctrl1 = 0x0238023C, |
||||
.p1_mpdgctrl0 = 0x422C0238, |
||||
.p1_mpdgctrl1 = 0x02180228, |
||||
.p0_mprddlctl = 0x44464A46, |
||||
.p1_mprddlctl = 0x44464A42, |
||||
.p0_mpwrdlctl = 0x36343236, |
||||
.p1_mpwrdlctl = 0x36343230, |
||||
}; |
||||
|
||||
/* DDR 64bit 1GB */ |
||||
static struct mx6_ddr_sysinfo mem_qdl = { |
||||
.dsize = 2, |
||||
.cs1_mirror = 0, |
||||
/* config for full 4GB range so that get_mem_size() works */ |
||||
.cs_density = 32, |
||||
.ncs = 1, |
||||
.bi_on = 1, |
||||
.rtt_nom = 1, |
||||
.rtt_wr = 1, |
||||
.ralat = 5, |
||||
.walat = 0, |
||||
.mif3_mode = 3, |
||||
.rst_to_cke = 0x23, |
||||
.sde_to_rst = 0x10, |
||||
.refsel = 1, /* Refresh cycles at 32KHz */ |
||||
.refr = 7, /* 8 refresh commands per refresh cycle */ |
||||
}; |
||||
|
||||
static void ccgr_init(void) |
||||
{ |
||||
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
||||
|
||||
/* set the default clock gate to save power */ |
||||
writel(0x00C03F3F, &ccm->CCGR0); |
||||
writel(0x0030FC03, &ccm->CCGR1); |
||||
writel(0x0FFFC000, &ccm->CCGR2); |
||||
writel(0x3FF00000, &ccm->CCGR3); |
||||
writel(0x00FFF300, &ccm->CCGR4); |
||||
writel(0xFFFFFFFF, &ccm->CCGR5); |
||||
writel(0x000003FF, &ccm->CCGR6); |
||||
} |
||||
|
||||
static void spl_dram_init(void) |
||||
{ |
||||
if (is_cpu_type(MXC_CPU_MX6DL)) { |
||||
mt41k128m16jt_125.mem_speed = 800; |
||||
mem_qdl.rtt_nom = 1; |
||||
mem_qdl.rtt_wr = 1; |
||||
|
||||
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); |
||||
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125); |
||||
} else { |
||||
printf("Wrong CPU for this board\n"); |
||||
return; |
||||
} |
||||
|
||||
udelay(100); |
||||
|
||||
#ifdef CONFIG_MX6_DDRCAL |
||||
|
||||
/* Perform DDR DRAM calibration */ |
||||
mmdc_do_write_level_calibration(&mem_qdl); |
||||
mmdc_do_dqs_calibration(&mem_qdl); |
||||
#endif |
||||
} |
||||
|
||||
static void check_bootcfg(void) |
||||
{ |
||||
u32 val5, val6; |
||||
|
||||
fuse_sense(0, 5, &val5); |
||||
fuse_sense(0, 6, &val6); |
||||
/* Check if boot from MMC */ |
||||
if (val6 & 0x10) { |
||||
puts("BT_FUSE_SEL already fused, will do nothing\n"); |
||||
return; |
||||
} |
||||
fuse_prog(0, 5, 0x00000840); |
||||
/* BT_FUSE_SEL */ |
||||
fuse_prog(0, 6, 0x00000010); |
||||
|
||||
do_reset(NULL, 0, 0, NULL); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
ccgr_init(); |
||||
|
||||
/* setup AIPS and disable watchdog */ |
||||
arch_cpu_init(); |
||||
|
||||
gpr_init(); |
||||
|
||||
/* iomux */ |
||||
board_early_init_f(); |
||||
|
||||
/* setup GP timer */ |
||||
timer_init(); |
||||
|
||||
/* UART clocks enabled and gd valid - init serial console */ |
||||
preloader_console_init(); |
||||
|
||||
/* DDR initialization */ |
||||
spl_dram_init(); |
||||
|
||||
/* Set fuses for new boards and reboot if not set */ |
||||
check_bootcfg(); |
||||
|
||||
/* Clear the BSS. */ |
||||
memset(__bss_start, 0, __bss_end - __bss_start); |
||||
|
||||
/* load/boot image from boot device */ |
||||
board_init_r(NULL, 0); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,47 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_SPL_GPIO_SUPPORT=y |
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y |
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y |
||||
CONFIG_MX6_DDRCAL=y |
||||
CONFIG_TARGET_SKSIMX6=y |
||||
CONFIG_SPL_MMC_SUPPORT=y |
||||
CONFIG_SPL_SERIAL_SUPPORT=y |
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y |
||||
CONFIG_SPL_LIBDISK_SUPPORT=y |
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y |
||||
CONFIG_FIT=y |
||||
CONFIG_FIT_VERBOSE=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL" |
||||
CONFIG_BOOTDELAY=1 |
||||
CONFIG_SILENT_CONSOLE=y |
||||
CONFIG_SILENT_U_BOOT_ONLY=y |
||||
CONFIG_VERSION_VARIABLE=y |
||||
CONFIG_BOARD_EARLY_INIT_F=y |
||||
CONFIG_SPL=y |
||||
CONFIG_SPL_EXT_SUPPORT=y |
||||
CONFIG_SPL_I2C_SUPPORT=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
CONFIG_DM=y |
||||
CONFIG_PHYLIB=y |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_PHY_MICREL_KSZ90X1=y |
||||
CONFIG_PHY_MICREL_KSZ8XXX=y |
||||
CONFIG_NETDEVICES=y |
||||
CONFIG_FEC_MXC=y |
||||
CONFIG_DM_THERMAL=y |
||||
CONFIG_OF_LIBFDT=y |
||||
@ -0,0 +1,101 @@ |
||||
/*
|
||||
* Copyright (C) Stefano Babic <sbabic@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
|
||||
#ifndef __SKSIMX6_CONFIG_H |
||||
#define __SKSIMX6_CONFIG_H |
||||
|
||||
#include <config_distro_defaults.h> |
||||
|
||||
#include "mx6_common.h" |
||||
#include "imx6_spl.h" |
||||
|
||||
/* Thermal */ |
||||
#define CONFIG_IMX_THERMAL |
||||
|
||||
/* Serial */ |
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) |
||||
|
||||
/* Ethernet */ |
||||
#define IMX_FEC_BASE ENET_BASE_ADDR |
||||
#define CONFIG_FEC_XCV_TYPE RGMII |
||||
#define CONFIG_ETHPRIME "FEC" |
||||
#define CONFIG_FEC_MXC_PHYADDR 0x01 |
||||
|
||||
#define CONFIG_MII |
||||
#define CONFIG_PHY_MICREL_KSZ9021 |
||||
|
||||
/* I2C Configs */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
|
||||
/* Filesystem support */ |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* MMC Configs */ |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
|
||||
/* Environment organization */ |
||||
#define CONFIG_ENV_SIZE (16 * 1024) |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
||||
CONFIG_ENV_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/* Default environment */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"addcons=setenv bootargs ${bootargs} " \
|
||||
"console=${console},${baudrate}\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
|
||||
"${netmask}:${hostname}:${netdev}:off\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \
|
||||
"bootcmd=run mmcboot\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"bootimage=uImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_addr_r=0x18000000\0" \
|
||||
"fdt_file=imx6dl-sks-cts.dtb\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
"miscargs=quiet\0" \
|
||||
"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \
|
||||
"mmcboot=if run mmcload;then " \
|
||||
"run mmcargs addcons addmisc;" \
|
||||
"bootm;fi\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p1\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \
|
||||
"run nfsargs addip addcons addmisc;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${nfsroot},v3 panic=1\0" |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue