spi: cadence_qspi: get sram size from device tree

sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
master
Vikas Manocha 9 years ago committed by Jagan Teki
parent c0535c0ef0
commit 90a2f71711
  1. 1
      arch/arm/dts/socfpga.dtsi
  2. 1
      arch/arm/dts/stv0991.dts
  3. 1
      drivers/spi/cadence_qspi.c
  4. 1
      drivers/spi/cadence_qspi.h
  5. 6
      drivers/spi/cadence_qspi_apb.c

@ -639,6 +639,7 @@
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
fifo-depth = <128>;
sram-size = <128>;
bus-num = <2>;
status = "disabled";
};

@ -35,6 +35,7 @@
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
fifo-depth = <256>;
sram-size = <256>;
bus-num = <0>;
status = "okay";

@ -309,6 +309,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,

@ -25,6 +25,7 @@ struct cadence_spi_platdata {
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
u32 sram_size;
};
struct cadence_spi_priv {

@ -36,9 +36,6 @@
#define CQSPI_FIFO_WIDTH (4)
/* Controller sram size in word */
#define CQSPI_REG_SRAM_SIZE_WORD (128)
#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
@ -536,8 +533,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
writel(0, plat->regbase + CQSPI_REG_REMAP);
/* Indirect mode configurations */
writel(CQSPI_REG_SRAM_PARTITION_RD,
plat->regbase + CQSPI_REG_SRAMPARTITION);
writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);

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