Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

drivers: remove Blackfin specific drivers

Browse Source 
These drivers have no user since commit ea3310e8aa ("Blackfin:
Remove").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
master
Masahiro Yamada 7 years ago committed by Tom Rini
parent 4326b45474
commit 90d6500c0f
14 changed files with 0 additions and 2817 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 1
      drivers/block/Makefile
  2. 1209
      drivers/block/pata_bfin.c
  3. 170
      drivers/block/pata_bfin.h
  4. 1
      drivers/mmc/Makefile
  5. 306
      drivers/mmc/bfin_sdh.c
  6. 1
      drivers/mtd/nand/Makefile
  7. 394
      drivers/mtd/nand/bfin_nand.c
  8. 1
      drivers/net/Makefile
  9. 519
      drivers/net/bfin_mac.c
  10. 65
      drivers/net/bfin_mac.h
  11. 1
      drivers/rtc/Makefile
  12. 121
      drivers/rtc/bfin_rtc.c
  13. 1
      drivers/watchdog/Makefile
  14. 27
      drivers/watchdog/bfin_wdt.c

1
drivers/block/Makefile
Unescape View File

@ -20,7 +20,6 @@ obj-$(CONFIG_IDE_FTIDE020) += ftide020.o
obj-$(CONFIG_LIBATA) += libata.o
obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
obj-$(CONFIG_MX51_PATA) += mxc_ata.o
obj-$(CONFIG_PATA_BFIN) += pata_bfin.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_DWC) += sata_dwc.o
obj-$(CONFIG_SATA_MV) += sata_mv.o

1209
drivers/block/pata_bfin.c
View File

File diff suppressed because it is too large Load Diff

170
drivers/block/pata_bfin.h
Unescape View File

@ -1,170 +0,0 @@
/*
* Driver for Blackfin on-chip ATAPI controller.
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (c) 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef PATA_BFIN_H
#define PATA_BFIN_H
#include <asm/blackfin_local.h>
struct ata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct ata_port {
unsigned int port_no; /* primary=0, secondary=1 */
struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned long flag;
unsigned int ata_mode;
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char dev_mask;
};
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
#define ATA_REG_CTRL 0x0E
#define ATA_REG_ALTSTATUS ATA_REG_CTRL
#define ATA_TMOUT_BOOT 30000
#define ATA_TMOUT_BOOT_QUICK 7000
#define PATA_BFIN_WAIT_TIMEOUT 10000
#define PATA_DEV_NUM_PER_PORT 2
/* These are the offset of the controller's registers */
#define ATAPI_OFFSET_CONTROL 0x00
#define ATAPI_OFFSET_STATUS 0x04
#define ATAPI_OFFSET_DEV_ADDR 0x08
#define ATAPI_OFFSET_DEV_TXBUF 0x0c
#define ATAPI_OFFSET_DEV_RXBUF 0x10
#define ATAPI_OFFSET_INT_MASK 0x14
#define ATAPI_OFFSET_INT_STATUS 0x18
#define ATAPI_OFFSET_XFER_LEN 0x1c
#define ATAPI_OFFSET_LINE_STATUS 0x20
#define ATAPI_OFFSET_SM_STATE 0x24
#define ATAPI_OFFSET_TERMINATE 0x28
#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
#define ATAPI_OFFSET_DMA_TFRCNT 0x30
#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
#define ATAPI_OFFSET_REG_TIM_0 0x40
#define ATAPI_OFFSET_PIO_TIM_0 0x44
#define ATAPI_OFFSET_PIO_TIM_1 0x48
#define ATAPI_OFFSET_MULTI_TIM_0 0x50
#define ATAPI_OFFSET_MULTI_TIM_1 0x54
#define ATAPI_OFFSET_MULTI_TIM_2 0x58
#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
#define ATAPI_GET_CONTROL(base)\
bfin_read16(base + ATAPI_OFFSET_CONTROL)
#define ATAPI_SET_CONTROL(base, val)\
bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
#define ATAPI_GET_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_STATUS)
#define ATAPI_GET_DEV_ADDR(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
#define ATAPI_SET_DEV_ADDR(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
#define ATAPI_GET_DEV_TXBUF(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
#define ATAPI_SET_DEV_TXBUF(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
#define ATAPI_GET_DEV_RXBUF(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
#define ATAPI_SET_DEV_RXBUF(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
#define ATAPI_GET_INT_MASK(base)\
bfin_read16(base + ATAPI_OFFSET_INT_MASK)
#define ATAPI_SET_INT_MASK(base, val)\
bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
#define ATAPI_GET_INT_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
#define ATAPI_SET_INT_STATUS(base, val)\
bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
#define ATAPI_GET_XFER_LEN(base)\
bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
#define ATAPI_SET_XFER_LEN(base, val)\
bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
#define ATAPI_GET_LINE_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
#define ATAPI_GET_SM_STATE(base)\
bfin_read16(base + ATAPI_OFFSET_SM_STATE)
#define ATAPI_GET_TERMINATE(base)\
bfin_read16(base + ATAPI_OFFSET_TERMINATE)
#define ATAPI_SET_TERMINATE(base, val)\
bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
#define ATAPI_GET_PIO_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
#define ATAPI_GET_DMA_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
#define ATAPI_GET_UMAIN_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
#define ATAPI_GET_REG_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
#define ATAPI_SET_REG_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
#define ATAPI_GET_PIO_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
#define ATAPI_SET_PIO_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
#define ATAPI_GET_PIO_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
#define ATAPI_SET_PIO_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
#define ATAPI_SET_MULTI_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
#define ATAPI_GET_MULTI_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
#define ATAPI_SET_MULTI_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_2(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
#define ATAPI_SET_MULTI_TIM_2(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
#define ATAPI_SET_ULTRA_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
#define ATAPI_GET_ULTRA_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
#define ATAPI_SET_ULTRA_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
#define ATAPI_GET_ULTRA_TIM_2(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
#define ATAPI_SET_ULTRA_TIM_2(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_3(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
#define ATAPI_SET_ULTRA_TIM_3(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
#endif

1
drivers/mmc/Makefile
Unescape View File

@ -14,7 +14,6 @@ obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o
endif
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
obj-$(CONFIG_MMC_DW) += dw_mmc.o

306
drivers/mmc/bfin_sdh.c
Unescape View File

@ -1,306 +0,0 @@
/*
* Driver for Blackfin on-chip SDH controller
*
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
# if defined(__ADSPBF60x__)
# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
# else
# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
# endif
# define PORTMUX_PINS \
{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
# define PORTMUX_PINS \
{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif
static int
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
unsigned int status, timeout;
int cmd = mmc_cmd->cmdidx;
int flags = mmc_cmd->resp_type;
int arg = mmc_cmd->cmdarg;
int ret;
u16 sdh_cmd;
sdh_cmd = cmd | CMD_E;
if (flags & MMC_RSP_PRESENT)
sdh_cmd |= CMD_RSP;
if (flags & MMC_RSP_136)
sdh_cmd |= CMD_L_RSP;
#ifdef RSI_BLKSZ
sdh_cmd |= CMD_DATA0_BUSY;
#endif
bfin_write_SDH_ARGUMENT(arg);
bfin_write_SDH_COMMAND(sdh_cmd);
/* wait for a while */
timeout = 0;
do {
if (++timeout > 1000000) {
status = CMD_TIME_OUT;
break;
}
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
CMD_CRC_FAIL)));
if (flags & MMC_RSP_PRESENT) {
mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
if (flags & MMC_RSP_136) {
mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
}
}
if (status & CMD_TIME_OUT)
ret = -ETIMEDOUT;
else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
ret = -ECOMM;
else
ret = 0;
bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
#ifdef RSI_BLKSZ
/* wait till card ready */
while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
continue;
bfin_write_RSI_ESTAT(SD_CARD_READY);
#endif
return ret;
}
/* set data for single block transfer */
static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
{
u16 data_ctl = 0;
u16 dma_cfg = 0;
unsigned long data_size = data->blocksize * data->blocks;
/* Don't support write yet. */
if (data->flags & MMC_DATA_WRITE)
return -EOPNOTSUPP;
#ifndef RSI_BLKSZ
data_ctl |= ((ffs(data->blocksize) - 1) << 4);
#else
bfin_write_SDH_BLK_SIZE(data->blocksize);
#endif
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
bfin_write_SDH_DATA_TIMER(-1);
blackfin_dcache_flush_invalidate_range(data->dest,
data->dest + data_size);
/* configure DMA */
bfin_write_DMA_START_ADDR(data->dest);
bfin_write_DMA_X_COUNT(data_size / 4);
bfin_write_DMA_X_MODIFY(4);
bfin_write_DMA_CONFIG(dma_cfg);
bfin_write_SDH_DATA_LGTH(data_size);
/* kick off transfer */
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
return 0;
}
static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
u32 status;
int ret = 0;
if (data) {
ret = sdh_setup_data(mmc, data);
if (ret)
return ret;
}
ret = sdh_send_cmd(mmc, cmd);
if (ret) {
bfin_write_SDH_COMMAND(0);
bfin_write_DMA_CONFIG(0);
bfin_write_SDH_DATA_CTL(0);
SSYNC();
printf("sending CMD%d failed\n", cmd->cmdidx);
return ret;
}
if (data) {
do {
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
RX_OVERRUN)));
if (status & DAT_TIME_OUT) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
ret = -ETIMEDOUT;
} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
ret = -ECOMM;
} else
bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
if (ret) {
printf("tranfering data failed\n");
return ret;
}
}
return 0;
}
static void sdh_set_clk(unsigned long clk)
{
unsigned long sys_clk;
unsigned long clk_div;
u16 clk_ctl = 0;
clk_ctl = bfin_read_SDH_CLK_CTL();
if (clk) {
/* setting SD_CLK */
sys_clk = get_sclk();
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
if (sys_clk % (2 * clk) == 0)
clk_div = sys_clk / (2 * clk) - 1;
else
clk_div = sys_clk / (2 * clk);
if (clk_div > 0xff)
clk_div = 0xff;
clk_ctl |= (clk_div & 0xff);
clk_ctl |= CLK_E;
bfin_write_SDH_CLK_CTL(clk_ctl);
} else
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}
static int bfin_sdh_set_ios(struct mmc *mmc)
{
u16 cfg = 0;
u16 clk_ctl = 0;
if (mmc->bus_width == 4) {
cfg = bfin_read_SDH_CFG();
#ifndef RSI_BLKSZ
cfg &= ~PD_SDDAT3;
#endif
cfg |= PUP_SDDAT3;
bfin_write_SDH_CFG(cfg);
clk_ctl |= WIDE_BUS_4;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
sdh_set_clk(mmc->clock);
return 0;
}
static int bfin_sdh_init(struct mmc *mmc)
{
const unsigned short pins[] = PORTMUX_PINS;
int ret;
/* Initialize sdh controller */
ret = peripheral_request_list(pins, "bfin_sdh");
if (ret < 0)
return ret;
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
#ifndef RSI_BLKSZ
bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
#else
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
#endif
return 0;
}
static const struct mmc_ops bfin_mmc_ops = {
.send_cmd = bfin_sdh_request,
.set_ios = bfin_sdh_set_ios,
.init = bfin_sdh_init,
};
static struct mmc_config bfin_mmc_cfg = {
.name = "Blackfin SDH",
.ops = &bfin_mmc_ops,
.host_caps = MMC_MODE_4BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
int bfin_mmc_init(bd_t *bis)
{
struct mmc *mmc;
bfin_mmc_cfg.f_max = get_sclk();
bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
mmc = mmc_create(&bfin_mmc_cfg, NULL);
if (mmc == NULL)
return -1;
return 0;
}

1
drivers/mtd/nand/Makefile
Unescape View File

@ -42,7 +42,6 @@ obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
obj-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
obj-$(CONFIG_NAND_DENALI) += denali.o
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o

394
drivers/mtd/nand/bfin_nand.c
Unescape View File

@ -1,394 +0,0 @@
/*
* Driver for Blackfin on-chip NAND controller.
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (c) 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
/* TODO:
* - move bit defines into mach-common/bits/nand.h
* - try and replace all IRQSTAT usage with STAT polling
* - have software ecc mode use same algo as hw ecc ?
*/
#include <common.h>
#include <console.h>
#include <asm/io.h>
#ifdef DEBUG
# define pr_stamp() printf("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
#else
# define pr_stamp()
#endif
#include <nand.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
#define RD_DLY 0xf0 /* Read Strobe Delay */
#define NWIDTH 0x100 /* NAND Data Width */
#define PG_SIZE 0x200 /* Page Size */
/* Bit masks for NFC_STAT */
#define NBUSY 0x1 /* Not Busy */
#define WB_FULL 0x2 /* Write Buffer Full */
#define PG_WR_STAT 0x4 /* Page Write Pending */
#define PG_RD_STAT 0x8 /* Page Read Pending */
#define WB_EMPTY 0x10 /* Write Buffer Empty */
/* Bit masks for NFC_IRQSTAT */
#define NBUSYIRQ 0x1 /* Not Busy IRQ */
#define WB_OVF 0x2 /* Write Buffer Overflow */
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
#define RD_RDY 0x8 /* Read Data Ready */
#define WR_DONE 0x10 /* Page Write Done */
#define NAND_IS_512() (CONFIG_BFIN_NFC_CTL_VAL & 0x200)
/*
* hardware specific access to control-lines
*/
static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
pr_stamp();
if (cmd == NAND_CMD_NONE)
return;
while (bfin_read_NFC_STAT() & WB_FULL)
continue;
if (ctrl & NAND_CLE)
bfin_write_NFC_CMD(cmd);
else
bfin_write_NFC_ADDR(cmd);
SSYNC();
}
static int bfin_nfc_devready(struct mtd_info *mtd)
{
pr_stamp();
return (bfin_read_NFC_STAT() & NBUSY) ? 1 : 0;
}
/*
* PIO mode for buffer writing and reading
*/
static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
pr_stamp();
int i;
/*
* Data reads are requested by first writing to NFC_DATA_RD
* and then reading back from NFC_READ.
*/
for (i = 0; i < len; ++i) {
while (bfin_read_NFC_STAT() & WB_FULL)
if (ctrlc())
return;
/* Contents do not matter */
bfin_write_NFC_DATA_RD(0x0000);
SSYNC();
while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
if (ctrlc())
return;
buf[i] = bfin_read_NFC_READ();
bfin_write_NFC_IRQSTAT(RD_RDY);
}
}
static uint8_t bfin_nfc_read_byte(struct mtd_info *mtd)
{
pr_stamp();
uint8_t val;
bfin_nfc_read_buf(mtd, &val, 1);
return val;
}
static void bfin_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
{
pr_stamp();
int i;
for (i = 0; i < len; ++i) {
while (bfin_read_NFC_STAT() & WB_FULL)
if (ctrlc())
return;
bfin_write_NFC_DATA_WR(buf[i]);
}
/* Wait for the buffer to drain before we return */
while (!(bfin_read_NFC_STAT() & WB_EMPTY))
if (ctrlc())
return;
}
/*
* ECC functions
* These allow the bfin to use the controller's ECC
* generator block to ECC the data as it passes through
*/
/*
* ECC error correction function
*/
static int bfin_nfc_correct_data_256(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
u32 syndrome[5];
u32 calced, stored;
unsigned short failing_bit, failing_byte;
u_char data;
pr_stamp();
calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
syndrome[0] = (calced ^ stored);
/*
* syndrome 0: all zero
* No error in data
* No action
*/
if (!syndrome[0] || !calced || !stored)
return 0;
/*
* sysdrome 0: only one bit is one
* ECC data was incorrect
* No action
*/
if (hweight32(syndrome[0]) == 1)
return 1;
syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
syndrome[4] = syndrome[2] ^ syndrome[3];
/*
* sysdrome 0: exactly 11 bits are one, each parity
* and parity' pair is 1 & 0 or 0 & 1.
* 1-bit correctable error
* Correct the error
*/
if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
failing_bit = syndrome[1] & 0x7;
failing_byte = syndrome[1] >> 0x3;
data = *(dat + failing_byte);
data = data ^ (0x1 << failing_bit);
*(dat + failing_byte) = data;
return 0;
}
/*
* sysdrome 0: random data
* More than 1-bit error, non-correctable error
* Discard data, mark bad block
*/
return 1;
}
static int bfin_nfc_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
int ret;
pr_stamp();
ret = bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
/* If page size is 512, correct second 256 bytes */
if (NAND_IS_512()) {
dat += 256;
read_ecc += 8;
calc_ecc += 8;
ret |= bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
}
return ret;
}
static void reset_ecc(void)
{
bfin_write_NFC_RST(0x1);
while (bfin_read_NFC_RST() & 1)
continue;
}
static void bfin_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
{
reset_ecc();
}
static int bfin_nfc_calculate_ecc(struct mtd_info *mtd,
const u_char *dat, u_char *ecc_code)
{
u16 ecc0, ecc1;
u32 code[2];
u8 *p;
pr_stamp();
/* first 4 bytes ECC code for 256 page size */
ecc0 = bfin_read_NFC_ECC0();
ecc1 = bfin_read_NFC_ECC1();
code[0] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
/* first 3 bytes in ecc_code for 256 page size */
p = (u8 *) code;
memcpy(ecc_code, p, 3);
/* second 4 bytes ECC code for 512 page size */
if (NAND_IS_512()) {
ecc0 = bfin_read_NFC_ECC2();
ecc1 = bfin_read_NFC_ECC3();
code[1] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
/* second 3 bytes in ecc_code for second 256
* bytes of 512 page size
*/
p = (u8 *) (code + 1);
memcpy((ecc_code + 3), p, 3);
}
reset_ecc();
return 0;
}
#ifdef CONFIG_BFIN_NFC_BOOTROM_ECC
# define BOOTROM_ECC 1
#else
# define BOOTROM_ECC 0
#endif
static uint8_t bbt_pattern[] = { 0xff };
static struct nand_bbt_descr bootrom_bbt = {
.options = 0,
.offs = 63,
.len = 1,
.pattern = bbt_pattern,
};
static struct nand_ecclayout bootrom_ecclayout = {
.eccbytes = 24,
.eccpos = {
0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
},
.oobfree = {
{ 0x8 * 0 + 3, 5 },
{ 0x8 * 1 + 3, 5 },
{ 0x8 * 2 + 3, 5 },
{ 0x8 * 3 + 3, 5 },
{ 0x8 * 4 + 3, 5 },
{ 0x8 * 5 + 3, 5 },
{ 0x8 * 6 + 3, 5 },
{ 0x8 * 7 + 3, 5 },
}
};
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand.h):
* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
* - cmd_ctrl: hardwarespecific function for accesing control-lines
* - dev_ready: hardwarespecific function for accesing device ready/busy line
* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
* only be provided if a hardware ECC is available
* - ecc.mode: mode of ecc, see defines
* - chip_delay: chip dependent delay for transfering data from array to
* read regs (tR)
* - options: various chip options. They can partly be set to inform
* nand_scan about special functionality. See the defines for further
* explanation
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
int board_nand_init(struct nand_chip *chip)
{
const unsigned short pins[] = {
P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
};
pr_stamp();
/* set width/ecc/timings/etc... */
bfin_write_NFC_CTL(CONFIG_BFIN_NFC_CTL_VAL);
/* clear interrupt status */
bfin_write_NFC_IRQMASK(0x0);
bfin_write_NFC_IRQSTAT(0xffff);
/* enable GPIO function enable register */
peripheral_request_list(pins, "bfin_nand");
chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
chip->read_buf = bfin_nfc_read_buf;
chip->write_buf = bfin_nfc_write_buf;
chip->read_byte = bfin_nfc_read_byte;
#ifdef CONFIG_BFIN_NFC_NO_HW_ECC
# define ECC_HW 0
#else
# define ECC_HW 1
#endif
if (ECC_HW) {
if (BOOTROM_ECC) {
chip->badblock_pattern = &bootrom_bbt;
chip->ecc.layout = &bootrom_ecclayout;
}
if (!NAND_IS_512()) {
chip->ecc.bytes = 3;
chip->ecc.size = 256;
chip->ecc.strength = 1;
} else {
chip->ecc.bytes = 6;
chip->ecc.size = 512;
chip->ecc.strength = 2;
}
chip->ecc.mode = NAND_ECC_HW;
chip->ecc.calculate = bfin_nfc_calculate_ecc;
chip->ecc.correct = bfin_nfc_correct_data;
chip->ecc.hwctl = bfin_nfc_enable_hwecc;
} else
chip->ecc.mode = NAND_ECC_SOFT;
chip->dev_ready = bfin_nfc_devready;
chip->chip_delay = 0;
return 0;
}

1
drivers/net/Makefile
Unescape View File

@ -13,7 +13,6 @@ obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_BFIN_MAC) += bfin_mac.o
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o

519
drivers/net/bfin_mac.c
Unescape View File

@ -1,519 +0,0 @@
/*
* Driver for Blackfin On-Chip MAC device
*
* Copyright (c) 2005-2008 Analog Device, Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mdio.h>
#include <linux/mii.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
#include "bfin_mac.h"
#ifndef CONFIG_PHY_ADDR
# define CONFIG_PHY_ADDR 1
#endif
#ifndef CONFIG_PHY_CLOCK_FREQ
# define CONFIG_PHY_CLOCK_FREQ 2500000
#endif
#ifdef CONFIG_POST
#include <post.h>
#endif
#define RXBUF_BASE_ADDR 0xFF900000
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx; /* index of the current RX buffer */
static u16 rxIdx; /* index of the current TX buffer */
/* DMAx_CONFIG values at DMA Restart */
static const union {
u16 data;
ADI_DMA_CONFIG_REG reg;
} txdmacfg = {
.reg = {
.b_DMA_EN = 1, /* enabled */
.b_WNR = 0, /* read from memory */
.b_WDSIZE = 2, /* wordsize is 32 bits */
.b_DMA2D = 0,
.b_RESTART = 0,
.b_DI_SEL = 0,
.b_DI_EN = 0, /* no interrupt */
.b_NDSIZE = 5, /* 5 half words is desc size */
.b_FLOW = 7 /* large desc flow */
},
};
static int bfin_miiphy_wait(void)
{
/* poll the STABUSY bit */
while (bfin_read_EMAC_STAADD() & STABUSY)
continue;
return 0;
}
static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
{
ushort val = 0;
if (bfin_miiphy_wait())
return 1;
bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
if (bfin_miiphy_wait())
return 1;
val = bfin_read_EMAC_STADAT();
return val;
}
static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 val)
{
if (bfin_miiphy_wait())
return 1;
bfin_write_EMAC_STADAT(val);
bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
return 0;
}
int bfin_EMAC_initialize(bd_t *bis)
{
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
dev->init = bfin_EMAC_init;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
dev->write_hwaddr = bfin_EMAC_setup_addr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bfin_miiphy_read;
mdiodev->write = bfin_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
dev->priv = mdiodev;
#endif
return 0;
}
static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
{
int i;
int result = 0;
if (length <= 0) {
printf("Ethernet: bad packet size: %d\n", length);
goto out;
}
if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
printf("Ethernet: tx DMA error\n");
goto out;
}
for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
}
}
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
bfin_write_DMA2_CONFIG(txdmacfg.data);
bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx error\n");
goto out;
}
}
result = txbuf[txIdx]->StatusWord;
txbuf[txIdx]->StatusWord = 0;
if ((txIdx + 1) >= TX_BUF_CNT)
txIdx = 0;
else
txIdx++;
out:
debug("BFIN EMAC send: length = %d\n", length);
return result;
}
static int bfin_EMAC_recv(struct eth_device *dev)
{
int length = 0;
for (;;) {
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
length = -1;
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
printf("Ethernet: rx dma overrun\n");
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
printf("Ethernet: rx error\n");
break;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
if (length <= 4) {
printf("Ethernet: bad frame\n");
break;
}
debug("%s: len = %d\n", __func__, length - 4);
net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
net_process_received_packet(net_rx_packets[rxIdx], length - 4);
bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
else
rxIdx++;
}
return length;
}
/**************************************************************
*
* Ethernet Initialization Routine
*
*************************************************************/
/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
#ifndef CONFIG_BFIN_MAC_PINS
# ifdef CONFIG_RMII
# define CONFIG_BFIN_MAC_PINS P_RMII0
# else
# define CONFIG_BFIN_MAC_PINS P_MII0
# endif
#endif
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
int phydat;
size_t count;
struct mii_dev *mdiodev = dev->priv;
/* Enable PHY output */
bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
/* Set all the pins to peripheral mode */
peripheral_request_list(pins, "bfin_mac");
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
/* turn on auto-negotiation and wait for link to come up */
bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR,
BMCR_ANENABLE);
count = 0;
while (1) {
++count;
phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR,
MDIO_DEVAD_NONE, MII_BMSR);
if (phydat < 0)
return phydat;
if (phydat & BMSR_LSTATUS)
break;
if (count > 30000) {
printf("%s: link down, check cable\n", dev->name);
return -1;
}
udelay(100);
}
/* see what kind of link we have */
phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE,
MII_LPA);
if (phydat < 0)
return phydat;
if (phydat & LPA_DUPLEX)
*opmode = FDMODE;
else
*opmode = 0;
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
/* Initialize the TX DMA channel registers */
bfin_write_DMA2_X_COUNT(0);
bfin_write_DMA2_X_MODIFY(4);
bfin_write_DMA2_Y_COUNT(0);
bfin_write_DMA2_Y_MODIFY(0);
/* Initialize the RX DMA channel registers */
bfin_write_DMA1_X_COUNT(0);
bfin_write_DMA1_X_MODIFY(4);
bfin_write_DMA1_Y_COUNT(0);
bfin_write_DMA1_Y_MODIFY(0);
return 0;
}
static int bfin_EMAC_setup_addr(struct eth_device *dev)
{
bfin_write_EMAC_ADDRLO(
dev->enetaddr[0] |
dev->enetaddr[1] << 8 |
dev->enetaddr[2] << 16 |
dev->enetaddr[3] << 24
);
bfin_write_EMAC_ADDRHI(
dev->enetaddr[4] |
dev->enetaddr[5] << 8
);
return 0;
}
static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
u32 opmode;
int dat;
int i;
debug("Eth_init: ......\n");
txIdx = 0;
rxIdx = 0;
/* Initialize System Register */
if (bfin_miiphy_init(dev, &dat) < 0)
return -1;
/* Initialize EMAC address */
bfin_EMAC_setup_addr(dev);
/* Initialize TX and RX buffer */
for (i = 0; i < PKTBUFSRX; i++) {
rxbuf[i] = SetupRxBuffer(i);
if (i > 0) {
rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
if (i == (PKTBUFSRX - 1))
rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
}
}
for (i = 0; i < TX_BUF_CNT; i++) {
txbuf[i] = SetupTxBuffer(i);
if (i > 0) {
txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
if (i == (TX_BUF_CNT - 1))
txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
}
}
/* Set RX DMA */
bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
/* Wait MII done */
bfin_miiphy_wait();
/* We enable only RX here */
/* ASTP : Enable Automatic Pad Stripping
PR : Promiscuous Mode for test
PSF : Receive frames with total length less than 64 bytes.
FDMODE : Full Duplex Mode
LB : Internal Loopback for test
RE : Receiver Enable */
if (dat == FDMODE)
opmode = ASTP | FDMODE | PSF;
else
opmode = ASTP | PSF;
opmode |= RE;
#ifdef CONFIG_RMII
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
bfin_write_EMAC_OPMODE(opmode);
return 0;
}
static void bfin_EMAC_halt(struct eth_device *dev)
{
debug("Eth_halt: ......\n");
/* Turn off the EMAC */
bfin_write_EMAC_OPMODE(0);
/* Turn off the EMAC RX DMA */
bfin_write_DMA1_CONFIG(0);
bfin_write_DMA2_CONFIG(0);
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0xfe, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
return buf;
}
ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0x00, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
return buf;
}
#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
uchar buf[64];
int i, value = 0;
int length;
uint addr;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
addr = bfin_read_EMAC_ADDRLO();
buf[0] = buf[6] = addr;
buf[1] = buf[7] = addr >> 8;
buf[2] = buf[8] = addr >> 16;
buf[3] = buf[9] = addr >> 24;
addr = bfin_read_EMAC_ADDRHI();
buf[4] = buf[10] = addr;
buf[5] = buf[11] = addr >> 8;
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
buf[15] = 0x01;
buf[16] = 0x08; /* Protocal type: IP */
buf[17] = 0x00;
buf[18] = 0x06; /* Hardware size */
buf[19] = 0x04; /* Protocol size */
buf[20] = 0x00; /* Opcode: request */
buf[21] = 0x01;
for (i = 0; i < 42; i++)
buf[i + 22] = i;
printf("--------Send 64 bytes......\n");
bfin_EMAC_send(NULL, buf, 64);
for (i = 0; i < 100; i++) {
udelay(10000);
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
value = 1;
break;
}
}
if (value == 0) {
printf("--------EMAC can't receive any data\n");
eth_halt();
return -1;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
for (i = 0; i < length; i++) {
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
printf("--------EMAC receive error data!\n");
eth_halt();
return -1;
}
}
printf("--------receive %d bytes, matched\n", length);
bfin_EMAC_halt(NULL);
return 0;
}
#endif

65
drivers/net/bfin_mac.h
Unescape View File

@ -1,65 +0,0 @@
/*
* bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
*
* Copyright (c) 2005-2008 Analog Device, Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MAC_H__
#define __BFIN_MAC_H__
#define RECV_BUFSIZE (0x614)
typedef struct ADI_DMA_CONFIG_REG {
u16 b_DMA_EN:1; /* 0 Enabled */
u16 b_WNR:1; /* 1 Direction */
u16 b_WDSIZE:2; /* 2:3 Transfer word size */
u16 b_DMA2D:1; /* 4 DMA mode */
u16 b_RESTART:1; /* 5 Retain FIFO */
u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
u16 b_DI_EN:1; /* 7 Data interrupt enabled */
u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
u16 b_FLOW:3; /* 12:14Flow */
} ADI_DMA_CONFIG_REG;
typedef struct adi_ether_frame_buffer {
u16 NoBytes; /* the no. of following bytes */
u8 Dest[6]; /* destination MAC address */
u8 Srce[6]; /* source MAC address */
u16 LTfield; /* length/type field */
u8 Data[0]; /* payload bytes */
} ADI_ETHER_FRAME_BUFFER;
/* 16 bytes/struct */
typedef struct dma_descriptor {
struct dma_descriptor *NEXT_DESC_PTR;
u32 START_ADDR;
union {
u16 CONFIG_DATA;
ADI_DMA_CONFIG_REG CONFIG;
};
} DMA_DESCRIPTOR;
/* 10 bytes/struct in 12 bytes */
typedef struct adi_ether_buffer {
DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
struct adi_ether_buffer *pNext; /* next buffer */
struct adi_ether_buffer *pPrev; /* prev buffer */
u16 IPHdrChksum; /* the IP header checksum */
u16 IPPayloadChksum; /* the IP header and payload checksum */
volatile u32 StatusWord; /* the frame status word */
} ADI_ETHER_BUFFER;
/* 40 bytes/struct in 44 bytes */
static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
static void bfin_EMAC_halt(struct eth_device *dev);
static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length);
static int bfin_EMAC_recv(struct eth_device *dev);
static int bfin_EMAC_setup_addr(struct eth_device *dev);
#endif

1
drivers/rtc/Makefile
Unescape View File

@ -9,7 +9,6 @@
obj-$(CONFIG_DM_RTC) += rtc-uclass.o
obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o
obj-y += date.o
obj-$(CONFIG_RTC_DAVINCI) += davinci.o
obj-$(CONFIG_RTC_DS1302) += ds1302.o

121
drivers/rtc/bfin_rtc.c
Unescape View File

@ -1,121 +0,0 @@
/*
* Copyright (c) 2004-2008 Analog Devices Inc.
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
#include <asm/blackfin.h>
#include <asm/mach-common/bits/rtc.h>
#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
#define MIN_TO_SECS(x) (60 * (x))
#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x))
#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x))
#define NUM_SECS_IN_MIN MIN_TO_SECS(1)
#define NUM_SECS_IN_HR HRS_TO_SECS(1)
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Enable the RTC prescaler enable register */
void rtc_init(void)
{
if (!(bfin_read_RTC_PREN() & 0x1))
bfin_write_RTC_PREN(0x1);
}
/* Our on-chip RTC has no notion of "reset" */
void rtc_reset(void)
{
rtc_init();
}
/* Wait for pending writes to complete */
static void wait_for_complete(void)
{
pr_stamp();
while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE))
if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING))
break;
bfin_write_RTC_ISTAT(WRITE_COMPLETE);
}
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long remain, days, hrs, mins, secs;
pr_stamp();
if (tmp == NULL) {
puts("Error setting the date/time\n");
return -1;
}
rtc_init();
wait_for_complete();
/* Calculate number of seconds this incoming time represents */
remain = rtc_mktime(tmp);
/* Figure out how many days since epoch */
days = remain / NUM_SECS_IN_DAY;
/* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
remain = remain % NUM_SECS_IN_DAY;
hrs = remain / NUM_SECS_IN_HR;
remain = remain % NUM_SECS_IN_HR;
mins = remain / NUM_SECS_IN_MIN;
secs = remain % NUM_SECS_IN_MIN;
/* Encode these time values into our RTC_STAT register */
bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs));
return 0;
}
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
int rtc_get(struct rtc_time *tmp)
{
uint32_t cur_rtc_stat;
int time_in_sec;
int tm_sec, tm_min, tm_hr, tm_day;
pr_stamp();
if (tmp == NULL) {
puts("Error getting the date/time\n");
return -1;
}
rtc_init();
wait_for_complete();
/* Read the RTC_STAT register */
cur_rtc_stat = bfin_read_RTC_STAT();
/* Convert our encoded format into actual time values */
tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P;
tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P;
tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P;
tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P;
/* Calculate the total number of seconds since epoch */
time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day);
rtc_to_tm(time_in_sec, tmp);
return 0;
}
#endif

1
drivers/watchdog/Makefile
Unescape View File

@ -12,7 +12,6 @@ obj-y += imx_watchdog.o
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o

27
drivers/watchdog/bfin_wdt.c
Unescape View File

@ -1,27 +0,0 @@
/*
* watchdog.c - driver for Blackfin on-chip watchdog
*
* Copyright (c) 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <watchdog.h>
#include <asm/blackfin.h>
#include <asm/clock.h>
#include <asm/mach-common/bits/watchdog.h>
void hw_watchdog_reset(void)
{
bfin_write_WDOG_STAT(0);
}
void hw_watchdog_init(void)
{
bfin_write_WDOG_CTL(WDDIS);
SSYNC();
bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk());
hw_watchdog_reset();
bfin_write_WDOG_CTL(WDEN);
}
Write Preview
Loading…
Cancel
Save