Import the upstream kernel dts into U-Boot. Currently only serial is supported, but a lot more DT changes are queued for v4.7. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>master
parent
11b9a4d8d9
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/* |
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* dts file for Hisilicon HiKey Development Board |
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* |
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* Copyright (C) 2015, Hisilicon Ltd. |
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* |
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*/ |
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|
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/dts-v1/; |
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/*Reserved 1MB memory for MCU*/ |
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/memreserve/ 0x05e00000 0x00100000; |
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#include "hi6220.dtsi" |
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/ { |
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model = "HiKey Development Board"; |
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compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; |
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|
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aliases { |
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serial0 = &uart0; /* On board UART0 */ |
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serial1 = &uart1; /* BT UART */ |
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serial2 = &uart2; /* LS Expansion UART0 */ |
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serial3 = &uart3; /* LS Expansion UART1 */ |
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}; |
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chosen { |
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stdout-path = "serial3:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x40000000>; |
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}; |
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}; |
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&uart2 { |
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label = "LS-UART0"; |
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}; |
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&uart3 { |
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label = "LS-UART1"; |
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}; |
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/* |
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* dts file for Hisilicon Hi6220 SoC |
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* |
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* Copyright (C) 2015, Hisilicon Ltd. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/hi6220-clock.h> |
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/ { |
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compatible = "hisilicon,hi6220"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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|
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&cpu0>; |
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}; |
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core1 { |
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cpu = <&cpu1>; |
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}; |
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core2 { |
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cpu = <&cpu2>; |
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}; |
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core3 { |
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cpu = <&cpu3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&cpu4>; |
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}; |
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core1 { |
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cpu = <&cpu5>; |
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}; |
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core2 { |
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cpu = <&cpu6>; |
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}; |
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core3 { |
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cpu = <&cpu7>; |
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}; |
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}; |
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}; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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}; |
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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}; |
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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}; |
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cpu4: cpu@100 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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}; |
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cpu5: cpu@101 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x101>; |
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enable-method = "psci"; |
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}; |
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cpu6: cpu@102 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x102>; |
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enable-method = "psci"; |
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}; |
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cpu7: cpu@103 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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device_type = "cpu"; |
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reg = <0x0 0x103>; |
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enable-method = "psci"; |
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}; |
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}; |
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gic: interrupt-controller@f6801000 { |
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compatible = "arm,gic-400"; |
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reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ |
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<0x0 0xf6802000 0 0x2000>, /* GICC */ |
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<0x0 0xf6804000 0 0x2000>, /* GICH */ |
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<0x0 0xf6806000 0 0x2000>; /* GICV */ |
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#address-cells = <0>; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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ao_ctrl: ao_ctrl@f7800000 { |
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compatible = "hisilicon,hi6220-aoctrl", "syscon"; |
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reg = <0x0 0xf7800000 0x0 0x2000>; |
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#clock-cells = <1>; |
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}; |
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sys_ctrl: sys_ctrl@f7030000 { |
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compatible = "hisilicon,hi6220-sysctrl", "syscon"; |
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reg = <0x0 0xf7030000 0x0 0x2000>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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media_ctrl: media_ctrl@f4410000 { |
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compatible = "hisilicon,hi6220-mediactrl", "syscon"; |
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reg = <0x0 0xf4410000 0x0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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pm_ctrl: pm_ctrl@f7032000 { |
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compatible = "hisilicon,hi6220-pmctrl", "syscon"; |
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reg = <0x0 0xf7032000 0x0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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uart0: uart@f8015000 { /* console */ |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xf8015000 0x0 0x1000>; |
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&ao_ctrl HI6220_UART0_PCLK>, |
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<&ao_ctrl HI6220_UART0_PCLK>; |
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clock-names = "uartclk", "apb_pclk"; |
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}; |
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uart1: uart@f7111000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xf7111000 0x0 0x1000>; |
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&sys_ctrl HI6220_UART1_PCLK>, |
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<&sys_ctrl HI6220_UART1_PCLK>; |
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clock-names = "uartclk", "apb_pclk"; |
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status = "disabled"; |
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}; |
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uart2: uart@f7112000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xf7112000 0x0 0x1000>; |
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&sys_ctrl HI6220_UART2_PCLK>, |
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<&sys_ctrl HI6220_UART2_PCLK>; |
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clock-names = "uartclk", "apb_pclk"; |
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status = "disabled"; |
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}; |
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uart3: uart@f7113000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xf7113000 0x0 0x1000>; |
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&sys_ctrl HI6220_UART3_PCLK>, |
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<&sys_ctrl HI6220_UART3_PCLK>; |
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clock-names = "uartclk", "apb_pclk"; |
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}; |
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uart4: uart@f7114000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x0 0xf7114000 0x0 0x1000>; |
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&sys_ctrl HI6220_UART4_PCLK>, |
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<&sys_ctrl HI6220_UART4_PCLK>; |
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clock-names = "uartclk", "apb_pclk"; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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/*
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* Copyright (c) 2015 Hisilicon Limited. |
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* |
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* Author: Bintian Wang <bintian.wang@huawei.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __DT_BINDINGS_CLOCK_HI6220_H |
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#define __DT_BINDINGS_CLOCK_HI6220_H |
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/* clk in Hi6220 AO (always on) controller */ |
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#define HI6220_NONE_CLOCK 0 |
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/* fixed rate clocks */ |
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#define HI6220_REF32K 1 |
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#define HI6220_CLK_TCXO 2 |
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#define HI6220_MMC1_PAD 3 |
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#define HI6220_MMC2_PAD 4 |
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#define HI6220_MMC0_PAD 5 |
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#define HI6220_PLL_BBP 6 |
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#define HI6220_PLL_GPU 7 |
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#define HI6220_PLL1_DDR 8 |
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#define HI6220_PLL_SYS 9 |
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#define HI6220_PLL_SYS_MEDIA 10 |
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#define HI6220_DDR_SRC 11 |
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#define HI6220_PLL_MEDIA 12 |
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#define HI6220_PLL_DDR 13 |
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/* fixed factor clocks */ |
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#define HI6220_300M 14 |
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#define HI6220_150M 15 |
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#define HI6220_PICOPHY_SRC 16 |
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#define HI6220_MMC0_SRC_SEL 17 |
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#define HI6220_MMC1_SRC_SEL 18 |
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#define HI6220_MMC2_SRC_SEL 19 |
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#define HI6220_VPU_CODEC 20 |
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#define HI6220_MMC0_SMP 21 |
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#define HI6220_MMC1_SMP 22 |
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#define HI6220_MMC2_SMP 23 |
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/* gate clocks */ |
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#define HI6220_WDT0_PCLK 24 |
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#define HI6220_WDT1_PCLK 25 |
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#define HI6220_WDT2_PCLK 26 |
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#define HI6220_TIMER0_PCLK 27 |
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#define HI6220_TIMER1_PCLK 28 |
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#define HI6220_TIMER2_PCLK 29 |
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#define HI6220_TIMER3_PCLK 30 |
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#define HI6220_TIMER4_PCLK 31 |
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#define HI6220_TIMER5_PCLK 32 |
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#define HI6220_TIMER6_PCLK 33 |
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#define HI6220_TIMER7_PCLK 34 |
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#define HI6220_TIMER8_PCLK 35 |
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#define HI6220_UART0_PCLK 36 |
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#define HI6220_AO_NR_CLKS 37 |
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/* clk in Hi6220 systrl */ |
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/* gate clock */ |
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#define HI6220_MMC0_CLK 1 |
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#define HI6220_MMC0_CIUCLK 2 |
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#define HI6220_MMC1_CLK 3 |
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#define HI6220_MMC1_CIUCLK 4 |
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#define HI6220_MMC2_CLK 5 |
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#define HI6220_MMC2_CIUCLK 6 |
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#define HI6220_USBOTG_HCLK 7 |
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#define HI6220_CLK_PICOPHY 8 |
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#define HI6220_HIFI 9 |
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#define HI6220_DACODEC_PCLK 10 |
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#define HI6220_EDMAC_ACLK 11 |
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#define HI6220_CS_ATB 12 |
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#define HI6220_I2C0_CLK 13 |
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#define HI6220_I2C1_CLK 14 |
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#define HI6220_I2C2_CLK 15 |
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#define HI6220_I2C3_CLK 16 |
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#define HI6220_UART1_PCLK 17 |
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#define HI6220_UART2_PCLK 18 |
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#define HI6220_UART3_PCLK 19 |
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#define HI6220_UART4_PCLK 20 |
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#define HI6220_SPI_CLK 21 |
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#define HI6220_TSENSOR_CLK 22 |
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#define HI6220_MMU_CLK 23 |
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#define HI6220_HIFI_SEL 24 |
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#define HI6220_MMC0_SYSPLL 25 |
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#define HI6220_MMC1_SYSPLL 26 |
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#define HI6220_MMC2_SYSPLL 27 |
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#define HI6220_MMC0_SEL 28 |
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#define HI6220_MMC1_SEL 29 |
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#define HI6220_BBPPLL_SEL 30 |
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#define HI6220_MEDIA_PLL_SRC 31 |
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#define HI6220_MMC2_SEL 32 |
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#define HI6220_CS_ATB_SYSPLL 33 |
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/* mux clocks */ |
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#define HI6220_MMC0_SRC 34 |
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#define HI6220_MMC0_SMP_IN 35 |
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#define HI6220_MMC1_SRC 36 |
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#define HI6220_MMC1_SMP_IN 37 |
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#define HI6220_MMC2_SRC 38 |
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#define HI6220_MMC2_SMP_IN 39 |
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#define HI6220_HIFI_SRC 40 |
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#define HI6220_UART1_SRC 41 |
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#define HI6220_UART2_SRC 42 |
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#define HI6220_UART3_SRC 43 |
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#define HI6220_UART4_SRC 44 |
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#define HI6220_MMC0_MUX0 45 |
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#define HI6220_MMC1_MUX0 46 |
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#define HI6220_MMC2_MUX0 47 |
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#define HI6220_MMC0_MUX1 48 |
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#define HI6220_MMC1_MUX1 49 |
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#define HI6220_MMC2_MUX1 50 |
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/* divider clocks */ |
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#define HI6220_CLK_BUS 51 |
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#define HI6220_MMC0_DIV 52 |
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#define HI6220_MMC1_DIV 53 |
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#define HI6220_MMC2_DIV 54 |
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#define HI6220_HIFI_DIV 55 |
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#define HI6220_BBPPLL0_DIV 56 |
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#define HI6220_CS_DAPB 57 |
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#define HI6220_CS_ATB_DIV 58 |
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#define HI6220_SYS_NR_CLKS 59 |
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/* clk in Hi6220 media controller */ |
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/* gate clocks */ |
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#define HI6220_DSI_PCLK 1 |
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#define HI6220_G3D_PCLK 2 |
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#define HI6220_ACLK_CODEC_VPU 3 |
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#define HI6220_ISP_SCLK 4 |
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#define HI6220_ADE_CORE 5 |
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#define HI6220_MED_MMU 6 |
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#define HI6220_CFG_CSI4PHY 7 |
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#define HI6220_CFG_CSI2PHY 8 |
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#define HI6220_ISP_SCLK_GATE 9 |
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#define HI6220_ISP_SCLK_GATE1 10 |
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#define HI6220_ADE_CORE_GATE 11 |
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#define HI6220_CODEC_VPU_GATE 12 |
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#define HI6220_MED_SYSPLL 13 |
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/* mux clocks */ |
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#define HI6220_1440_1200 14 |
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#define HI6220_1000_1200 15 |
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#define HI6220_1000_1440 16 |
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/* divider clocks */ |
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#define HI6220_CODEC_JPEG 17 |
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#define HI6220_ISP_SCLK_SRC 18 |
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#define HI6220_ISP_SCLK1 19 |
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#define HI6220_ADE_CORE_SRC 20 |
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#define HI6220_ADE_PIX_SRC 21 |
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#define HI6220_G3D_CLK 22 |
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#define HI6220_CODEC_VPU_SRC 23 |
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#define HI6220_MEDIA_NR_CLKS 24 |
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/* clk in Hi6220 power controller */ |
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/* gate clocks */ |
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#define HI6220_PLL_GPU_GATE 1 |
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#define HI6220_PLL1_DDR_GATE 2 |
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#define HI6220_PLL_DDR_GATE 3 |
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#define HI6220_PLL_MEDIA_GATE 4 |
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#define HI6220_PLL0_BBP_GATE 5 |
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/* divider clocks */ |
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#define HI6220_DDRC_SRC 6 |
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#define HI6220_DDRC_AXI1 7 |
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#define HI6220_POWER_NR_CLKS 8 |
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#endif |
Loading…
Reference in new issue