- Update SPDX tag in arch/arm/mach-socfpga/spl_a10.c Signed-off-by: Tom Rini <trini@konsulko.com>lime2-spi
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/* SPDX-License-Identifier: GPL-2.0
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* |
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
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* |
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*/ |
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#ifndef _FIREWALL_S10_ |
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#define _FIREWALL_S10_ |
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struct socfpga_firwall_l4_per { |
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u32 nand; /* 0x00 */ |
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u32 nand_data; |
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u32 _pad_0x8; |
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u32 usb0; |
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u32 usb1; /* 0x10 */ |
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u32 _pad_0x14; |
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u32 _pad_0x18; |
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u32 spim0; |
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u32 spim1; /* 0x20 */ |
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u32 spis0; |
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u32 spis1; |
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u32 emac0; |
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u32 emac1; /* 0x30 */ |
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u32 emac2; |
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u32 _pad_0x38; |
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u32 _pad_0x3c; |
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u32 sdmmc; /* 0x40 */ |
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u32 gpio0; |
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u32 gpio1; |
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u32 _pad_0x4c; |
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u32 i2c0; /* 0x50 */ |
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u32 i2c1; |
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u32 i2c2; |
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u32 i2c3; |
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u32 i2c4; /* 0x60 */ |
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u32 timer0; |
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u32 timer1; |
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u32 uart0; |
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u32 uart1; /* 0x70 */ |
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}; |
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struct socfpga_firwall_l4_sys { |
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u32 _pad_0x00; /* 0x00 */ |
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u32 _pad_0x04; |
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u32 dma_ecc; |
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u32 emac0rx_ecc; |
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u32 emac0tx_ecc; /* 0x10 */ |
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u32 emac1rx_ecc; |
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u32 emac1tx_ecc; |
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u32 emac2rx_ecc; |
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u32 emac2tx_ecc; /* 0x20 */ |
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u32 _pad_0x24; |
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u32 _pad_0x28; |
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u32 nand_ecc; |
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u32 nand_read_ecc; /* 0x30 */ |
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u32 nand_write_ecc; |
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u32 ocram_ecc; |
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u32 _pad_0x3c; |
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u32 sdmmc_ecc; /* 0x40 */ |
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u32 usb0_ecc; |
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u32 usb1_ecc; |
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u32 clock_manager; |
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u32 _pad_0x50; /* 0x50 */ |
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u32 io_manager; |
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u32 reset_manager; |
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u32 system_manager; |
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u32 osc0_timer; /* 0x60 */ |
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u32 osc1_timer; |
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u32 watchdog0; |
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u32 watchdog1; |
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u32 watchdog2; /* 0x70 */ |
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u32 watchdog3; |
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}; |
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#define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16)) |
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#define FIREWALL_BRIDGE_DISABLE_ALL (~0) |
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/* Cache coherency unit (CCU) registers */ |
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#define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640 |
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#define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660 |
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#define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0 |
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#define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600 |
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#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 |
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#define CCU_ADMASK_P_MASK BIT(0) |
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#define CCU_ADMASK_NS_MASK BIT(1) |
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#define CCU_ADBASE_DI_MASK BIT(4) |
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#define CCU_REG_ADDR(reg) \ |
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(SOCFPGA_CCU_ADDRESS + (reg)) |
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/* Firewall MPU DDR SCR registers */ |
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#define FW_MPU_DDR_SCR_EN 0x00 |
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#define FW_MPU_DDR_SCR_EN_SET 0x04 |
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18 |
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#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c |
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 |
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#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c |
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#define MPUREGION0_ENABLE BIT(0) |
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#define NONMPUREGION0_ENABLE BIT(8) |
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#define FW_MPU_DDR_SCR_WRITEL(data, reg) \ |
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writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) |
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#endif /* _FIREWALL_S10_ */ |
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/* SPDX-License-Identifier: GPL-2.0
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* |
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
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* |
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*/ |
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#ifndef _MAILBOX_S10_H_ |
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#define _MAILBOX_S10_H_ |
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/* user define Uboot ID */ |
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#define MBOX_CLIENT_ID_UBOOT 0xB |
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#define MBOX_ID_UBOOT 0x1 |
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#define MBOX_CMD_DIRECT 0 |
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#define MBOX_CMD_INDIRECT 1 |
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#define MBOX_MAX_CMD_INDEX 2047 |
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#define MBOX_CMD_BUFFER_SIZE 32 |
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#define MBOX_RESP_BUFFER_SIZE 16 |
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#define MBOX_HDR_CMD_LSB 0 |
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#define MBOX_HDR_CMD_MSK (BIT(11) - 1) |
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#define MBOX_HDR_I_LSB 11 |
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#define MBOX_HDR_I_MSK BIT(11) |
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#define MBOX_HDR_LEN_LSB 12 |
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#define MBOX_HDR_LEN_MSK 0x007FF000 |
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#define MBOX_HDR_ID_LSB 24 |
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#define MBOX_HDR_ID_MSK 0x0F000000 |
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#define MBOX_HDR_CLIENT_LSB 28 |
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#define MBOX_HDR_CLIENT_MSK 0xF0000000 |
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/* Interrupt flags */ |
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#define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */ |
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#define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */ |
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#define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */ |
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#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \ |
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MBOX_FLAGS_INT_RIE | \
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MBOX_FLAGS_INT_UAE) |
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/* Status */ |
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#define MBOX_STATUS_UA_MSK BIT(8) |
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#define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \ |
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((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
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(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
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(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
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(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \
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(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK)) |
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#define MBOX_RESP_ERR_GET(resp) \ |
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(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB) |
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#define MBOX_RESP_LEN_GET(resp) \ |
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(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB) |
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#define MBOX_RESP_ID_GET(resp) \ |
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(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB) |
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#define MBOX_RESP_CLIENT_GET(resp) \ |
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(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB) |
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/* Response error list */ |
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enum ALT_SDM_MBOX_RESP_CODE { |
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/* CMD completed successfully, but check resp ARGS for any errors */ |
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MBOX_RESP_STATOK = 0, |
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/* CMD is incorrectly formatted in some way */ |
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MBOX_RESP_INVALID_COMMAND = 1, |
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/* BootROM Command code not undesrtood */ |
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MBOX_RESP_UNKNOWN_BR = 2, |
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/* CMD code not recognized by firmware */ |
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MBOX_RESP_UNKNOWN = 3, |
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/* Indicates that the device is not configured */ |
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MBOX_RESP_NOT_CONFIGURED = 256, |
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/* Indicates that the device is busy */ |
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MBOX_RESP_DEVICE_BUSY = 0x1FF, |
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/* Indicates that there is no valid response available */ |
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MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF, |
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/* General Error */ |
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MBOX_RESP_ERROR = 0x3FF, |
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}; |
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/* Mailbox command list */ |
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#define MBOX_RESTART 2 |
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#define MBOX_CONFIG_STATUS 4 |
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#define MBOX_RECONFIG 6 |
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#define MBOX_RECONFIG_MSEL 7 |
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#define MBOX_RECONFIG_DATA 8 |
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#define MBOX_RECONFIG_STATUS 9 |
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#define MBOX_QSPI_OPEN 50 |
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#define MBOX_QSPI_CLOSE 51 |
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#define MBOX_QSPI_DIRECT 59 |
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#define MBOX_REBOOT_HPS 71 |
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/* Mailbox registers */ |
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#define MBOX_CIN 0 /* command valid offset */ |
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#define MBOX_ROUT 4 /* response output offset */ |
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#define MBOX_URG 8 /* urgent command */ |
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#define MBOX_FLAGS 0x0c /* interrupt enables */ |
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#define MBOX_COUT 0x20 /* command free offset */ |
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#define MBOX_RIN 0x24 /* respond valid offset */ |
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#define MBOX_STATUS 0x2c /* mailbox status */ |
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#define MBOX_CMD_BUF 0x40 /* circular command buffer */ |
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#define MBOX_RESP_BUF 0xc0 /* circular response buffer */ |
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#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */ |
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#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */ |
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/* Status and bit information returned by RECONFIG_STATUS */ |
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#define RECONFIG_STATUS_RESPONSE_LEN 6 |
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#define RECONFIG_STATUS_STATE 0 |
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#define RECONFIG_STATUS_PIN_STATUS 2 |
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3 |
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#define MBOX_CFGSTAT_STATE_IDLE 0x00000000 |
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 |
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#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 |
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#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 |
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#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 |
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#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 |
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#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 |
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 |
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#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 |
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 |
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 |
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#define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0) |
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#define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1) |
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#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3) |
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#define RCF_PIN_STATUS_NSTATUS BIT(31) |
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int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent, |
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u32 *resp_buf_len, u32 *resp_buf); |
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int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, |
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u8 urgent, u32 *resp_buf_len, u32 *resp_buf); |
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int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); |
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int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg); |
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int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); |
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int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); |
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int mbox_init(void); |
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#ifdef CONFIG_CADENCE_QSPI |
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int mbox_qspi_close(void); |
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int mbox_qspi_open(void); |
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#endif |
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int mbox_reset_cold(void); |
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#endif /* _MAILBOX_S10_H_ */ |
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/* SPDX-License-Identifier: GPL-2.0
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* |
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
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* |
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*/ |
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#ifndef _SDRAM_S10_H_ |
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#define _SDRAM_S10_H_ |
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unsigned long sdram_calculate_size(void); |
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int sdram_mmr_init_full(unsigned int sdr_phy_reg); |
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int sdram_calibration_full(void); |
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#define DDR_TWR 15 |
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#define DDR_READ_LATENCY_DELAY 40 |
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#define DDR_ACTIVATE_FAWBANK 0x1 |
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/* ECC HMC registers */ |
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#define DDRIOCTRL 0x8 |
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#define DDRCALSTAT 0xc |
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#define DRAMADDRWIDTH 0xe0 |
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#define ECCCTRL1 0x100 |
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#define ECCCTRL2 0x104 |
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#define ERRINTEN 0x110 |
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#define INTMODE 0x11c |
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#define INTSTAT 0x120 |
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#define AUTOWB_CORRADDR 0x138 |
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#define ECC_REG2WRECCDATABUS 0x144 |
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#define ECC_DIAGON 0x150 |
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#define ECC_DECSTAT 0x154 |
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#define HPSINTFCSEL 0x210 |
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#define RSTHANDSHAKECTRL 0x214 |
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#define RSTHANDSHAKESTAT 0x218 |
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#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 |
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#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) |
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#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) |
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#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) |
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#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) |
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#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) |
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#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) |
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#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) |
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#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) |
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#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) |
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#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) |
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#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) |
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#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) |
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#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) |
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#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) |
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#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff |
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#define DDR_HMC_CORE2SEQ_INT_REQ 0xF |
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#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) |
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#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f |
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/* NOC DDR scheduler */ |
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#define DDR_SCH_ID_COREID 0 |
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#define DDR_SCH_ID_REVID 0x4 |
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#define DDR_SCH_DDRCONF 0x8 |
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#define DDR_SCH_DDRTIMING 0xc |
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#define DDR_SCH_DDRMODE 0x10 |
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#define DDR_SCH_READ_LATENCY 0x14 |
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#define DDR_SCH_ACTIVATE 0x38 |
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#define DDR_SCH_DEVTODEV 0x3c |
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#define DDR_SCH_DDR4TIMING 0x40 |
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#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 |
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#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 |
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#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 |
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#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 |
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#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 |
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#define DDR_SCH_DDRTIMING_WRTORD_OFF 26 |
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#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 |
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#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 |
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#define DDR_SCH_ACTIVATE_RRD_OFF 0 |
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#define DDR_SCH_ACTIVATE_FAW_OFF 4 |
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#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 |
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#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 |
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#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 |
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#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4 |
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/* HMC MMR IO48 registers */ |
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#define CTRLCFG0 0x28 |
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#define CTRLCFG1 0x2c |
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#define DRAMTIMING0 0x50 |
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#define CALTIMING0 0x7c |
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#define CALTIMING1 0x80 |
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#define CALTIMING2 0x84 |
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#define CALTIMING3 0x88 |
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#define CALTIMING4 0x8c |
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#define CALTIMING9 0xa0 |
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#define DRAMADDRW 0xa8 |
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#define DRAMSTS 0xec |
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#define NIOSRESERVED0 0x110 |
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#define NIOSRESERVED1 0x114 |
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#define NIOSRESERVED2 0x118 |
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#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ |
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(((x) >> 0) & 0x1F) |
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#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ |
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(((x) >> 5) & 0x1F) |
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#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ |
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(((x) >> 10) & 0xF) |
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#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ |
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(((x) >> 14) & 0x3) |
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#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ |
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(((x) >> 16) & 0x7) |
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#define CTRLCFG0_CFG_MEMTYPE(x) \ |
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(((x) >> 0) & 0xF) |
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#define CTRLCFG0_CFG_DIMM_TYPE(x) \ |
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(((x) >> 4) & 0x7) |
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#define CTRLCFG0_CFG_AC_POS(x) \ |
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(((x) >> 7) & 0x3) |
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#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ |
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(((x) >> 9) & 0x1F) |
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#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ |
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(((x) >> 0) & 0x1F) |
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#define CTRLCFG1_CFG_ADDR_ORDER(x) \ |
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(((x) >> 5) & 0x3) |
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#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ |
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(((x) >> 7) & 0x1) |
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#define DRAMTIMING0_CFG_TCL(x) \ |
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(((x) >> 0) & 0x7F) |
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#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ |
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(((x) >> 0) & 0x3F) |
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#define CALTIMING0_CFG_ACT_TO_PCH(x) \ |
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(((x) >> 6) & 0x3F) |
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#define CALTIMING0_CFG_ACT_TO_ACT(x) \ |
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(((x) >> 12) & 0x3F) |
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#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ |
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(((x) >> 18) & 0x3F) |
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#define CALTIMING1_CFG_RD_TO_RD(x) \ |
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(((x) >> 0) & 0x3F) |
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#define CALTIMING1_CFG_RD_TO_RD_DC(x) \ |
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(((x) >> 6) & 0x3F) |
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#define CALTIMING1_CFG_RD_TO_RD_DB(x) \ |
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(((x) >> 12) & 0x3F) |
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#define CALTIMING1_CFG_RD_TO_WR(x) \ |
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(((x) >> 18) & 0x3F) |
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#define CALTIMING1_CFG_RD_TO_WR_DC(x) \ |
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(((x) >> 24) & 0x3F) |
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#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ |
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(((x) >> 0) & 0x3F) |
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#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ |
||||
(((x) >> 6) & 0x3F) |
||||
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ |
||||
(((x) >> 12) & 0x3F) |
||||
#define CALTIMING2_CFG_WR_TO_WR(x) \ |
||||
(((x) >> 18) & 0x3F) |
||||
#define CALTIMING2_CFG_WR_TO_WR_DC(x) \ |
||||
(((x) >> 24) & 0x3F) |
||||
|
||||
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ |
||||
(((x) >> 0) & 0x3F) |
||||
#define CALTIMING3_CFG_WR_TO_RD(x) \ |
||||
(((x) >> 6) & 0x3F) |
||||
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \ |
||||
(((x) >> 12) & 0x3F) |
||||
#define CALTIMING3_CFG_WR_TO_RD_DB(x) \ |
||||
(((x) >> 18) & 0x3F) |
||||
#define CALTIMING3_CFG_WR_TO_PCH(x) \ |
||||
(((x) >> 24) & 0x3F) |
||||
|
||||
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ |
||||
(((x) >> 0) & 0x3F) |
||||
#define CALTIMING4_CFG_PCH_TO_VALID(x) \ |
||||
(((x) >> 6) & 0x3F) |
||||
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ |
||||
(((x) >> 12) & 0x3F) |
||||
#define CALTIMING4_CFG_ARF_TO_VALID(x) \ |
||||
(((x) >> 18) & 0xFF) |
||||
#define CALTIMING4_CFG_PDN_TO_VALID(x) \ |
||||
(((x) >> 26) & 0x3F) |
||||
|
||||
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ |
||||
(((x) >> 0) & 0xFF) |
||||
|
||||
#endif /* _SDRAM_S10_H_ */ |
@ -0,0 +1,380 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <wait_bit.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/mailbox_s10.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <asm/secure.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define MBOX_READL(reg) \ |
||||
readl(SOCFPGA_MAILBOX_ADDRESS + (reg)) |
||||
|
||||
#define MBOX_WRITEL(data, reg) \ |
||||
writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg)) |
||||
|
||||
#define MBOX_READ_RESP_BUF(rout) \ |
||||
MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32))) |
||||
|
||||
#define MBOX_WRITE_CMD_BUF(data, cin) \ |
||||
MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32))) |
||||
|
||||
static __always_inline int mbox_polling_resp(u32 rout) |
||||
{ |
||||
u32 rin; |
||||
unsigned long i = ~0; |
||||
|
||||
while (i) { |
||||
rin = MBOX_READL(MBOX_RIN); |
||||
if (rout != rin) |
||||
return 0; |
||||
|
||||
i--; |
||||
} |
||||
|
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
/* Check for available slot and write to circular buffer.
|
||||
* It also update command valid offset (cin) register. |
||||
*/ |
||||
static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len, |
||||
u32 *arg) |
||||
{ |
||||
u32 cin; |
||||
u32 cout; |
||||
u32 i; |
||||
|
||||
cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE; |
||||
cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE; |
||||
|
||||
/* if command buffer is full or not enough free space
|
||||
* to fit the data |
||||
*/ |
||||
if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout || |
||||
((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) % |
||||
MBOX_CMD_BUFFER_SIZE) < len) |
||||
return -ENOMEM; |
||||
|
||||
/* write header to circular buffer */ |
||||
MBOX_WRITE_CMD_BUF(header, cin++); |
||||
/* wrapping around when it reach the buffer size */ |
||||
cin %= MBOX_CMD_BUFFER_SIZE; |
||||
|
||||
/* write arguments */ |
||||
for (i = 0; i < len; i++) { |
||||
MBOX_WRITE_CMD_BUF(arg[i], cin++); |
||||
/* wrapping around when it reach the buffer size */ |
||||
cin %= MBOX_CMD_BUFFER_SIZE; |
||||
} |
||||
|
||||
/* write command valid offset */ |
||||
MBOX_WRITEL(cin, MBOX_CIN); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Check the command and fill it into circular buffer */ |
||||
static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd, |
||||
u8 is_indirect, u32 len, |
||||
u32 *arg) |
||||
{ |
||||
u32 header; |
||||
int ret; |
||||
|
||||
/* Total length is command + argument length */ |
||||
if ((len + 1) > MBOX_CMD_BUFFER_SIZE) |
||||
return -EINVAL; |
||||
|
||||
if (cmd > MBOX_MAX_CMD_INDEX) |
||||
return -EINVAL; |
||||
|
||||
header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len, |
||||
(is_indirect) ? 1 : 0, cmd); |
||||
|
||||
ret = mbox_fill_cmd_circular_buff(header, len, arg); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/* Send command only without waiting for responses from SDM */ |
||||
static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd, |
||||
u8 is_indirect, u32 len, |
||||
u32 *arg) |
||||
{ |
||||
int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); |
||||
/* write doorbell */ |
||||
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/* Return number of responses received in buffer */ |
||||
static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len) |
||||
{ |
||||
u32 rin; |
||||
u32 rout; |
||||
u32 resp_len = 0; |
||||
|
||||
/* clear doorbell from SDM if it was SET */ |
||||
if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1) |
||||
MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); |
||||
|
||||
/* read current response offset */ |
||||
rout = MBOX_READL(MBOX_ROUT); |
||||
/* read response valid offset */ |
||||
rin = MBOX_READL(MBOX_RIN); |
||||
|
||||
while (rin != rout && (resp_len < resp_buf_max_len)) { |
||||
/* Response received */ |
||||
if (resp_buf) |
||||
resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout); |
||||
|
||||
rout++; |
||||
/* wrapping around when it reach the buffer size */ |
||||
rout %= MBOX_RESP_BUFFER_SIZE; |
||||
/* update next ROUT */ |
||||
MBOX_WRITEL(rout, MBOX_ROUT); |
||||
} |
||||
|
||||
return resp_len; |
||||
} |
||||
|
||||
/* Support one command and up to 31 words argument length only */ |
||||
static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect, |
||||
u32 len, u32 *arg, u8 urgent, |
||||
u32 *resp_buf_len, |
||||
u32 *resp_buf) |
||||
{ |
||||
u32 rin; |
||||
u32 resp; |
||||
u32 rout; |
||||
u32 status; |
||||
u32 resp_len; |
||||
u32 buf_len; |
||||
int ret; |
||||
|
||||
ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
if (urgent) { |
||||
/* Read status because it is toggled */ |
||||
status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK; |
||||
/* Send command as urgent command */ |
||||
MBOX_WRITEL(1, MBOX_URG); |
||||
} |
||||
|
||||
/* write doorbell */ |
||||
MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM); |
||||
|
||||
while (1) { |
||||
ret = ~0; |
||||
|
||||
/* Wait for doorbell from SDM */ |
||||
while (!MBOX_READL(MBOX_DOORBELL_FROM_SDM) && ret--) |
||||
; |
||||
if (!ret) |
||||
return -ETIMEDOUT; |
||||
|
||||
/* clear interrupt */ |
||||
MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); |
||||
|
||||
if (urgent) { |
||||
u32 new_status = MBOX_READL(MBOX_STATUS); |
||||
/* urgent command doesn't have response */ |
||||
MBOX_WRITEL(0, MBOX_URG); |
||||
/* Urgent ACK is toggled */ |
||||
if ((new_status & MBOX_STATUS_UA_MSK) ^ status) |
||||
return 0; |
||||
|
||||
return -ECOMM; |
||||
} |
||||
|
||||
/* read current response offset */ |
||||
rout = MBOX_READL(MBOX_ROUT); |
||||
|
||||
/* read response valid offset */ |
||||
rin = MBOX_READL(MBOX_RIN); |
||||
|
||||
if (rout != rin) { |
||||
/* Response received */ |
||||
resp = MBOX_READ_RESP_BUF(rout); |
||||
rout++; |
||||
/* wrapping around when it reach the buffer size */ |
||||
rout %= MBOX_RESP_BUFFER_SIZE; |
||||
/* update next ROUT */ |
||||
MBOX_WRITEL(rout, MBOX_ROUT); |
||||
|
||||
/* check client ID and ID */ |
||||
if ((MBOX_RESP_CLIENT_GET(resp) == |
||||
MBOX_CLIENT_ID_UBOOT) && |
||||
(MBOX_RESP_ID_GET(resp) == id)) { |
||||
ret = MBOX_RESP_ERR_GET(resp); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
if (resp_buf_len) { |
||||
buf_len = *resp_buf_len; |
||||
*resp_buf_len = 0; |
||||
} else { |
||||
buf_len = 0; |
||||
} |
||||
|
||||
resp_len = MBOX_RESP_LEN_GET(resp); |
||||
while (resp_len) { |
||||
ret = mbox_polling_resp(rout); |
||||
if (ret) |
||||
return ret; |
||||
/* we need to process response buffer
|
||||
* even caller doesn't need it |
||||
*/ |
||||
resp = MBOX_READ_RESP_BUF(rout); |
||||
rout++; |
||||
resp_len--; |
||||
rout %= MBOX_RESP_BUFFER_SIZE; |
||||
MBOX_WRITEL(rout, MBOX_ROUT); |
||||
if (buf_len) { |
||||
/* copy response to buffer */ |
||||
resp_buf[*resp_buf_len] = resp; |
||||
(*resp_buf_len)++; |
||||
buf_len--; |
||||
} |
||||
} |
||||
return ret; |
||||
} |
||||
} |
||||
}; |
||||
|
||||
return -EIO; |
||||
} |
||||
|
||||
int mbox_init(void) |
||||
{ |
||||
int ret; |
||||
|
||||
/* enable mailbox interrupts */ |
||||
MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS); |
||||
|
||||
/* Ensure urgent request is cleared */ |
||||
MBOX_WRITEL(0, MBOX_URG); |
||||
|
||||
/* Ensure the Doorbell Interrupt is cleared */ |
||||
MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM); |
||||
|
||||
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0, |
||||
NULL, 1, 0, NULL); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* Renable mailbox interrupts after MBOX_RESTART */ |
||||
MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CADENCE_QSPI |
||||
int mbox_qspi_close(void) |
||||
{ |
||||
return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT, |
||||
0, NULL, 0, 0, NULL); |
||||
} |
||||
|
||||
int mbox_qspi_open(void) |
||||
{ |
||||
static const struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
int ret; |
||||
u32 resp_buf[1]; |
||||
u32 resp_buf_len; |
||||
|
||||
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT, |
||||
0, NULL, 0, 0, NULL); |
||||
if (ret) { |
||||
/* retry again by closing and reopen the QSPI again */ |
||||
ret = mbox_qspi_close(); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, |
||||
MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
/* HPS will directly control the QSPI controller, no longer mailbox */ |
||||
resp_buf_len = 1; |
||||
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT, |
||||
0, NULL, 0, (u32 *)&resp_buf_len, |
||||
(u32 *)&resp_buf); |
||||
if (ret) |
||||
goto error; |
||||
|
||||
/* We are getting QSPI ref clock and set into sysmgr boot register */ |
||||
printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); |
||||
writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0); |
||||
|
||||
return 0; |
||||
|
||||
error: |
||||
mbox_qspi_close(); |
||||
|
||||
return ret; |
||||
} |
||||
#endif /* CONFIG_CADENCE_QSPI */ |
||||
|
||||
int mbox_reset_cold(void) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT, |
||||
0, NULL, 0, 0, NULL); |
||||
if (ret) { |
||||
/* mailbox sent failure, wait for watchdog to kick in */ |
||||
hang(); |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, |
||||
u8 urgent, u32 *resp_buf_len, u32 *resp_buf) |
||||
{ |
||||
return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, |
||||
resp_buf_len, resp_buf); |
||||
} |
||||
|
||||
int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, |
||||
u32 *arg, u8 urgent, u32 *resp_buf_len, |
||||
u32 *resp_buf) |
||||
{ |
||||
return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent, |
||||
resp_buf_len, resp_buf); |
||||
} |
||||
|
||||
int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg) |
||||
{ |
||||
return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); |
||||
} |
||||
|
||||
int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, |
||||
u32 *arg) |
||||
{ |
||||
return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg); |
||||
} |
||||
|
||||
int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len) |
||||
{ |
||||
return __mbox_rcv_resp(resp_buf, resp_buf_max_len); |
||||
} |
||||
|
||||
int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len) |
||||
{ |
||||
return __mbox_rcv_resp(resp_buf, resp_buf_max_len); |
||||
} |
@ -0,0 +1,133 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <altera.h> |
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <miiphy.h> |
||||
#include <netdev.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <asm/arch/misc.h> |
||||
#include <asm/pl310.h> |
||||
#include <linux/libfdt.h> |
||||
|
||||
#include <dt-bindings/reset/altr,rst-mgr-s10.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
/*
|
||||
* DesignWare Ethernet initialization |
||||
*/ |
||||
#ifdef CONFIG_ETH_DESIGNWARE |
||||
|
||||
static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) |
||||
{ |
||||
u32 modereg; |
||||
|
||||
if (!phymode) |
||||
return -EINVAL; |
||||
|
||||
if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) |
||||
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; |
||||
else if (!strcmp(phymode, "rgmii")) |
||||
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; |
||||
else if (!strcmp(phymode, "rmii")) |
||||
modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; |
||||
else |
||||
return -EINVAL; |
||||
|
||||
clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, |
||||
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, |
||||
modereg); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int socfpga_set_phymode(void) |
||||
{ |
||||
const void *fdt = gd->fdt_blob; |
||||
struct fdtdec_phandle_args args; |
||||
const char *phy_mode; |
||||
u32 gmac_index; |
||||
int nodes[2]; /* Max. 3 GMACs */ |
||||
int ret, count; |
||||
int i, node; |
||||
|
||||
count = fdtdec_find_aliases_for_id(fdt, "ethernet", |
||||
COMPAT_ALTERA_SOCFPGA_DWMAC, |
||||
nodes, ARRAY_SIZE(nodes)); |
||||
for (i = 0; i < count; i++) { |
||||
node = nodes[i]; |
||||
if (node <= 0) |
||||
continue; |
||||
|
||||
ret = fdtdec_parse_phandle_with_args(fdt, node, "resets", |
||||
"#reset-cells", 1, 0, |
||||
&args); |
||||
if (ret || args.args_count != 1) { |
||||
debug("GMAC%i: Failed to parse DT 'resets'!\n", i); |
||||
continue; |
||||
} |
||||
|
||||
gmac_index = args.args[0] - EMAC0_RESET; |
||||
|
||||
phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); |
||||
ret = socfpga_phymode_setup(gmac_index, phy_mode); |
||||
if (ret) { |
||||
debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); |
||||
continue; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#else |
||||
static int socfpga_set_phymode(void) |
||||
{ |
||||
return 0; |
||||
}; |
||||
#endif |
||||
|
||||
/*
|
||||
* Print CPU information |
||||
*/ |
||||
#if defined(CONFIG_DISPLAY_CPUINFO) |
||||
int print_cpuinfo(void) |
||||
{ |
||||
puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n"); |
||||
|
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ARCH_MISC_INIT |
||||
int arch_misc_init(void) |
||||
{ |
||||
char qspi_string[13]; |
||||
|
||||
sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz()); |
||||
env_set("qspi_clock", qspi_string); |
||||
|
||||
socfpga_set_phymode(); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
int arch_early_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void do_bridge_reset(int enable) |
||||
{ |
||||
socfpga_bridges_reset(enable); |
||||
} |
@ -0,0 +1,71 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/armv8/mmu.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct mm_region socfpga_stratix10_mem_map[] = { |
||||
{ |
||||
/* MEM 2GB*/ |
||||
.virt = 0x0UL, |
||||
.phys = 0x0UL, |
||||
.size = 0x80000000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
||||
PTE_BLOCK_INNER_SHARE, |
||||
}, { |
||||
/* FPGA 1.5GB */ |
||||
.virt = 0x80000000UL, |
||||
.phys = 0x80000000UL, |
||||
.size = 0x60000000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
||||
PTE_BLOCK_NON_SHARE | |
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
||||
}, { |
||||
/* DEVICE 142MB */ |
||||
.virt = 0xF7000000UL, |
||||
.phys = 0xF7000000UL, |
||||
.size = 0x08E00000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
||||
PTE_BLOCK_NON_SHARE | |
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
||||
}, { |
||||
/* OCRAM 1MB but available 256KB */ |
||||
.virt = 0xFFE00000UL, |
||||
.phys = 0xFFE00000UL, |
||||
.size = 0x00100000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
||||
PTE_BLOCK_INNER_SHARE, |
||||
}, { |
||||
/* DEVICE 32KB */ |
||||
.virt = 0xFFFC0000UL, |
||||
.phys = 0xFFFC0000UL, |
||||
.size = 0x00008000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
||||
PTE_BLOCK_NON_SHARE | |
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
||||
}, { |
||||
/* MEM 124GB */ |
||||
.virt = 0x0100000000UL, |
||||
.phys = 0x0100000000UL, |
||||
.size = 0x1F00000000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
||||
PTE_BLOCK_INNER_SHARE, |
||||
}, { |
||||
/* DEVICE 4GB */ |
||||
.virt = 0x2000000000UL, |
||||
.phys = 0x2000000000UL, |
||||
.size = 0x0100000000UL, |
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
||||
PTE_BLOCK_NON_SHARE | |
||||
PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
||||
}, { |
||||
/* List terminator */ |
||||
}, |
||||
}; |
||||
|
||||
struct mm_region *mem_map = socfpga_stratix10_mem_map; |
@ -0,0 +1,104 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com> |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/pl310.h> |
||||
#include <asm/u-boot.h> |
||||
#include <asm/utils.h> |
||||
#include <image.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <spl.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <asm/arch/freeze_controller.h> |
||||
#include <asm/arch/clock_manager.h> |
||||
#include <asm/arch/scan_manager.h> |
||||
#include <asm/arch/sdram.h> |
||||
#include <asm/arch/scu.h> |
||||
#include <asm/arch/nic301.h> |
||||
#include <asm/sections.h> |
||||
#include <fdtdec.h> |
||||
#include <watchdog.h> |
||||
#include <asm/arch/pinmux.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static const struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
u32 spl_boot_device(void) |
||||
{ |
||||
const u32 bsel = readl(&sysmgr_regs->bootinfo); |
||||
|
||||
switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { |
||||
case 0x1: /* FPGA (HPS2FPGA Bridge) */ |
||||
return BOOT_DEVICE_RAM; |
||||
case 0x2: /* NAND Flash (1.8V) */ |
||||
case 0x3: /* NAND Flash (3.0V) */ |
||||
socfpga_per_reset(SOCFPGA_RESET(NAND), 0); |
||||
return BOOT_DEVICE_NAND; |
||||
case 0x4: /* SD/MMC External Transceiver (1.8V) */ |
||||
case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ |
||||
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); |
||||
socfpga_per_reset(SOCFPGA_RESET(DMA), 0); |
||||
return BOOT_DEVICE_MMC1; |
||||
case 0x6: /* QSPI Flash (1.8V) */ |
||||
case 0x7: /* QSPI Flash (3.0V) */ |
||||
socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); |
||||
return BOOT_DEVICE_SPI; |
||||
default: |
||||
printf("Invalid boot device (bsel=%08x)!\n", bsel); |
||||
hang(); |
||||
} |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT |
||||
u32 spl_boot_mode(const u32 boot_device) |
||||
{ |
||||
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) |
||||
return MMCSD_MODE_FS; |
||||
#else |
||||
return MMCSD_MODE_RAW; |
||||
#endif |
||||
} |
||||
#endif |
||||
|
||||
void spl_board_init(void) |
||||
{ |
||||
/* configuring the clock based on handoff */ |
||||
cm_basic_init(gd->fdt_blob); |
||||
WATCHDOG_RESET(); |
||||
|
||||
config_dedicated_pins(gd->fdt_blob); |
||||
WATCHDOG_RESET(); |
||||
|
||||
/* Release UART from reset */ |
||||
socfpga_reset_uart(0); |
||||
|
||||
/* enable console uart printing */ |
||||
preloader_console_init(); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
/*
|
||||
* Configure Clock Manager to use intosc clock instead external osc to |
||||
* ensure success watchdog operation. We do it as early as possible. |
||||
*/ |
||||
cm_use_intosc(); |
||||
|
||||
socfpga_watchdog_disable(); |
||||
|
||||
arch_early_init_r(); |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
/* release osc1 watchdog timer 0 from reset */ |
||||
socfpga_reset_deassert_osc1wd0(); |
||||
|
||||
/* reconfigure and enable the watchdog */ |
||||
hw_watchdog_init(); |
||||
WATCHDOG_RESET(); |
||||
#endif /* CONFIG_HW_WATCHDOG */ |
||||
} |
@ -0,0 +1,200 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/u-boot.h> |
||||
#include <asm/utils.h> |
||||
#include <common.h> |
||||
#include <debug_uart.h> |
||||
#include <image.h> |
||||
#include <spl.h> |
||||
#include <asm/arch/clock_manager.h> |
||||
#include <asm/arch/firewall_s10.h> |
||||
#include <asm/arch/mailbox_s10.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
#include <asm/arch/sdram_s10.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <watchdog.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct socfpga_system_manager *sysmgr_regs = |
||||
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
u32 spl_boot_device(void) |
||||
{ |
||||
/* TODO: Get from SDM or handoff */ |
||||
return BOOT_DEVICE_MMC1; |
||||
} |
||||
|
||||
#ifdef CONFIG_SPL_MMC_SUPPORT |
||||
u32 spl_boot_mode(const u32 boot_device) |
||||
{ |
||||
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) |
||||
return MMCSD_MODE_FS; |
||||
#else |
||||
return MMCSD_MODE_RAW; |
||||
#endif |
||||
} |
||||
#endif |
||||
|
||||
void spl_disable_firewall_l4_per(void) |
||||
{ |
||||
const struct socfpga_firwall_l4_per *firwall_l4_per_base = |
||||
(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; |
||||
u32 i; |
||||
const u32 *addr[] = { |
||||
&firwall_l4_per_base->nand, |
||||
&firwall_l4_per_base->nand_data, |
||||
&firwall_l4_per_base->usb0, |
||||
&firwall_l4_per_base->usb1, |
||||
&firwall_l4_per_base->spim0, |
||||
&firwall_l4_per_base->spim1, |
||||
&firwall_l4_per_base->emac0, |
||||
&firwall_l4_per_base->emac1, |
||||
&firwall_l4_per_base->emac2, |
||||
&firwall_l4_per_base->sdmmc, |
||||
&firwall_l4_per_base->gpio0, |
||||
&firwall_l4_per_base->gpio1, |
||||
&firwall_l4_per_base->i2c0, |
||||
&firwall_l4_per_base->i2c1, |
||||
&firwall_l4_per_base->i2c2, |
||||
&firwall_l4_per_base->i2c3, |
||||
&firwall_l4_per_base->i2c4, |
||||
&firwall_l4_per_base->timer0, |
||||
&firwall_l4_per_base->timer1, |
||||
&firwall_l4_per_base->uart0, |
||||
&firwall_l4_per_base->uart1 |
||||
}; |
||||
|
||||
/*
|
||||
* The following lines of code will enable non-secure access |
||||
* to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This |
||||
* is needed as most OS run in non-secure mode. Thus we need to |
||||
* enable non-secure access to these peripherals in order for the |
||||
* OS to use these peripherals. |
||||
*/ |
||||
for (i = 0; i < ARRAY_SIZE(addr); i++) |
||||
writel(FIREWALL_L4_DISABLE_ALL, addr[i]); |
||||
} |
||||
|
||||
void spl_disable_firewall_l4_sys(void) |
||||
{ |
||||
const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = |
||||
(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; |
||||
u32 i; |
||||
const u32 *addr[] = { |
||||
&firwall_l4_sys_base->dma_ecc, |
||||
&firwall_l4_sys_base->emac0rx_ecc, |
||||
&firwall_l4_sys_base->emac0tx_ecc, |
||||
&firwall_l4_sys_base->emac1rx_ecc, |
||||
&firwall_l4_sys_base->emac1tx_ecc, |
||||
&firwall_l4_sys_base->emac2rx_ecc, |
||||
&firwall_l4_sys_base->emac2tx_ecc, |
||||
&firwall_l4_sys_base->nand_ecc, |
||||
&firwall_l4_sys_base->nand_read_ecc, |
||||
&firwall_l4_sys_base->nand_write_ecc, |
||||
&firwall_l4_sys_base->ocram_ecc, |
||||
&firwall_l4_sys_base->sdmmc_ecc, |
||||
&firwall_l4_sys_base->usb0_ecc, |
||||
&firwall_l4_sys_base->usb1_ecc, |
||||
&firwall_l4_sys_base->clock_manager, |
||||
&firwall_l4_sys_base->io_manager, |
||||
&firwall_l4_sys_base->reset_manager, |
||||
&firwall_l4_sys_base->system_manager, |
||||
&firwall_l4_sys_base->watchdog0, |
||||
&firwall_l4_sys_base->watchdog1, |
||||
&firwall_l4_sys_base->watchdog2, |
||||
&firwall_l4_sys_base->watchdog3 |
||||
}; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(addr); i++) |
||||
writel(FIREWALL_L4_DISABLE_ALL, addr[i]); |
||||
} |
||||
|
||||
void board_init_f(ulong dummy) |
||||
{ |
||||
const struct cm_config *cm_default_cfg = cm_get_default_config(); |
||||
int ret; |
||||
|
||||
#ifdef CONFIG_HW_WATCHDOG |
||||
/* Ensure watchdog is paused when debugging is happening */ |
||||
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); |
||||
|
||||
/* Enable watchdog before initializing the HW */ |
||||
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); |
||||
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); |
||||
hw_watchdog_init(); |
||||
#endif |
||||
|
||||
/* ensure all processors are not released prior Linux boot */ |
||||
writeq(0, CPU_RELEASE_ADDR); |
||||
|
||||
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); |
||||
timer_init(); |
||||
|
||||
populate_sysmgr_pinmux(); |
||||
|
||||
/* configuring the HPS clocks */ |
||||
cm_basic_init(cm_default_cfg); |
||||
|
||||
#ifdef CONFIG_DEBUG_UART |
||||
socfpga_per_reset(SOCFPGA_RESET(UART0), 0); |
||||
debug_uart_init(); |
||||
#endif |
||||
ret = spl_early_init(); |
||||
if (ret) { |
||||
debug("spl_early_init() failed: %d\n", ret); |
||||
hang(); |
||||
} |
||||
|
||||
preloader_console_init(); |
||||
cm_print_clock_quick_summary(); |
||||
|
||||
/* enable non-secure interface to DMA330 DMA and peripherals */ |
||||
writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); |
||||
writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); |
||||
|
||||
spl_disable_firewall_l4_per(); |
||||
|
||||
spl_disable_firewall_l4_sys(); |
||||
|
||||
/* disable lwsocf2fpga and soc2fpga bridge security */ |
||||
writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); |
||||
writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); |
||||
|
||||
/* disable SMMU security */ |
||||
writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); |
||||
|
||||
/* disable ocram security at CCU for non secure access */ |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), |
||||
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), |
||||
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); |
||||
|
||||
debug("DDR: Initializing Hard Memory Controller\n"); |
||||
if (sdram_mmr_init_full(0)) { |
||||
puts("DDR: Initialization failed.\n"); |
||||
hang(); |
||||
} |
||||
|
||||
gd->ram_size = sdram_calculate_size(); |
||||
printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); |
||||
|
||||
/* Sanity check ensure correct SDRAM size specified */ |
||||
debug("DDR: Running SDRAM size sanity check\n"); |
||||
if (get_ram_size(0, gd->ram_size) != gd->ram_size) { |
||||
puts("DDR: SDRAM size check failed!\n"); |
||||
hang(); |
||||
} |
||||
debug("DDR: SDRAM size check passed!\n"); |
||||
|
||||
mbox_init(); |
||||
|
||||
#ifdef CONFIG_CADENCE_QSPI |
||||
mbox_qspi_open(); |
||||
#endif |
||||
} |
@ -0,0 +1,26 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/timer.h> |
||||
|
||||
/*
|
||||
* Timer initialization |
||||
*/ |
||||
int timer_init(void) |
||||
{ |
||||
int enable = 0x3; /* timer enable + output signal masked */ |
||||
int loadval = ~0; |
||||
|
||||
/* enable system counter */ |
||||
writel(enable, SOCFPGA_GTIMER_SEC_ADDRESS); |
||||
/* enable processor pysical counter */ |
||||
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); |
||||
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,7 @@ |
||||
SOCFPGA BOARD |
||||
M: Chin-Liang See <chin.liang.see@intel.com> |
||||
M: Dinh Nguyen <dinh.nguyen@intel.com> |
||||
S: Maintained |
||||
F: board/altera/stratix10-socdk/ |
||||
F: include/configs/socfpga_stratix10_socdk.h |
||||
F: configs/socfpga_stratix10_defconfig |
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
|
||||
obj-y := socfpga.o
|
@ -0,0 +1,7 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
@ -0,0 +1,56 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_SOCFPGA=y |
||||
CONFIG_SYS_TEXT_BASE=0x1000 |
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000 |
||||
CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y |
||||
CONFIG_SPL=y |
||||
CONFIG_IDENT_STRING="socfpga_stratix10" |
||||
CONFIG_SPL_FAT_SUPPORT=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" |
||||
CONFIG_BOOTDELAY=5 |
||||
CONFIG_SPL_SPI_LOAD=y |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " |
||||
CONFIG_CMD_MEMTEST=y |
||||
# CONFIG_CMD_FLASH is not set |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_SPI=y |
||||
CONFIG_CMD_USB=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
CONFIG_NET_RANDOM_ETHADDR=y |
||||
CONFIG_SPL_DM=y |
||||
CONFIG_SPL_DM_SEQ_ALIAS=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_DWAPB_GPIO=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_SYS_I2C_DW=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_MMC_DW=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SPI_FLASH_SPANSION=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_PHY_MICREL_KSZ90X1=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_ETH_DESIGNWARE=y |
||||
CONFIG_DM_RESET=y |
||||
CONFIG_SPI=y |
||||
CONFIG_CADENCE_QSPI=y |
||||
CONFIG_DESIGNWARE_SPI=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_USB_DWC2=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_USE_TINY_PRINTF=y |
@ -0,0 +1,388 @@ |
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <div64.h> |
||||
#include <asm/io.h> |
||||
#include <wait_bit.h> |
||||
#include <asm/arch/firewall_s10.h> |
||||
#include <asm/arch/sdram_s10.h> |
||||
#include <asm/arch/system_manager.h> |
||||
#include <asm/arch/reset_manager.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static const struct socfpga_system_manager *sysmgr_regs = |
||||
(void *)SOCFPGA_SYSMGR_ADDRESS; |
||||
|
||||
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) |
||||
|
||||
/* The followring are the supported configurations */ |
||||
u32 ddr_config[] = { |
||||
/* DDR_CONFIG(Address order,Bank,Column,Row) */ |
||||
/* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */ |
||||
DDR_CONFIG(0, 3, 10, 12), |
||||
DDR_CONFIG(0, 3, 9, 13), |
||||
DDR_CONFIG(0, 3, 10, 13), |
||||
DDR_CONFIG(0, 3, 9, 14), |
||||
DDR_CONFIG(0, 3, 10, 14), |
||||
DDR_CONFIG(0, 3, 10, 15), |
||||
DDR_CONFIG(0, 3, 11, 14), |
||||
DDR_CONFIG(0, 3, 11, 15), |
||||
DDR_CONFIG(0, 3, 10, 16), |
||||
DDR_CONFIG(0, 3, 11, 16), |
||||
DDR_CONFIG(0, 3, 12, 15), /* 0xa */ |
||||
/* List for DDR4 only (pinout order > chip, bank, row, column) */ |
||||
DDR_CONFIG(1, 3, 10, 14), |
||||
DDR_CONFIG(1, 4, 10, 14), |
||||
DDR_CONFIG(1, 3, 10, 15), |
||||
DDR_CONFIG(1, 4, 10, 15), |
||||
DDR_CONFIG(1, 3, 10, 16), |
||||
DDR_CONFIG(1, 4, 10, 16), |
||||
DDR_CONFIG(1, 3, 10, 17), |
||||
DDR_CONFIG(1, 4, 10, 17), |
||||
}; |
||||
|
||||
static u32 hmc_readl(u32 reg) |
||||
{ |
||||
return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg))); |
||||
} |
||||
|
||||
static u32 hmc_ecc_readl(u32 reg) |
||||
{ |
||||
return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); |
||||
} |
||||
|
||||
static u32 hmc_ecc_writel(u32 data, u32 reg) |
||||
{ |
||||
return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); |
||||
} |
||||
|
||||
static u32 ddr_sch_writel(u32 data, u32 reg) |
||||
{ |
||||
return writel(data, |
||||
(void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg)); |
||||
} |
||||
|
||||
int match_ddr_conf(u32 ddr_conf) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ddr_config); i++) { |
||||
if (ddr_conf == ddr_config[i]) |
||||
return i; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int emif_clear(void) |
||||
{ |
||||
hmc_ecc_writel(0, RSTHANDSHAKECTRL); |
||||
|
||||
return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + |
||||
RSTHANDSHAKESTAT), |
||||
DDR_HMC_RSTHANDSHAKE_MASK, |
||||
false, 1000, false); |
||||
} |
||||
|
||||
static int emif_reset(void) |
||||
{ |
||||
u32 c2s, s2c, ret; |
||||
|
||||
c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; |
||||
s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; |
||||
|
||||
debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", |
||||
c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1), |
||||
hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS)); |
||||
|
||||
if (s2c && emif_clear()) { |
||||
printf("DDR: emif_clear() failed\n"); |
||||
return -1; |
||||
} |
||||
|
||||
debug("DDR: Triggerring emif reset\n"); |
||||
hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); |
||||
|
||||
/* if seq2core[3] = 0, we are good */ |
||||
ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + |
||||
RSTHANDSHAKESTAT), |
||||
DDR_HMC_SEQ2CORE_INT_RESP_MASK, |
||||
false, 1000, false); |
||||
if (ret) { |
||||
printf("DDR: failed to get ack from EMIF\n"); |
||||
return ret; |
||||
} |
||||
|
||||
ret = emif_clear(); |
||||
if (ret) { |
||||
printf("DDR: emif_clear() failed\n"); |
||||
return ret; |
||||
} |
||||
|
||||
debug("DDR: %s triggered successly\n", __func__); |
||||
return 0; |
||||
} |
||||
|
||||
static int poll_hmc_clock_status(void) |
||||
{ |
||||
return wait_for_bit_le32(&sysmgr_regs->hmc_clk, |
||||
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); |
||||
} |
||||
|
||||
/**
|
||||
* sdram_mmr_init_full() - Function to initialize SDRAM MMR |
||||
* |
||||
* Initialize the SDRAM MMR. |
||||
*/ |
||||
int sdram_mmr_init_full(unsigned int unused) |
||||
{ |
||||
u32 update_value, io48_value, ddrioctl; |
||||
u32 i; |
||||
int ret; |
||||
|
||||
/* Enable access to DDR from CPU master */ |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E), |
||||
CCU_ADBASE_DI_MASK); |
||||
|
||||
/* Enable access to DDR from IO master */ |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D), |
||||
CCU_ADBASE_DI_MASK); |
||||
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), |
||||
CCU_ADBASE_DI_MASK); |
||||
|
||||
/* this enables nonsecure access to DDR */ |
||||
/* mpuregion0addr_limit */ |
||||
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); |
||||
FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); |
||||
|
||||
/* nonmpuregion0addr_limit */ |
||||
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, |
||||
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); |
||||
FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT); |
||||
|
||||
/* Enable mpuregion0enable and nonmpuregion0enable */ |
||||
FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, |
||||
FW_MPU_DDR_SCR_EN_SET); |
||||
|
||||
/* Ensure HMC clock is running */ |
||||
if (poll_hmc_clock_status()) { |
||||
puts("DDR: Error as HMC clock not running\n"); |
||||
return -1; |
||||
} |
||||
|
||||
/* release DDR scheduler from reset */ |
||||
socfpga_per_reset(SOCFPGA_RESET(SDR), 0); |
||||
|
||||
/* Try 3 times to do a calibration */ |
||||
for (i = 0; i < 3; i++) { |
||||
ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + |
||||
DDRCALSTAT), |
||||
DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, |
||||
false); |
||||
if (!ret) |
||||
break; |
||||
|
||||
emif_reset(); |
||||
} |
||||
|
||||
if (ret) { |
||||
puts("DDR: Error as SDRAM calibration failed\n"); |
||||
return -1; |
||||
} |
||||
debug("DDR: Calibration success\n"); |
||||
|
||||
u32 ctrlcfg0 = hmc_readl(CTRLCFG0); |
||||
u32 ctrlcfg1 = hmc_readl(CTRLCFG1); |
||||
u32 dramaddrw = hmc_readl(DRAMADDRW); |
||||
u32 dramtim0 = hmc_readl(DRAMTIMING0); |
||||
u32 caltim0 = hmc_readl(CALTIMING0); |
||||
u32 caltim1 = hmc_readl(CALTIMING1); |
||||
u32 caltim2 = hmc_readl(CALTIMING2); |
||||
u32 caltim3 = hmc_readl(CALTIMING3); |
||||
u32 caltim4 = hmc_readl(CALTIMING4); |
||||
u32 caltim9 = hmc_readl(CALTIMING9); |
||||
|
||||
/*
|
||||
* Configure the DDR IO size [0xFFCFB008] |
||||
* niosreserve0: Used to indicate DDR width & |
||||
* bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) |
||||
* bit[8] = 1 if user-mode OCT is present |
||||
* bit[9] = 1 if warm reset compiled into EMIF Cal Code |
||||
* bit[10] = 1 if warm reset is on during generation in EMIF Cal |
||||
* niosreserve1: IP ADCDS version encoded as 16 bit value |
||||
* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, |
||||
* 3=EAP, 4-6 are reserved) |
||||
* bit[5:3] = Service Pack # (e.g. 1) |
||||
* bit[9:6] = Minor Release # |
||||
* bit[14:10] = Major Release # |
||||
*/ |
||||
update_value = hmc_readl(NIOSRESERVED0); |
||||
hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL); |
||||
ddrioctl = hmc_ecc_readl(DDRIOCTRL); |
||||
|
||||
/* enable HPS interface to HMC */ |
||||
hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); |
||||
|
||||
/* Set the DDR Configuration */ |
||||
io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1), |
||||
(DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + |
||||
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)), |
||||
DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw), |
||||
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw)); |
||||
|
||||
update_value = match_ddr_conf(io48_value); |
||||
if (update_value) |
||||
ddr_sch_writel(update_value, DDR_SCH_DDRCONF); |
||||
|
||||
/* Configure HMC dramaddrw */ |
||||
hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH); |
||||
|
||||
/*
|
||||
* Configure DDR timing |
||||
* RDTOMISS = tRTP + tRP + tRCD - BL/2 |
||||
* WRTOMISS = WL + tWR + tRP + tRCD and |
||||
* WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so... |
||||
* First part of equation is in memory clock units so divide by 2 |
||||
* for HMC clock units. 1066MHz is close to 1ns so use 15 directly. |
||||
* WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD |
||||
*/ |
||||
u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0); |
||||
|
||||
update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) + |
||||
CALTIMING4_CFG_PCH_TO_VALID(caltim4) + |
||||
CALTIMING0_CFG_ACT_TO_RDWR(caltim0) - |
||||
(burst_len >> 2); |
||||
io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR + |
||||
(burst_len >> 1)) >> 1) - |
||||
/* Up to here was in memory cycles so divide by 2 */ |
||||
CALTIMING1_CFG_RD_TO_WR(caltim1) + |
||||
CALTIMING0_CFG_ACT_TO_RDWR(caltim0) + |
||||
CALTIMING4_CFG_PCH_TO_VALID(caltim4)); |
||||
|
||||
ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << |
||||
DDR_SCH_DDRTIMING_ACTTOACT_OFF) | |
||||
(update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | |
||||
(io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) | |
||||
((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) | |
||||
(CALTIMING1_CFG_RD_TO_WR(caltim1) << |
||||
DDR_SCH_DDRTIMING_RDTOWR_OFF) | |
||||
(CALTIMING3_CFG_WR_TO_RD(caltim3) << |
||||
DDR_SCH_DDRTIMING_WRTORD_OFF) | |
||||
(((ddrioctl == 1) ? 1 : 0) << |
||||
DDR_SCH_DDRTIMING_BWRATIO_OFF)), |
||||
DDR_SCH_DDRTIMING); |
||||
|
||||
/* Configure DDR mode [precharge = 0] */ |
||||
ddr_sch_writel(((ddrioctl ? 0 : 1) << |
||||
DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF), |
||||
DDR_SCH_DDRMODE); |
||||
|
||||
/* Configure the read latency */ |
||||
ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + |
||||
DDR_READ_LATENCY_DELAY, |
||||
DDR_SCH_READ_LATENCY); |
||||
|
||||
/*
|
||||
* Configuring timing values concerning activate commands |
||||
* [FAWBANK alway 1 because always 4 bank DDR] |
||||
*/ |
||||
ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << |
||||
DDR_SCH_ACTIVATE_RRD_OFF) | |
||||
(CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) << |
||||
DDR_SCH_ACTIVATE_FAW_OFF) | |
||||
(DDR_ACTIVATE_FAWBANK << |
||||
DDR_SCH_ACTIVATE_FAWBANK_OFF)), |
||||
DDR_SCH_ACTIVATE); |
||||
|
||||
/*
|
||||
* Configuring timing values concerning device to device data bus |
||||
* ownership change |
||||
*/ |
||||
ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << |
||||
DDR_SCH_DEVTODEV_BUSRDTORD_OFF) | |
||||
(CALTIMING1_CFG_RD_TO_WR_DC(caltim1) << |
||||
DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) | |
||||
(CALTIMING3_CFG_WR_TO_RD_DC(caltim3) << |
||||
DDR_SCH_DEVTODEV_BUSWRTORD_OFF)), |
||||
DDR_SCH_DEVTODEV); |
||||
|
||||
/* assigning the SDRAM size */ |
||||
unsigned long long size = sdram_calculate_size(); |
||||
/* If the size is invalid, use default Config size */ |
||||
if (size <= 0) |
||||
gd->ram_size = PHYS_SDRAM_1_SIZE; |
||||
else |
||||
gd->ram_size = size; |
||||
|
||||
/* Enable or disable the SDRAM ECC */ |
||||
if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { |
||||
setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, |
||||
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
DDR_HMC_ECCCTL_CNT_RST_SET_MSK | |
||||
DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, |
||||
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); |
||||
setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, |
||||
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | |
||||
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} else { |
||||
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, |
||||
(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | |
||||
DDR_HMC_ECCCTL_CNT_RST_SET_MSK | |
||||
DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); |
||||
clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, |
||||
(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | |
||||
DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); |
||||
} |
||||
|
||||
debug("DDR: HMC init success\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* sdram_calculate_size() - Calculate SDRAM size |
||||
* |
||||
* Calculate SDRAM device size based on SDRAM controller parameters. |
||||
* Size is specified in bytes. |
||||
*/ |
||||
unsigned long sdram_calculate_size(void) |
||||
{ |
||||
u32 dramaddrw = hmc_readl(DRAMADDRW); |
||||
|
||||
u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + |
||||
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + |
||||
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + |
||||
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + |
||||
DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); |
||||
|
||||
size *= (2 << (hmc_ecc_readl(DDRIOCTRL) & |
||||
DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); |
||||
|
||||
return size; |
||||
} |
@ -0,0 +1,222 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
* |
||||
* Copyright (C) 2017-2018 Intel Corporation <www.intel.com> |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ |
||||
#define __CONFIG_SOCFGPA_STRATIX10_H__ |
||||
|
||||
#include <asm/arch/base_addr_s10.h> |
||||
#include <asm/arch/handoff_s10.h> |
||||
|
||||
/*
|
||||
* U-Boot general configurations |
||||
*/ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
||||
#define CONFIG_LOADADDR 0x2000000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_REMAKE_ELF |
||||
/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ |
||||
#define CPU_RELEASE_ADDR 0xFFD12210 |
||||
#define CONFIG_SYS_CACHELINE_SIZE 64 |
||||
#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ |
||||
|
||||
/*
|
||||
* U-Boot console configurations |
||||
*/ |
||||
#define CONFIG_SYS_MAXARGS 64 |
||||
#define CONFIG_SYS_CBSIZE 2048 |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
/* Extend size of kernel image for uncompression */ |
||||
#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) |
||||
|
||||
/*
|
||||
* U-Boot run time memory configurations |
||||
*/ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ |
||||
+ CONFIG_SYS_INIT_RAM_SIZE \
|
||||
- S10_HANDOFF_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) |
||||
#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) |
||||
|
||||
/*
|
||||
* U-Boot environment configurations |
||||
*/ |
||||
#define CONFIG_ENV_SIZE 0x1000 |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ |
||||
#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ |
||||
|
||||
/*
|
||||
* QSPI support |
||||
*/ |
||||
#ifdef CONFIG_CADENCE_QSPI |
||||
/* Enable it if you want to use dual-stacked mode */ |
||||
#undef CONFIG_SF_DUAL_FLASH |
||||
/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ |
||||
|
||||
/* Flash device info */ |
||||
#define CONFIG_SF_DEFAULT_SPEED (50000000) |
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD) |
||||
#define CONFIG_SF_DEFAULT_BUS 0 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
|
||||
/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ |
||||
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#undef CONFIG_ENV_OFFSET |
||||
#undef CONFIG_ENV_SIZE |
||||
#define CONFIG_ENV_OFFSET 0x710000 |
||||
#define CONFIG_ENV_SIZE (4 * 1024) |
||||
#define CONFIG_ENV_SECT_SIZE (4 * 1024) |
||||
#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" |
||||
#endif /* CONFIG_SPL_BUILD */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
unsigned int cm_get_qspi_controller_clk_hz(void); |
||||
#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() |
||||
#endif |
||||
|
||||
#endif /* CONFIG_CADENCE_QSPI */ |
||||
|
||||
/*
|
||||
* Boot arguments passed to the boot command. The value of |
||||
* CONFIG_BOOTARGS goes into the environment value "bootargs". |
||||
* Do note the value will override also the chosen node in FDT blob. |
||||
*/ |
||||
#define CONFIG_BOOTARGS "earlycon" |
||||
#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ |
||||
"run mmcboot" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"bootfile=Image\0" \
|
||||
"fdt_addr=8000000\0" \
|
||||
"fdtimage=socfpga_stratix10_socdk.dtb\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
|
||||
" root=${mmcroot} rw rootwait;" \
|
||||
"booti ${loadaddr} - ${fdt_addr}\0" \
|
||||
"mmcload=mmc rescan;" \
|
||||
"load mmc 0:1 ${loadaddr} ${bootfile};" \
|
||||
"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
|
||||
"linux_qspi_enable=if sf probe; then " \
|
||||
"echo Enabling QSPI at Linux DTB...;" \
|
||||
"fdt addr ${fdt_addr}; fdt resize;" \
|
||||
"fdt set /soc/spi@ff8d2000 status okay;" \
|
||||
"fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
|
||||
" ${qspi_clock}; fi; \0" \
|
||||
"scriptaddr=0x02100000\0" \
|
||||
"scriptfile=u-boot.scr\0" \
|
||||
"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
|
||||
"then source ${scriptaddr}; fi\0" |
||||
|
||||
/*
|
||||
* Generic Interrupt Controller Definitions |
||||
*/ |
||||
#define CONFIG_GICV2 |
||||
|
||||
/*
|
||||
* External memory configurations |
||||
*/ |
||||
#define PHYS_SDRAM_1 0x0 |
||||
#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) |
||||
#define CONFIG_SYS_SDRAM_BASE 0 |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define CONFIG_SYS_MEMTEST_START 0 |
||||
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 |
||||
|
||||
/*
|
||||
* SDRAM controller |
||||
*/ |
||||
#define CONFIG_ALTERA_SDRAM |
||||
|
||||
/*
|
||||
* Serial / UART configurations |
||||
*/ |
||||
#define CONFIG_SYS_NS16550_CLK 100000000 |
||||
#define CONFIG_SYS_NS16550_MEM32 |
||||
|
||||
/*
|
||||
* Timer & watchdog configurations |
||||
*/ |
||||
#define COUNTER_FREQUENCY 400000000 |
||||
|
||||
/*
|
||||
* SDMMC configurations |
||||
*/ |
||||
#ifdef CONFIG_CMD_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 |
||||
#endif |
||||
/*
|
||||
* Flash configurations |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
|
||||
/* Ethernet on SoC (EMAC) */ |
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_DW_ALTDESCRIPTOR |
||||
#define CONFIG_MII |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
/*
|
||||
* L4 Watchdog |
||||
*/ |
||||
#ifdef CONFIG_SPL_BUILD |
||||
#define CONFIG_HW_WATCHDOG |
||||
#define CONFIG_DESIGNWARE_WATCHDOG |
||||
#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
||||
#ifndef __ASSEMBLY__ |
||||
unsigned int cm_get_l4_sys_free_clk_hz(void); |
||||
#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) |
||||
#endif |
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 |
||||
#endif |
||||
|
||||
/*
|
||||
* SPL memory layout |
||||
* |
||||
* On chip RAM |
||||
* 0xFFE0_0000 ...... Start of OCRAM |
||||
* SPL code, rwdata |
||||
* empty space |
||||
* 0xFFEx_xxxx ...... Top of stack (grows down) |
||||
* 0xFFEy_yyyy ...... Global Data |
||||
* 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) |
||||
* 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) |
||||
* 0xFFE3_FFFF ...... End of OCRAM |
||||
* |
||||
* SDRAM |
||||
* 0x0000_0000 ...... Start of SDRAM_1 |
||||
* unused / empty space for image loading |
||||
* Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) |
||||
* Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) |
||||
* 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) |
||||
* |
||||
*/ |
||||
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR |
||||
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE |
||||
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR |
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ |
||||
#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ |
||||
- CONFIG_SPL_BSS_MAX_SIZE) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) |
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ |
||||
- CONFIG_SYS_SPL_MALLOC_SIZE) |
||||
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 |
||||
|
||||
/* SPL SDMMC boot support */ |
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue