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@ -27,6 +27,7 @@ |
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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/* Two MT48LC8M32B2 for 32 MB */ |
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/* #include "mt48lc8m32b2-6-7.h" */ |
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@ -98,6 +99,7 @@ long int initdram (int board_type) |
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{ |
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ulong dramsize = 0; |
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ulong dramsize2 = 0; |
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uint svr, pvr; |
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#ifndef CFG_RAMBOOT |
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ulong test1, test2; |
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@ -192,6 +194,23 @@ long int initdram (int board_type) |
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#endif /* CFG_RAMBOOT */ |
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/*
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* On MPC5200B we need to set the special configuration delay in the |
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM |
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: |
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* |
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* "The SDelay should be written to a value of 0x00000004. It is |
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* required to account for changes caused by normal wafer processing |
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* parameters." |
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*/ |
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svr = get_svr(); |
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pvr = get_pvr(); |
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if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) &&
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(PVR_MIN(pvr) == 4)) { |
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*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; |
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__asm__ volatile ("sync"); |
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} |
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return dramsize + dramsize2; |
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} |
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