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@ -1,5 +1,5 @@ |
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/*
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* (C) Copyright 2006-2007 |
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* (C) Copyright 2006-2008 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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@ -28,6 +28,10 @@ static int nand_ecc_pos[] = CFG_NAND_ECCPOS; |
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extern void board_nand_init(struct nand_chip *nand); |
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#if (CFG_NAND_PAGE_SIZE <= 512) |
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/*
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* NAND command for small page NAND devices (512) |
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*/ |
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static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) |
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{ |
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struct nand_chip *this = mtd->priv; |
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@ -65,6 +69,64 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 |
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return 0; |
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} |
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#else |
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/*
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* NAND command for large page NAND devices (2k) |
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*/ |
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static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) |
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{ |
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struct nand_chip *this = mtd->priv; |
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int page_offs = offs; |
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int page_addr = page + block * CFG_NAND_PAGE_COUNT; |
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if (this->dev_ready) |
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this->dev_ready(mtd); |
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else |
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CFG_NAND_READ_DELAY; |
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/* Emulate NAND_CMD_READOOB */ |
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if (cmd == NAND_CMD_READOOB) { |
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page_offs += CFG_NAND_PAGE_SIZE; |
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cmd = NAND_CMD_READ0; |
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} |
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/* Begin command latch cycle */ |
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this->hwcontrol(mtd, NAND_CTL_SETCLE); |
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this->write_byte(mtd, cmd); |
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/* Set ALE and clear CLE to start address cycle */ |
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this->hwcontrol(mtd, NAND_CTL_CLRCLE); |
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this->hwcontrol(mtd, NAND_CTL_SETALE); |
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/* Column address */ |
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this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */ |
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this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */ |
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/* Row address */ |
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this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */ |
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this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */ |
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#ifdef CFG_NAND_5_ADDR_CYCLE |
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/* One more address cycle for devices > 128MiB */ |
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this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */ |
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#endif |
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/* Latch in address */ |
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this->hwcontrol(mtd, NAND_CTL_CLRALE); |
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/* Begin command latch cycle */ |
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this->hwcontrol(mtd, NAND_CTL_SETCLE); |
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/* Write out the start read command */ |
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this->write_byte(mtd, NAND_CMD_READSTART); |
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/* End command latch cycle */ |
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this->hwcontrol(mtd, NAND_CTL_CLRCLE); |
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/*
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* Wait a while for the data to be ready |
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*/ |
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if (this->dev_ready) |
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this->dev_ready(mtd); |
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else |
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CFG_NAND_READ_DELAY; |
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return 0; |
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} |
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#endif |
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static int nand_is_bad_block(struct mtd_info *mtd, int block) |
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{ |
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