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@ -33,11 +33,11 @@ |
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mcr 15, 0, r0, c1, c0, 1 |
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/* reconfigure L2 cache aux control reg */ |
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mov r0, #0xC0 /* tag RAM */ |
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add r0, r0, #0x4 /* data RAM */ |
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orr r0, r0, #(1 << 24) /* disable write allocate delay */ |
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orr r0, r0, #(1 << 23) /* disable write allocate combine */ |
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orr r0, r0, #(1 << 22) /* disable write allocate */ |
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mov r0, #0xC0 /* tag RAM */ |
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add r0, r0, #0x4 /* data RAM */ |
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orr r0, r0, #(1 << 24) /* disable write allocate delay */ |
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orr r0, r0, #(1 << 23) /* disable write allocate combine */ |
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orr r0, r0, #(1 << 22) /* disable write allocate */ |
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cmp r3, #0x10 /* r3 contains the silicon rev */ |
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@ -157,7 +157,7 @@ |
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/* Switch peripheral to PLL 3 */ |
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ldr r0, =CCM_BASE_ADDR |
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ldr r1, =0x000010C0 |
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ldr r1, =0x000010C0 |
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str r1, [r0, #CLKCTL_CBCMR] |
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ldr r1, =0x13239145 |
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str r1, [r0, #CLKCTL_CBCDR] |
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@ -255,17 +255,17 @@ lowlevel_init: |
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str r1, [r0, #0x4] |
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#ifdef ENABLE_IMPRECISE_ABORT |
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mrs r1, spsr /* save old spsr */ |
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mrs r0, cpsr /* read out the cpsr */ |
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bic r0, r0, #0x100 /* clear the A bit */ |
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msr spsr, r0 /* update spsr */ |
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add lr, pc, #0x8 /* update lr */ |
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movs pc, lr /* update cpsr */ |
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mrs r1, spsr /* save old spsr */ |
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mrs r0, cpsr /* read out the cpsr */ |
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bic r0, r0, #0x100 /* clear the A bit */ |
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msr spsr, r0 /* update spsr */ |
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add lr, pc, #0x8 /* update lr */ |
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movs pc, lr /* update cpsr */ |
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nop |
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nop |
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nop |
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nop |
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msr spsr, r1 /* restore old spsr */ |
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msr spsr, r1 /* restore old spsr */ |
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#endif |
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init_l2cc |
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