Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>master
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/* |
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* Copyright (C) 2016 Marvell International Ltd. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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* https://spdx.org/licenses |
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*/ |
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#include "armada-8040.dtsi" /* include SoC device tree */ |
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/ { |
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model = "MACCHIATOBin-8040"; |
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compatible = "marvell,armada8040-mcbin", |
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"marvell,armada8040"; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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aliases { |
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i2c0 = &cpm_i2c0; |
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i2c1 = &cpm_i2c1; |
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spi0 = &cps_spi1; |
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gpio0 = &ap_gpio0; |
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gpio1 = &cpm_gpio0; |
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gpio2 = &cpm_gpio1; |
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}; |
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memory@00000000 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>; |
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}; |
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simple-bus { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg_usb3h0_vbus: usb3-vbus0 { |
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compatible = "regulator-fixed"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_xhci_vbus_pins>; |
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regulator-name = "reg-usb3h0-vbus"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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startup-delay-us = <500000>; |
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enable-active-high; |
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regulator-always-on; |
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regulator-boot-on; |
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gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ |
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}; |
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}; |
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}; |
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/* Accessible over the mini-USB CON9 connector on the main board */ |
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&uart0 { |
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status = "okay"; |
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}; |
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&ap_pinctl { |
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/* |
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* MPP Bus: |
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* eMMC [0-10] |
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* UART0 [11,19] |
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*/ |
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/* 0 1 2 3 4 5 6 7 8 9 */ |
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pin-func = < 1 1 1 1 1 1 1 1 1 1 |
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1 3 0 0 0 0 0 0 0 3 >; |
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}; |
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/* on-board eMMC */ |
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&ap_sdhci0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&ap_emmc_pins>; |
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bus-width= <8>; |
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status = "okay"; |
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}; |
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&cpm_pinctl { |
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/* |
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* MPP Bus: |
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* [0-31] = 0xff: Keep default CP0_shared_pins: |
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* [11] CLKOUT_MPP_11 (out) |
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* [23] LINK_RD_IN_CP2CP (in) |
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* [25] CLKOUT_MPP_25 (out) |
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* [29] AVS_FB_IN_CP2CP (in) |
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* [32,34] SMI |
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* [33] MSS power down |
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* [35-38] CP0 I2C1 and I2C0 |
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* [39] MSS CKE Enable |
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* [40,41] CP0 UART1 TX/RX |
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* [42,43] XSMI (controls two 10G phys) |
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* [47] USB VBUS EN |
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* [48] FAN PWM |
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* [49] 10G port 1 interrupt |
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* [50] 10G port 0 interrupt |
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* [51] 2.5G SFP TX fault |
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* [52] PCIe reset out |
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* [53] 2.5G SFP mode |
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* [54] 2.5G SFP LOS |
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* [55] Micro SD card detect |
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* [56-61] Micro SD |
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* [62] CP1 KR SFP FAULT |
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*/ |
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/* 0 1 2 3 4 5 6 7 8 9 */ |
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pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0 7 0xa 7 2 2 2 2 0xa |
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7 7 8 8 0 0 0 0 0 0 |
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0 0 0 0 0 0 0xe 0xe 0xe 0xe |
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0xe 0xe 0 >; |
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cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { |
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marvell,pins = < 47 >; |
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marvell,function = <0>; |
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}; |
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cpm_pcie_reset_pins: cpm-pcie-reset-pins { |
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marvell,pins = < 52 >; |
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marvell,function = <0>; |
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}; |
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}; |
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/* uSD slot */ |
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&cpm_sdhci0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_sdhci_pins>; |
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bus-width= <4>; |
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status = "okay"; |
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}; |
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/* PCIe x4 */ |
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&cpm_pcie0 { |
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num-lanes = <4>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_pcie_reset_pins>; |
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marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ |
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status = "okay"; |
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}; |
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&cpm_i2c0 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_i2c0_pins>; |
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status = "okay"; |
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clock-frequency = <100000>; |
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}; |
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&cpm_i2c1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cpm_i2c1_pins>; |
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status = "okay"; |
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clock-frequency = <100000>; |
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}; |
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&cpm_sata0 { |
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status = "okay"; |
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}; |
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&cpm_comphy { |
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/* |
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* CP0 Serdes Configuration: |
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* Lane 0: PCIe0 (x4) |
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* Lane 1: PCIe0 (x4) |
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* Lane 2: PCIe0 (x4) |
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* Lane 3: PCIe0 (x4) |
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* Lane 4: KR (10G) |
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* Lane 5: SATA1 |
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*/ |
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phy0 { |
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phy-type = <PHY_TYPE_PEX0>; |
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}; |
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phy1 { |
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phy-type = <PHY_TYPE_PEX0>; |
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}; |
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phy2 { |
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phy-type = <PHY_TYPE_PEX0>; |
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}; |
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phy3 { |
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phy-type = <PHY_TYPE_PEX0>; |
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}; |
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phy4 { |
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phy-type = <PHY_TYPE_KR>; |
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}; |
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phy5 { |
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phy-type = <PHY_TYPE_SATA1>; |
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}; |
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}; |
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&cps_sata0 { |
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status = "okay"; |
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}; |
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&cps_usb3_0 { |
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vbus-supply = <®_usb3h0_vbus>; |
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status = "okay"; |
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}; |
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&cps_utmi0 { |
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status = "okay"; |
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}; |
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&cps_pinctl { |
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/* |
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* MPP Bus: |
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* [0-5] TDM |
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* [6,7] CP1_UART 0 |
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* [8] CP1 10G SFP LOS |
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* [9] CP1 10G PHY RESET |
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* [10] CP1 10G SFP TX Disable |
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* [11] CP1 10G SFP Mode |
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* [12] SPI1 CS1n |
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* [13] SPI1 MISO (TDM and SPI ROM shared) |
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* [14] SPI1 CS0n |
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* [15] SPI1 MOSI (TDM and SPI ROM shared) |
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* [16] SPI1 CLK (TDM and SPI ROM shared) |
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* [24] CP1 2.5G SFP TX Disable |
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* [26] CP0 10G SFP TX Fault |
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* [27] CP0 10G SFP Mode |
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* [28] CP0 10G SFP LOS |
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* [29] CP0 10G SFP TX Disable |
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* [30] USB Over current indication |
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* [31] 10G Port 0 phy reset |
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* [32-62] = 0xff: Keep default CP1_shared_pins: |
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*/ |
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/* 0 1 2 3 4 5 6 7 8 9 */ |
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pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 |
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0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff |
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0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 |
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0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff |
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0xff 0xff 0xff>; |
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}; |
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&cps_spi1 { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&cps_spi1_pins>; |
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status = "okay"; |
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spi-flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <10000000>; |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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partition@0 { |
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label = "U-Boot"; |
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reg = <0 0x200000>; |
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}; |
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partition@400000 { |
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label = "Filesystem"; |
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reg = <0x200000 0xce0000>; |
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}; |
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}; |
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}; |
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}; |
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&cps_comphy { |
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/* |
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* CP1 Serdes Configuration: |
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* Lane 0: SGMII2 |
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* Lane 1: SATA 0 |
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* Lane 2: USB HOST 0 |
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* Lane 3: SATA1 |
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* Lane 4: KR (10G) |
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* Lane 5: SGMII3 |
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*/ |
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phy0 { |
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phy-type = <PHY_TYPE_SGMII2>; |
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phy-speed = <PHY_SPEED_1_25G>; |
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}; |
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phy1 { |
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phy-type = <PHY_TYPE_SATA0>; |
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}; |
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phy2 { |
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phy-type = <PHY_TYPE_USB3_HOST0>; |
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}; |
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phy3 { |
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phy-type = <PHY_TYPE_SATA1>; |
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}; |
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phy4 { |
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phy-type = <PHY_TYPE_KR>; |
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}; |
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phy5 { |
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phy-type = <PHY_TYPE_SGMII3>; |
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}; |
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}; |
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