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@ -92,6 +92,12 @@ static struct pci_device_id e1000_supported[] = { |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, |
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, |
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{} |
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}; |
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@ -340,7 +346,7 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) |
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return -E1000_ERR_SWFW_SYNC; |
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eecd = E1000_READ_REG(hw, EECD); |
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if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) { |
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if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { |
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/* Request EEPROM Access */ |
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if (hw->mac_type > e1000_82544) { |
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eecd |= E1000_EECD_REQ; |
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@ -391,10 +397,15 @@ int32_t e1000_acquire_eeprom(struct e1000_hw *hw) |
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static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
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{ |
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struct e1000_eeprom_info *eeprom = &hw->eeprom; |
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uint32_t eecd = E1000_READ_REG(hw, EECD); |
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uint32_t eecd; |
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int32_t ret_val = E1000_SUCCESS; |
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uint16_t eeprom_size; |
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if (hw->mac_type == e1000_igb) |
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eecd = E1000_READ_REG(hw, I210_EECD); |
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else |
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eecd = E1000_READ_REG(hw, EECD); |
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DEBUGFUNC(); |
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switch (hw->mac_type) { |
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@ -485,9 +496,10 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
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eeprom->page_size = 8; |
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eeprom->address_bits = 8; |
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} |
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eeprom->use_eerd = true; |
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eeprom->use_eewr = true; |
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if (e1000_is_onboard_nvm_eeprom(hw) == false) { |
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eeprom->use_eerd = true; |
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eeprom->use_eewr = true; |
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eeprom->type = e1000_eeprom_flash; |
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eeprom->word_size = 2048; |
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@ -511,6 +523,16 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
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eeprom->use_eerd = true; |
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eeprom->use_eewr = false; |
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break; |
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case e1000_igb: |
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/* i210 has 4k of iNVM mapped as EEPROM */ |
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eeprom->type = e1000_eeprom_invm; |
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eeprom->opcode_bits = 8; |
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eeprom->delay_usec = 1; |
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eeprom->page_size = 32; |
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eeprom->address_bits = 16; |
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eeprom->use_eerd = true; |
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eeprom->use_eewr = false; |
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break; |
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/* ich8lan does not support currently. if needed, please
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* add corresponding code and functions. |
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@ -552,7 +574,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) |
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break; |
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} |
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if (eeprom->type == e1000_eeprom_spi) { |
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if (eeprom->type == e1000_eeprom_spi || |
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eeprom->type == e1000_eeprom_invm) { |
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/* eeprom_size will be an enum [0..8] that maps
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* to eeprom sizes 128B to |
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* 32KB (incremented by powers of 2). |
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@ -596,10 +619,17 @@ e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
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int32_t done = E1000_ERR_EEPROM; |
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for (i = 0; i < attempts; i++) { |
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if (eerd == E1000_EEPROM_POLL_READ) |
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reg = E1000_READ_REG(hw, EERD); |
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else |
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reg = E1000_READ_REG(hw, EEWR); |
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if (eerd == E1000_EEPROM_POLL_READ) { |
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if (hw->mac_type == e1000_igb) |
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reg = E1000_READ_REG(hw, I210_EERD); |
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else |
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reg = E1000_READ_REG(hw, EERD); |
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} else { |
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if (hw->mac_type == e1000_igb) |
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reg = E1000_READ_REG(hw, I210_EEWR); |
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else |
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reg = E1000_READ_REG(hw, EEWR); |
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} |
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if (reg & E1000_EEPROM_RW_REG_DONE) { |
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done = E1000_SUCCESS; |
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@ -632,13 +662,23 @@ e1000_read_eeprom_eerd(struct e1000_hw *hw, |
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eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
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E1000_EEPROM_RW_REG_START; |
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E1000_WRITE_REG(hw, EERD, eerd); |
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if (hw->mac_type == e1000_igb) |
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E1000_WRITE_REG(hw, I210_EERD, eerd); |
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else |
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E1000_WRITE_REG(hw, EERD, eerd); |
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error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
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if (error) |
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break; |
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data[i] = (E1000_READ_REG(hw, EERD) >> |
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if (hw->mac_type == e1000_igb) { |
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data[i] = (E1000_READ_REG(hw, I210_EERD) >> |
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E1000_EEPROM_RW_REG_DATA); |
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} else { |
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data[i] = (E1000_READ_REG(hw, EERD) >> |
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E1000_EEPROM_RW_REG_DATA); |
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} |
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} |
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@ -949,6 +989,10 @@ e1000_get_software_semaphore(struct e1000_hw *hw) |
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DEBUGFUNC(); |
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swsm = E1000_READ_REG(hw, SWSM); |
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swsm &= ~E1000_SWSM_SMBI; |
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E1000_WRITE_REG(hw, SWSM, swsm); |
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if (hw->mac_type != e1000_80003es2lan) |
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return E1000_SUCCESS; |
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@ -1069,7 +1113,7 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
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return -E1000_ERR_SWFW_SYNC; |
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swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
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if (!(swfw_sync & (fwmask | swmask))) |
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if ((swfw_sync & swmask) && !(swfw_sync & fwmask)) |
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break; |
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/* firmware currently using resource (fwmask) */ |
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@ -1118,13 +1162,23 @@ e1000_read_mac_addr(struct eth_device *nic) |
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struct e1000_hw *hw = nic->priv; |
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uint16_t offset; |
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uint16_t eeprom_data; |
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uint32_t reg_data = 0; |
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int i; |
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DEBUGFUNC(); |
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for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
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offset = i >> 1; |
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if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
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if (hw->mac_type == e1000_igb) { |
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/* i210 preloads MAC address into RAL/RAH registers */ |
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if (offset == 0) |
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reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); |
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else if (offset == 1) |
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reg_data >>= 16; |
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else if (offset == 2) |
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reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); |
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eeprom_data = reg_data & 0xffff; |
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} else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
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DEBUGOUT("EEPROM Read Error\n"); |
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return -E1000_ERR_EEPROM; |
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} |
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@ -1320,6 +1374,13 @@ e1000_set_mac_type(struct e1000_hw *hw) |
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case E1000_DEV_ID_ICH8_IGP_M: |
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hw->mac_type = e1000_ich8lan; |
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break; |
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case PCI_DEVICE_ID_INTEL_I210_COPPER: |
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case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS: |
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case PCI_DEVICE_ID_INTEL_I210_SERDES: |
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case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS: |
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case PCI_DEVICE_ID_INTEL_I210_1000BASEKX: |
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hw->mac_type = e1000_igb; |
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break; |
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default: |
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/* Should never have loaded on this device */ |
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return -E1000_ERR_MAC_TYPE; |
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@ -1339,6 +1400,7 @@ e1000_reset_hw(struct e1000_hw *hw) |
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uint32_t ctrl_ext; |
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uint32_t manc; |
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uint32_t pba = 0; |
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uint32_t reg; |
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DEBUGFUNC(); |
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@ -1357,6 +1419,8 @@ e1000_reset_hw(struct e1000_hw *hw) |
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/* Clear interrupt mask to stop board from generating interrupts */ |
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DEBUGOUT("Masking off all interrupts\n"); |
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if (hw->mac_type == e1000_igb) |
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E1000_WRITE_REG(hw, I210_IAM, 0); |
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E1000_WRITE_REG(hw, IMC, 0xffffffff); |
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/* Disable the Transmit and Receive units. Then delay to allow
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@ -1386,7 +1450,15 @@ e1000_reset_hw(struct e1000_hw *hw) |
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E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
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/* Force a reload from the EEPROM if necessary */ |
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if (hw->mac_type < e1000_82540) { |
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if (hw->mac_type == e1000_igb) { |
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mdelay(20); |
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reg = E1000_READ_REG(hw, STATUS); |
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if (reg & E1000_STATUS_PF_RST_DONE) |
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DEBUGOUT("PF OK\n"); |
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reg = E1000_READ_REG(hw, I210_EECD); |
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if (reg & E1000_EECD_AUTO_RD) |
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DEBUGOUT("EEC OK\n"); |
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} else if (hw->mac_type < e1000_82540) { |
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/* Wait for reset to complete */ |
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udelay(10); |
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ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
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@ -1406,6 +1478,8 @@ e1000_reset_hw(struct e1000_hw *hw) |
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/* Clear interrupt mask to stop board from generating interrupts */ |
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DEBUGOUT("Masking off all interrupts\n"); |
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if (hw->mac_type == e1000_igb) |
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E1000_WRITE_REG(hw, I210_IAM, 0); |
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E1000_WRITE_REG(hw, IMC, 0xffffffff); |
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/* Clear any pending interrupt events. */ |
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@ -1415,7 +1489,8 @@ e1000_reset_hw(struct e1000_hw *hw) |
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if (hw->mac_type == e1000_82542_rev2_0) { |
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pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); |
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} |
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E1000_WRITE_REG(hw, PBA, pba); |
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if (hw->mac_type != e1000_igb) |
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E1000_WRITE_REG(hw, PBA, pba); |
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} |
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/******************************************************************************
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@ -1451,6 +1526,10 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) |
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reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; |
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E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); |
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/* IGB is cool */ |
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if (hw->mac_type == e1000_igb) |
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return; |
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switch (hw->mac_type) { |
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case e1000_82571: |
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case e1000_82572: |
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@ -1641,6 +1720,7 @@ e1000_init_hw(struct eth_device *nic) |
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switch (hw->mac_type) { |
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case e1000_82545_rev_3: |
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case e1000_82546_rev_3: |
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case e1000_igb: |
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break; |
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default: |
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/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
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@ -1670,6 +1750,8 @@ e1000_init_hw(struct eth_device *nic) |
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/* More time needed for PHY to initialize */ |
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if (hw->mac_type == e1000_ich8lan) |
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mdelay(15); |
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if (hw->mac_type == e1000_igb) |
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mdelay(15); |
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/* Call a subroutine to configure the link and setup flow control. */ |
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ret_val = e1000_setup_link(nic); |
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@ -1684,7 +1766,6 @@ e1000_init_hw(struct eth_device *nic) |
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} |
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/* Set the receive descriptor write back policy */ |
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if (hw->mac_type >= e1000_82571) { |
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ctrl = E1000_READ_REG(hw, RXDCTL); |
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ctrl = |
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@ -1731,6 +1812,8 @@ e1000_init_hw(struct eth_device *nic) |
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reg_data = E1000_READ_REG(hw, GCR); |
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reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
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E1000_WRITE_REG(hw, GCR, reg_data); |
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case e1000_igb: |
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break; |
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} |
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#if 0 |
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@ -1807,6 +1890,7 @@ e1000_setup_link(struct eth_device *nic) |
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case e1000_ich8lan: |
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case e1000_82573: |
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case e1000_82574: |
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case e1000_igb: |
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hw->fc = e1000_fc_full; |
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break; |
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default: |
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@ -2267,6 +2351,8 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
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if (hw->mac_type == e1000_ich8lan) { |
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phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
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} else if (hw->mac_type == e1000_igb) { |
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phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); |
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} else { |
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ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
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&phy_data); |
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@ -2278,6 +2364,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
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if (hw->mac_type == e1000_ich8lan) { |
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phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
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E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
|
|
|
} else if (hw->mac_type == e1000_igb) { |
|
|
|
|
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
|
|
|
|
E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); |
|
|
|
|
} else { |
|
|
|
|
phy_data &= ~IGP02E1000_PM_D0_LPLU; |
|
|
|
|
ret_val = e1000_write_phy_reg(hw, |
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|
|
@ -2286,6 +2375,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
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|
return ret_val; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (hw->mac_type == e1000_igb) |
|
|
|
|
return E1000_SUCCESS; |
|
|
|
|
|
|
|
|
|
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
|
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|
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|
* Dx states where the power conservation is most important. During |
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|
|
|
* driver activity we should enable SmartSpeed, so performance is |
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|
|
@ -2320,6 +2412,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
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|
|
|
if (hw->mac_type == e1000_ich8lan) { |
|
|
|
|
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
|
|
|
|
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
|
|
|
|
} else if (hw->mac_type == e1000_igb) { |
|
|
|
|
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
|
|
|
|
E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); |
|
|
|
|
} else { |
|
|
|
|
phy_data |= IGP02E1000_PM_D0_LPLU; |
|
|
|
|
ret_val = e1000_write_phy_reg(hw, |
|
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|
@ -2328,6 +2423,9 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) |
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|
|
return ret_val; |
|
|
|
|
} |
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|
|
|
|
|
|
|
if (hw->mac_type == e1000_igb) |
|
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|
|
return E1000_SUCCESS; |
|
|
|
|
|
|
|
|
|
/* When LPLU is enabled we should disable SmartSpeed */ |
|
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|
|
ret_val = e1000_read_phy_reg(hw, |
|
|
|
|
IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
|
|
|
@ -2549,8 +2647,10 @@ e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) |
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|
|
if (e1000_is_second_port(hw)) |
|
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|
|
swfw = E1000_SWFW_PHY1_SM; |
|
|
|
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|
|
|
|
|
if (e1000_swfw_sync_acquire(hw, swfw)) |
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|
|
|
if (e1000_swfw_sync_acquire(hw, swfw)) { |
|
|
|
|
debug("%s[%i]\n", __func__, __LINE__); |
|
|
|
|
return -E1000_ERR_SWFW_SYNC; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Write register address */ |
|
|
|
|
reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
|
|
|
@ -2985,7 +3085,8 @@ e1000_setup_copper_link(struct eth_device *nic) |
|
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|
|
ret_val = e1000_copper_link_igp_setup(hw); |
|
|
|
|
if (ret_val) |
|
|
|
|
return ret_val; |
|
|
|
|
} else if (hw->phy_type == e1000_phy_m88) { |
|
|
|
|
} else if (hw->phy_type == e1000_phy_m88 || |
|
|
|
|
hw->phy_type == e1000_phy_igb) { |
|
|
|
|
ret_val = e1000_copper_link_mgp_setup(hw); |
|
|
|
|
if (ret_val) |
|
|
|
|
return ret_val; |
|
|
|
@ -3229,7 +3330,8 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) |
|
|
|
|
*/ |
|
|
|
|
ctrl = E1000_READ_REG(hw, CTRL); |
|
|
|
|
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
|
|
|
|
ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
|
|
|
|
ctrl &= ~(E1000_CTRL_ILOS); |
|
|
|
|
ctrl |= (E1000_CTRL_SPD_SEL); |
|
|
|
|
|
|
|
|
|
/* Set up duplex in the Device Control and Transmit Control
|
|
|
|
|
* registers depending on negotiated values. |
|
|
|
@ -4255,11 +4357,16 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) |
|
|
|
|
|
|
|
|
|
case e1000_82571: |
|
|
|
|
case e1000_82572: |
|
|
|
|
case e1000_igb: |
|
|
|
|
while (timeout) { |
|
|
|
|
if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
|
|
|
|
break; |
|
|
|
|
else |
|
|
|
|
mdelay(1); |
|
|
|
|
if (hw->mac_type == e1000_igb) { |
|
|
|
|
if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) |
|
|
|
|
break; |
|
|
|
|
} else { |
|
|
|
|
if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
|
|
|
|
break; |
|
|
|
|
} |
|
|
|
|
mdelay(1); |
|
|
|
|
timeout--; |
|
|
|
|
} |
|
|
|
|
if (!timeout) { |
|
|
|
@ -4488,6 +4595,7 @@ e1000_phy_reset(struct e1000_hw *hw) |
|
|
|
|
case e1000_phy_igp_2: |
|
|
|
|
case e1000_phy_igp_3: |
|
|
|
|
case e1000_phy_ife: |
|
|
|
|
case e1000_phy_igb: |
|
|
|
|
ret_val = e1000_phy_hw_reset(hw); |
|
|
|
|
if (ret_val) |
|
|
|
|
return ret_val; |
|
|
|
@ -4550,6 +4658,9 @@ static int e1000_set_phy_type (struct e1000_hw *hw) |
|
|
|
|
case BME1000_E_PHY_ID: |
|
|
|
|
hw->phy_type = e1000_phy_bm; |
|
|
|
|
break; |
|
|
|
|
case I210_I_PHY_ID: |
|
|
|
|
hw->phy_type = e1000_phy_igb; |
|
|
|
|
break; |
|
|
|
|
/* Fall Through */ |
|
|
|
|
default: |
|
|
|
|
/* Should never have loaded on this device */ |
|
|
|
@ -4654,6 +4765,10 @@ e1000_detect_gig_phy(struct e1000_hw *hw) |
|
|
|
|
if (hw->phy_id == IFE_C_E_PHY_ID) |
|
|
|
|
match = true; |
|
|
|
|
break; |
|
|
|
|
case e1000_igb: |
|
|
|
|
if (hw->phy_id == I210_I_PHY_ID) |
|
|
|
|
match = true; |
|
|
|
|
break; |
|
|
|
|
default: |
|
|
|
|
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); |
|
|
|
|
return -E1000_ERR_CONFIG; |
|
|
|
@ -4705,6 +4820,7 @@ e1000_set_media_type(struct e1000_hw *hw) |
|
|
|
|
case e1000_ich8lan: |
|
|
|
|
case e1000_82573: |
|
|
|
|
case e1000_82574: |
|
|
|
|
case e1000_igb: |
|
|
|
|
/* The STATUS_TBIMODE bit is reserved or reused
|
|
|
|
|
* for the this device. |
|
|
|
|
*/ |
|
|
|
@ -4773,6 +4889,7 @@ e1000_sw_init(struct eth_device *nic) |
|
|
|
|
hw->fc_send_xon = 1; |
|
|
|
|
|
|
|
|
|
/* Media type - copper or fiber */ |
|
|
|
|
hw->tbi_compatibility_en = true; |
|
|
|
|
e1000_set_media_type(hw); |
|
|
|
|
|
|
|
|
|
if (hw->mac_type >= e1000_82543) { |
|
|
|
@ -4789,7 +4906,6 @@ e1000_sw_init(struct eth_device *nic) |
|
|
|
|
hw->media_type = e1000_media_type_fiber; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
hw->tbi_compatibility_en = true; |
|
|
|
|
hw->wait_autoneg_complete = true; |
|
|
|
|
if (hw->mac_type < e1000_82543) |
|
|
|
|
hw->report_tx_early = 0; |
|
|
|
@ -4907,7 +5023,22 @@ e1000_configure_tx(struct e1000_hw *hw) |
|
|
|
|
hw->txd_cmd |= E1000_TXD_CMD_RPS; |
|
|
|
|
else |
|
|
|
|
hw->txd_cmd |= E1000_TXD_CMD_RS; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
if (hw->mac_type == e1000_igb) { |
|
|
|
|
E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); |
|
|
|
|
|
|
|
|
|
uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); |
|
|
|
|
reg_txdctl |= 1 << 25; |
|
|
|
|
E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); |
|
|
|
|
mdelay(20); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
E1000_WRITE_REG(hw, TCTL, tctl); |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
@ -4978,7 +5109,16 @@ e1000_configure_rx(struct e1000_hw *hw) |
|
|
|
|
E1000_WRITE_REG(hw, RDT, 0); |
|
|
|
|
/* Enable Receives */ |
|
|
|
|
|
|
|
|
|
if (hw->mac_type == e1000_igb) { |
|
|
|
|
|
|
|
|
|
uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); |
|
|
|
|
reg_rxdctl |= 1 << 25; |
|
|
|
|
E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); |
|
|
|
|
mdelay(20); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
E1000_WRITE_REG(hw, RCTL, rctl); |
|
|
|
|
|
|
|
|
|
fill_rx(hw); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
@ -5140,9 +5280,8 @@ void e1000_get_bus_type(struct e1000_hw *hw) |
|
|
|
|
case e1000_82573: |
|
|
|
|
case e1000_82574: |
|
|
|
|
case e1000_80003es2lan: |
|
|
|
|
hw->bus_type = e1000_bus_type_pci_express; |
|
|
|
|
break; |
|
|
|
|
case e1000_ich8lan: |
|
|
|
|
case e1000_igb: |
|
|
|
|
hw->bus_type = e1000_bus_type_pci_express; |
|
|
|
|
break; |
|
|
|
|
default: |
|
|
|
@ -5223,6 +5362,7 @@ e1000_initialize(bd_t * bis) |
|
|
|
|
hw->autoneg_failed = 0; |
|
|
|
|
hw->autoneg = 1; |
|
|
|
|
hw->get_link_status = true; |
|
|
|
|
hw->eeprom_semaphore_present = true; |
|
|
|
|
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, |
|
|
|
|
PCI_REGION_MEM); |
|
|
|
|
hw->mac_type = e1000_undefined; |
|
|
|
@ -5246,7 +5386,8 @@ e1000_initialize(bd_t * bis) |
|
|
|
|
E1000_ERR(nic, "EEPROM is invalid!\n"); |
|
|
|
|
continue; |
|
|
|
|
} |
|
|
|
|
if (e1000_validate_eeprom_checksum(hw)) |
|
|
|
|
if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && |
|
|
|
|
e1000_validate_eeprom_checksum(hw)) |
|
|
|
|
continue; |
|
|
|
|
#endif |
|
|
|
|
e1000_read_mac_addr(nic); |
|
|
|
|