This patch provides support for the A4M072 board with the following features: UART NOR flash FEC Ethernet External SRAM I2C EEPROM CompactFlash cards on IDE/ATA port USB Host PCI initialization The 7-segment LED indicator is not yet supported. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>master
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
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* |
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* (C) Copyright 2010 |
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <libfdt.h> |
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#include <netdev.h> |
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#include "mt46v32m16.h" |
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#ifndef CONFIG_SYS_RAMBOOT |
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static void sdram_start (int hi_addr) |
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{ |
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long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
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long control = SDRAM_CONTROL | hi_addr_bit; |
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/* unlock mode register */ |
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); |
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__asm__ volatile ("sync"); |
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/* precharge all banks */ |
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); |
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__asm__ volatile ("sync"); |
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#if SDRAM_DDR |
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/* set mode register: extended mode */ |
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); |
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__asm__ volatile ("sync"); |
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/* set mode register: reset DLL */ |
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); |
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__asm__ volatile ("sync"); |
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#endif |
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/* precharge all banks */ |
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); |
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__asm__ volatile ("sync"); |
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/* auto refresh */ |
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); |
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__asm__ volatile ("sync"); |
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/* set mode register */ |
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); |
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__asm__ volatile ("sync"); |
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/* normal operation */ |
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control); |
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__asm__ volatile ("sync"); |
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} |
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#endif |
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use |
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
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* is something else than 0x00000000. |
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*/ |
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phys_size_t initdram (int board_type) |
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{ |
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ulong dramsize = 0; |
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uint svr, pvr; |
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#ifndef CONFIG_SYS_RAMBOOT |
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ulong test1, test2; |
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/* setup SDRAM chip selects */ |
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ |
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ |
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__asm__ volatile ("sync"); |
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/* setup config registers */ |
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out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); |
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out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); |
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__asm__ volatile ("sync"); |
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#if SDRAM_DDR |
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/* set tap delay */ |
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out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); |
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__asm__ volatile ("sync"); |
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#endif |
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/* find RAM size using SDRAM CS0 only */ |
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sdram_start(0); |
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
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sdram_start(1); |
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); |
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if (test1 > test2) { |
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sdram_start(0); |
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dramsize = test1; |
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} else { |
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dramsize = test2; |
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} |
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/* memory smaller than 1MB is impossible */ |
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if (dramsize < (1 << 20)) { |
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dramsize = 0; |
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} |
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/* set SDRAM CS0 size according to the amount of RAM found */ |
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if (dramsize > 0) { |
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, |
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0x13 + __builtin_ffs(dramsize >> 20) - 1); |
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} else { |
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ |
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} |
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#else /* CONFIG_SYS_RAMBOOT */ |
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/* retrieve size of memory connected to SDRAM CS0 */ |
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dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; |
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if (dramsize >= 0x13) { |
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dramsize = (1 << (dramsize - 0x13)) << 20; |
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} else { |
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dramsize = 0; |
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} |
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#endif /* CONFIG_SYS_RAMBOOT */ |
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/*
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* On MPC5200B we need to set the special configuration delay in the |
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM |
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: |
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* |
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* "The SDelay should be written to a value of 0x00000004. It is |
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* required to account for changes caused by normal wafer processing |
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* parameters." |
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*/ |
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svr = get_svr(); |
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pvr = get_pvr(); |
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if ((SVR_MJREV(svr) >= 2) && |
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { |
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out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); |
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__asm__ volatile ("sync"); |
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} |
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return dramsize; |
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} |
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int checkboard (void) |
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{ |
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puts ("Board: A4M072\n"); |
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return 0; |
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} |
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#ifdef CONFIG_PCI |
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static struct pci_controller hose; |
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extern void pci_mpc5xxx_init(struct pci_controller *); |
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void pci_init_board(void) |
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{ |
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pci_mpc5xxx_init(&hose); |
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} |
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#endif |
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
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void |
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ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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} |
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#endif |
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int board_eth_init(bd_t *bis) |
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{ |
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int rv, num_if = 0; |
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/* Initialize TSECs first */ |
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if ((rv = cpu_eth_init(bis)) >= 0) |
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num_if += rv; |
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else |
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printf("ERROR: failed to initialize FEC.\n"); |
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if ((rv = pci_eth_init(bis)) >= 0) |
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num_if += rv; |
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else |
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printf("ERROR: failed to initialize PCI Ethernet.\n"); |
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return num_if; |
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} |
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/*
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* Miscellaneous late-boot configurations |
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* |
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* Initialize EEPROM write-protect GPIO pin. |
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*/ |
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int misc_init_r(void) |
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{ |
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#if defined(CONFIG_SYS_EEPROM_WREN) |
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/* Enable GPIO pin */ |
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP); |
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/* Set direction, output */ |
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP); |
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/* De-assert write enable */ |
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); |
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#endif |
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return 0; |
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} |
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#if defined(CONFIG_SYS_EEPROM_WREN) |
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state |
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* 0: disable write |
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* 1: enable write |
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* Returns: -1: wrong device address |
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* 0: dis-/en- able done |
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* 0/1: current state if <state> was -1. |
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*/ |
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int eeprom_write_enable (unsigned dev_addr, int state) |
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{ |
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if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { |
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return -1; |
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} else { |
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switch (state) { |
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case 1: |
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/* Enable write access */ |
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clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); |
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state = 0; |
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break; |
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case 0: |
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/* Disable write access */ |
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); |
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state = 0; |
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break; |
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default: |
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/* Read current status back. */ |
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state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & |
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CONFIG_SYS_EEPROM_WP)); |
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break; |
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} |
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} |
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return state; |
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} |
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#endif |
@ -0,0 +1,39 @@ |
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# a4m072 board:
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#
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# Valid values for TEXT_BASE is:
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#
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# 0xFE000000 boot low
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
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ifndef TEXT_BASE |
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## Standard: boot low
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TEXT_BASE = 0xFE000000
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endif |
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,37 @@ |
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/*
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#define SDRAM_DDR 1 /* is DDR */ |
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#if defined(CONFIG_MPC5200) |
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/* Settings for XLB = 132 MHz */ |
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#define SDRAM_MODE 0x018D0000 |
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#define SDRAM_EMODE 0x40010000 |
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#define SDRAM_CONTROL 0x704f0f00 |
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#define SDRAM_CONFIG1 0x73722930 |
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#define SDRAM_CONFIG2 0x47770000 |
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#define SDRAM_TAPDELAY 0x10000000 |
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#else |
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#error CONFIG_MPC5200 not defined |
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#endif |
@ -0,0 +1,377 @@ |
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/*
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* (C) Copyright 2003-2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2010 |
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
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#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */ |
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#define CONFIG_A4M072 1 /* ... on A4M072 board */ |
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#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ |
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#define CONFIG_MISC_INIT_R |
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
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/*
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* Serial console configuration |
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*/ |
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
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#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
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/* define to enable silent console */ |
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#define CONFIG_SILENT_CONSOLE |
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
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/*
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* PCI Mapping: |
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* 0x40000000 - 0x4fffffff - PCI Memory |
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* 0x50000000 - 0x50ffffff - PCI IO Space |
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*/ |
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#define CONFIG_PCI |
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#if defined(CONFIG_PCI) |
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#define CONFIG_PCI_PNP 1 |
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#define CONFIG_PCI_SCAN_SHOW 1 |
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
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#define CONFIG_PCI_MEM_BUS 0x40000000 |
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
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#define CONFIG_PCI_MEM_SIZE 0x10000000 |
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#define CONFIG_PCI_IO_BUS 0x50000000 |
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
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#define CONFIG_PCI_IO_SIZE 0x01000000 |
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#endif |
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#define CONFIG_SYS_XLB_PIPELINING 1 |
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#undef CONFIG_NET_MULTI |
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#undef CONFIG_EEPRO100 |
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/* Partitions */ |
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#define CONFIG_MAC_PARTITION |
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#define CONFIG_DOS_PARTITION |
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/* USB */ |
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#define CONFIG_USB_OHCI_NEW |
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#define CONFIG_USB_STORAGE |
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#define CONFIG_SYS_OHCI_BE_CONTROLLER |
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
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#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB |
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" |
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 |
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
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/*
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* BOOTP options |
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*/ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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/*
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* Command line configuration. |
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*/ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_EEPROM |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_IDE |
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#define CONFIG_CMD_NFS |
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#define CONFIG_CMD_SNTP |
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#define CONFIG_CMD_USB |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_PING |
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#if defined(CONFIG_PCI) |
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#define CONFIG_CMD_PCI |
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#endif |
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||||
#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */ |
||||
#define CONFIG_SYS_LOWBOOT 1 |
||||
#define CONFIG_SYS_LOWBOOT32 1 |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ |
||||
|
||||
#define CONFIG_SYS_AUTOLOAD "n" |
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED |
||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay |
||||
#define CONFIG_AUTOBOOT_DELAY_STR "asdfg" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_PREBOOT "run try_update" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
|
||||
"cf1=diskboot 200000 0:1\0" \
|
||||
"bootcmd_cf1=run bcf1\0" \
|
||||
"bcf=setenv bootargs root=/dev/hda3\0" \
|
||||
"bootcmd_nfs=run bnfs\0" \
|
||||
"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs\0" \
|
||||
"bootcmd_nor=cp.b ${kernel_addr} 200000 100000; run norargs addip; run bk\0" \
|
||||
"bnfs=nfs 200000 ${rootpath}/boot/uImage ; run nfsargs addip ; run bk\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
|
||||
"try_update=usb start;sleep 2;usb start;sleep 1;fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;source 2F0000\0" \
|
||||
"env_addr=FE060000\0" \
|
||||
"kernel_addr=FE100000\0" \
|
||||
"rootfs_addr=FE200000\0" \
|
||||
"add_mtd=setenv bootargs ${bootargs} mtdparts=phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
|
||||
"bcf1=run cf1; run bcf; run addip; run bk\0" \
|
||||
"add_consolespec=setenv bootargs ${bootargs} console=/dev/null quiet\0" \
|
||||
"addip=if test \"${ethaddr}\" != \"00:00:00:00:00:00\" ; then if test -n ${ipaddr}; then setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off panic=1; fi ; fi\0" \
|
||||
"hostname=CPUP0\0" \
|
||||
"ethaddr=00:00:00:00:00:00\0" \
|
||||
"netdev=eth0\0" \
|
||||
"bootcmd=run bootcmd_nor\0" \
|
||||
"" |
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
||||
|
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
#define CONFIG_SYS_EEPROM_WREN 1 |
||||
#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4 |
||||
|
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xFE000000 |
||||
#define CONFIG_SYS_FLASH_SIZE 0x02000000 |
||||
#if !defined(CONFIG_SYS_LOWBOOT) |
||||
#error "CONFIG_SYS_LOWBOOT not defined?" |
||||
#else /* CONFIG_SYS_LOWBOOT */ |
||||
#if defined(CONFIG_SYS_LOWBOOT32) |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
||||
#endif |
||||
#endif /* CONFIG_SYS_LOWBOOT */ |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START} |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SIZE 0x10000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CONFIG_SYS_MBAR 0xF0000000 |
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
||||
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Use SRAM until RAM will be available */ |
||||
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ |
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
||||
# define CONFIG_SYS_RAMBOOT 1 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
#define CONFIG_MPC5xxx_FEC_MII100 |
||||
/*
|
||||
* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
||||
*/ |
||||
/* #define CONFIG_MPC5xxx_FEC_MII10 */ |
||||
#define CONFIG_PHY_ADDR 0x1f |
||||
#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */ |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
*/ |
||||
#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CONFIG_SYS_HID0_FINAL HID0_ICE |
||||
/* Flash at CSBoot, CS0 */ |
||||
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE |
||||
#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00 |
||||
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE |
||||
/* External SRAM at CS1 */ |
||||
#define CONFIG_SYS_CS1_START 0x62000000 |
||||
#define CONFIG_SYS_CS1_SIZE 0x00400000 |
||||
#define CONFIG_SYS_CS1_CFG 0x00009930 |
||||
#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START |
||||
#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE |
||||
|
||||
|
||||
#define CONFIG_SYS_CS_BURST 0x00000000 |
||||
#define CONFIG_SYS_CS_DEADCYCLE 0x33333003 |
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* USB stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_USB_CLOCK 0x0001BBBB |
||||
#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff Supports IDE harddisk |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
|
||||
#define CONFIG_IDE_PREINIT |
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ |
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
||||
|
||||
/* Interval between registers */ |
||||
#define CONFIG_SYS_ATA_STRIDE 4 |
||||
|
||||
#define CONFIG_ATAPI 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Open firmware flat tree support |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_OF_LIBFDT 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
#define OF_CPU "PowerPC,5200@0" |
||||
#define OF_SOC "soc5200@f0000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue