commit
9597494ebf
@ -0,0 +1,60 @@ |
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/*
|
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* Tegra pulse width frequency modulator definitions |
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* |
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* Copyright (c) 2011 The Chromium OS Authors. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef __ASM_ARCH_TEGRA_PWM_H |
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#define __ASM_ARCH_TEGRA_PWM_H |
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|
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/* This is a single PWM channel */ |
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struct pwm_ctlr { |
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uint control; /* Control register */ |
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uint reserved[3]; /* Space space */ |
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}; |
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|
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#define PWM_NUM_CHANNELS 4 |
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|
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/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ |
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#define PWM_ENABLE_SHIFT 31 |
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#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) |
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|
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#define PWM_WIDTH_SHIFT 16 |
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#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT) |
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#define PWM_DIVIDER_SHIFT 0 |
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#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT) |
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|
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/**
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* Program the PWM with the given parameters. |
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* |
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* @param channel PWM channel to update |
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* @param rate Clock rate to use for PWM, or 0 to leave alone |
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* @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high, |
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* n = n/256 pulse high |
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* @param freq_divider frequency divider value (1 to use rate as is) |
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*/ |
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void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider); |
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|
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/**
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* Request a pwm channel as referenced by a device tree node. |
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* |
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* This channel can then be passed to pwm_enable(). |
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* |
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* @param blob Device tree blob |
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* @param node Node containing reference to pwm |
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* @param prop_name Property name of pwm reference |
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* @return channel number, if ok, else -1 |
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*/ |
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int pwm_request(const void *blob, int node, const char *prop_name); |
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|
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/**
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* Set up the pwm controller, by looking it up in the fdt. |
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* |
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* @return 0 if ok, -1 if the device tree node was not found or invalid. |
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*/ |
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int pwm_init(const void *blob); |
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#endif /* __ASM_ARCH_TEGRA_PWM_H */ |
@ -0,0 +1,58 @@ |
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/*
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* (C) Copyright 2010 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H |
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#define __ASM_ARCH_TEGRA_DISPLAY_H |
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|
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/**
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* Register a new display based on device tree configuration. |
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* |
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* The frame buffer can be positioned by U-Boot or overriden by the fdt. |
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* You should pass in the U-Boot address here, and check the contents of |
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* struct fdt_disp_config to see what was actually chosen. |
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* |
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* @param blob Device tree blob |
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* @param default_lcd_base Default address of LCD frame buffer |
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* @return 0 if ok, -1 on error (unsupported bits per pixel) |
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*/ |
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int tegra_display_probe(const void *blob, void *default_lcd_base); |
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|
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/**
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* Return the current display configuration |
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* |
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* @return pointer to display configuration, or NULL if there is no valid |
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* config |
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*/ |
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struct fdt_disp_config *tegra_display_get_config(void); |
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|
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/**
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* Perform the next stage of the LCD init if it is time to do so. |
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* |
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* LCD init can be time-consuming because of the number of delays we need |
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* while waiting for the backlight power supply, etc. This function can |
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* be called at various times during U-Boot operation to advance the |
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* initialization of the LCD to the next stage if sufficient time has |
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* passed since the last stage. It keeps track of what stage it is up to |
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* and the time that it is permitted to move to the next stage. |
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* |
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* The final call should have wait=1 to complete the init. |
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* |
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* @param blob fdt blob containing LCD information |
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* @param wait 1 to wait until all init is complete, and then return |
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* 0 to return immediately, potentially doing nothing if it is |
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* not yet time for the next init. |
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*/ |
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int tegra_lcd_check_next_stage(const void *blob, int wait); |
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/**
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* Set up the maximum LCD size so we can size the frame buffer. |
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* |
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* @param blob fdt blob containing LCD information |
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*/ |
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void tegra_lcd_early_init(const void *blob); |
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ |
@ -0,0 +1,14 @@ |
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/*
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* Tegra pulse width frequency modulator definitions |
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* |
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* Copyright (c) 2011 The Chromium OS Authors. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __ASM_ARCH_TEGRA124_PWM_H |
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#define __ASM_ARCH_TEGRA124_PWM_H |
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#include <asm/arch-tegra/pwm.h> |
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#endif /* __ASM_ARCH_TEGRA124_PWM_H */ |
@ -0,0 +1,114 @@ |
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/* |
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* Copyright (C) 2014, NVIDIA |
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* Copyright (C) 2015, Siemens AG |
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* |
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* Authors: |
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* Thierry Reding <treding@nvidia.com>
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* Jan Kiszka <jan.kiszka@siemens.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/macro.h> |
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#include <asm/psci.h> |
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.pushsection ._secure.text, "ax" |
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.arch_extension sec
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#define TEGRA_SB_CSR_0 0x6000c200 |
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#define NS_RST_VEC_WR_DIS (1 << 1) |
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#define TEGRA_RESET_EXCEPTION_VECTOR 0x6000f100 |
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#define TEGRA_FLOW_CTRL_BASE 0x60007000 |
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#define FLOW_CTRL_CPU_CSR 0x08 |
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#define CSR_ENABLE (1 << 0) |
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#define CSR_IMMEDIATE_WAKE (1 << 3) |
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#define CSR_WAIT_WFI_SHIFT 8 |
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#define FLOW_CTRL_CPU1_CSR 0x18 |
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@ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
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.macro get_csr_reg cpu, ofs, tmp |
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cmp \cpu, #0 @ CPU0?
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lsl \tmp, \cpu, #3 @ multiple by 8 (register offset CPU1-3)
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moveq \ofs, #FLOW_CTRL_CPU_CSR |
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addne \ofs, \tmp, #FLOW_CTRL_CPU1_CSR - 8 |
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.endm |
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ENTRY(psci_arch_init) |
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mov r6, lr |
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb |
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@ lock reset vector for non-secure
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ldr r4, =TEGRA_SB_CSR_0 |
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ldr r5, [r4] |
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orr r5, r5, #NS_RST_VEC_WR_DIS |
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str r5, [r4] |
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bl psci_get_cpu_id @ CPU ID => r0
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adr r5, _sys_clock_freq |
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cmp r0, #0 |
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mrceq p15, 0, r7, c14, c0, 0 @ read CNTFRQ from CPU0
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streq r7, [r5] |
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ldrne r7, [r5] |
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mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3
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bl psci_get_cpu_stack_top @ stack top => r0
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mov sp, r0 |
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bx r6 |
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ENDPROC(psci_arch_init) |
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_sys_clock_freq: |
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.word 0
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ENTRY(psci_cpu_off) |
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bl psci_cpu_off_common |
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bl psci_get_cpu_id @ CPU ID => r0
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get_csr_reg r0, r2, r3 |
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ldr r6, =TEGRA_FLOW_CTRL_BASE |
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mov r5, #(CSR_ENABLE) |
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mov r4, #(1 << CSR_WAIT_WFI_SHIFT) |
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add r5, r4, lsl r0 |
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str r5, [r6, r2] |
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_loop: wfi |
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b _loop |
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ENDPROC(psci_cpu_off) |
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ENTRY(psci_cpu_on) |
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push {lr} |
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mov r0, r1 |
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bl psci_get_cpu_stack_top @ get stack top of target CPU
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str r2, [r0] @ store target PC at stack top
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dsb |
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ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR |
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ldr r5, =psci_cpu_entry |
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str r5, [r6] |
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get_csr_reg r1, r2, r3 |
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ldr r6, =TEGRA_FLOW_CTRL_BASE |
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mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE) |
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str r5, [r6, r2] |
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS |
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pop {pc} |
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ENDPROC(psci_cpu_on) |
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.globl psci_text_end
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psci_text_end: |
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.popsection |
@ -0,0 +1,59 @@ |
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/*
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* (C) Copyright 2015, Siemens AG |
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* Author: Jan Kiszka <jan.kiszka@siemens.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/psci.h> |
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#include <asm/arch/flow.h> |
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#include <asm/arch/powergate.h> |
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#include <asm/arch-tegra/ap.h> |
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#include <asm/arch-tegra/pmc.h> |
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static void park_cpu(void) |
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{ |
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while (1) |
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asm volatile("wfi"); |
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} |
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/**
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* Initialize power management for application processors |
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*/ |
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void psci_board_init(void) |
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{ |
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; |
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writel((u32)park_cpu, EXCEP_VECTOR_CPU_RESET_VECTOR); |
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/*
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* The naturally expected order of putting these CPUs under Flow |
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* Controller regime would be |
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* - configure the Flow Controller |
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* - power up the CPUs |
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* - wait for the CPUs to hit wfi and be powered down again |
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* |
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* However, this doesn't work in practice. We rather need to power them |
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* up first and park them in wfi. While they are waiting there, we can |
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* indeed program the Flow Controller to powergate them on wfi, which |
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* will then happen immediately as they are already in that state. |
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*/ |
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU1); |
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU2); |
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tegra_powergate_power_on(TEGRA_POWERGATE_CPU3); |
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writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); |
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writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); |
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writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); |
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writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); |
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writel(EVENT_MODE_STOP, &flow->halt_cpu2_events); |
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writel(EVENT_MODE_STOP, &flow->halt_cpu3_events); |
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while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) || |
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!(readl(&flow->cpu2_csr) & CSR_PWR_OFF_STS) || |
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!(readl(&flow->cpu3_csr) & CSR_PWR_OFF_STS)) |
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/* wait */; |
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} |
@ -1,4 +0,0 @@ |
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# Copyright (c) 2011 The Chromium OS Authors.
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# SPDX-License-Identifier: GPL-2.0+
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include $(src)/common.mk |
@ -1,3 +0,0 @@ |
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# common options for all tegra boards
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obj-y += ../../nvidia/common/board.o
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obj-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o
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@ -1,6 +1,4 @@ |
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# Copyright (c) 2014 Marcel Ziswiler
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# SPDX-License-Identifier: GPL-2.0+
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include $(srctree)/board/nvidia/common/common.mk |
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obj-y += apalis_t30.o
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|
@ -1,6 +1,4 @@ |
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# Copyright (c) 2013-2014 Stefan Agner
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# SPDX-License-Identifier: GPL-2.0+
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include $(srctree)/board/nvidia/common/common.mk |
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obj-y += colibri_t30.o
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|
@ -0,0 +1,372 @@ |
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NVIDIA Tegra host1x |
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|
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Required properties: |
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- compatible: "nvidia,tegra<chip>-host1x" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- #address-cells: The number of cells used to represent physical base addresses |
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in the host1x address space. Should be 1. |
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- #size-cells: The number of cells used to represent the size of an address |
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range in the host1x address space. Should be 1. |
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- ranges: The mapping of the host1x address space to the CPU address space. |
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- clocks: Must contain one entry, for the module clock. |
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See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- host1x |
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|
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The host1x top-level node defines a number of children, each representing one |
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of the following host1x client modules: |
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|
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- mpe: video encoder |
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|
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Required properties: |
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- compatible: "nvidia,tegra<chip>-mpe" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- clocks: Must contain one entry, for the module clock. |
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See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- mpe |
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|
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- vi: video input |
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|
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Required properties: |
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- compatible: "nvidia,tegra<chip>-vi" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- clocks: Must contain one entry, for the module clock. |
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See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- vi |
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|
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- epp: encoder pre-processor |
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|
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Required properties: |
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- compatible: "nvidia,tegra<chip>-epp" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- clocks: Must contain one entry, for the module clock. |
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See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- epp |
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|
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- isp: image signal processor |
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|
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Required properties: |
||||
- compatible: "nvidia,tegra<chip>-isp" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- clocks: Must contain one entry, for the module clock. |
||||
See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- isp |
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|
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- gr2d: 2D graphics engine |
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|
||||
Required properties: |
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- compatible: "nvidia,tegra<chip>-gr2d" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. |
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- clocks: Must contain one entry, for the module clock. |
||||
See ../clocks/clock-bindings.txt for details. |
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- resets: Must contain an entry for each entry in reset-names. |
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See ../reset/reset.txt for details. |
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- reset-names: Must include the following entries: |
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- 2d |
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|
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- gr3d: 3D graphics engine |
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|
||||
Required properties: |
||||
- compatible: "nvidia,tegra<chip>-gr3d" |
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- reg: Physical base address and length of the controller's registers. |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
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- clock-names: Must include the following entries: |
||||
(This property may be omitted if the only clock in the list is "3d") |
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- 3d |
||||
This MUST be the first entry. |
||||
- 3d2 (Only required on SoCs with two 3D clocks) |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- 3d |
||||
- 3d2 (Only required on SoCs with two 3D clocks) |
||||
|
||||
- dc: display controller |
||||
|
||||
Required properties: |
||||
- compatible: "nvidia,tegra<chip>-dc" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- interrupts: The interrupt outputs from the controller. |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
- clock-names: Must include the following entries: |
||||
- dc |
||||
This MUST be the first entry. |
||||
- parent |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- dc |
||||
- nvidia,head: The number of the display controller head. This is used to |
||||
setup the various types of output to receive video data from the given |
||||
head. |
||||
|
||||
Each display controller node has a child node, named "rgb", that represents |
||||
the RGB output associated with the controller. It can take the following |
||||
optional properties: |
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
||||
- nvidia,edid: supplies a binary EDID blob |
||||
- nvidia,panel: phandle of a display panel |
||||
|
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- hdmi: High Definition Multimedia Interface |
||||
|
||||
Required properties: |
||||
- compatible: "nvidia,tegra<chip>-hdmi" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- interrupts: The interrupt outputs from the controller. |
||||
- hdmi-supply: supply for the +5V HDMI connector pin |
||||
- vdd-supply: regulator for supply voltage |
||||
- pll-supply: regulator for PLL |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
- clock-names: Must include the following entries: |
||||
- hdmi |
||||
This MUST be the first entry. |
||||
- parent |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- hdmi |
||||
|
||||
Optional properties: |
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
||||
- nvidia,edid: supplies a binary EDID blob |
||||
- nvidia,panel: phandle of a display panel |
||||
|
||||
- tvo: TV encoder output |
||||
|
||||
Required properties: |
||||
- compatible: "nvidia,tegra<chip>-tvo" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- interrupts: The interrupt outputs from the controller. |
||||
- clocks: Must contain one entry, for the module clock. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
|
||||
- dsi: display serial interface |
||||
|
||||
Required properties: |
||||
- compatible: "nvidia,tegra<chip>-dsi" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
- clock-names: Must include the following entries: |
||||
- dsi |
||||
This MUST be the first entry. |
||||
- lp |
||||
- parent |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- dsi |
||||
- avdd-dsi-supply: phandle of a supply that powers the DSI controller |
||||
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying |
||||
which pads are used by this DSI output and need to be calibrated. See also |
||||
../mipi/nvidia,tegra114-mipi.txt. |
||||
|
||||
Optional properties: |
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
||||
- nvidia,edid: supplies a binary EDID blob |
||||
- nvidia,panel: phandle of a display panel |
||||
|
||||
- sor: serial output resource |
||||
|
||||
Required properties: |
||||
- compatible: "nvidia,tegra124-sor" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- interrupts: The interrupt outputs from the controller. |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
- clock-names: Must include the following entries: |
||||
- sor: clock input for the SOR hardware |
||||
- parent: input for the pixel clock |
||||
- dp: reference clock for the SOR clock |
||||
- safe: safe reference for the SOR clock during power up |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- sor |
||||
|
||||
Optional properties: |
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing |
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
||||
- nvidia,edid: supplies a binary EDID blob |
||||
- nvidia,panel: phandle of a display panel |
||||
|
||||
Optional properties when driving an eDP output: |
||||
- nvidia,dpaux: phandle to a DispayPort AUX interface |
||||
|
||||
- dpaux: DisplayPort AUX interface |
||||
- compatible: "nvidia,tegra124-dpaux" |
||||
- reg: Physical base address and length of the controller's registers. |
||||
- interrupts: The interrupt outputs from the controller. |
||||
- clocks: Must contain an entry for each entry in clock-names. |
||||
See ../clocks/clock-bindings.txt for details. |
||||
- clock-names: Must include the following entries: |
||||
- dpaux: clock input for the DPAUX hardware |
||||
- parent: reference clock |
||||
- resets: Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names: Must include the following entries: |
||||
- dpaux |
||||
- vdd-supply: phandle of a supply that powers the DisplayPort link |
||||
|
||||
Example: |
||||
|
||||
/ { |
||||
... |
||||
|
||||
host1x { |
||||
compatible = "nvidia,tegra20-host1x", "simple-bus"; |
||||
reg = <0x50000000 0x00024000>; |
||||
interrupts = <0 65 0x04 /* mpcore syncpt */ |
||||
0 67 0x04>; /* mpcore general */ |
||||
clocks = <&tegra_car TEGRA20_CLK_HOST1X>; |
||||
resets = <&tegra_car 28>; |
||||
reset-names = "host1x"; |
||||
|
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
ranges = <0x54000000 0x54000000 0x04000000>; |
||||
|
||||
mpe { |
||||
compatible = "nvidia,tegra20-mpe"; |
||||
reg = <0x54040000 0x00040000>; |
||||
interrupts = <0 68 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_MPE>; |
||||
resets = <&tegra_car 60>; |
||||
reset-names = "mpe"; |
||||
}; |
||||
|
||||
vi { |
||||
compatible = "nvidia,tegra20-vi"; |
||||
reg = <0x54080000 0x00040000>; |
||||
interrupts = <0 69 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_VI>; |
||||
resets = <&tegra_car 100>; |
||||
reset-names = "vi"; |
||||
}; |
||||
|
||||
epp { |
||||
compatible = "nvidia,tegra20-epp"; |
||||
reg = <0x540c0000 0x00040000>; |
||||
interrupts = <0 70 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_EPP>; |
||||
resets = <&tegra_car 19>; |
||||
reset-names = "epp"; |
||||
}; |
||||
|
||||
isp { |
||||
compatible = "nvidia,tegra20-isp"; |
||||
reg = <0x54100000 0x00040000>; |
||||
interrupts = <0 71 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_ISP>; |
||||
resets = <&tegra_car 23>; |
||||
reset-names = "isp"; |
||||
}; |
||||
|
||||
gr2d { |
||||
compatible = "nvidia,tegra20-gr2d"; |
||||
reg = <0x54140000 0x00040000>; |
||||
interrupts = <0 72 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_GR2D>; |
||||
resets = <&tegra_car 21>; |
||||
reset-names = "2d"; |
||||
}; |
||||
|
||||
gr3d { |
||||
compatible = "nvidia,tegra20-gr3d"; |
||||
reg = <0x54180000 0x00040000>; |
||||
clocks = <&tegra_car TEGRA20_CLK_GR3D>; |
||||
resets = <&tegra_car 24>; |
||||
reset-names = "3d"; |
||||
}; |
||||
|
||||
dc@54200000 { |
||||
compatible = "nvidia,tegra20-dc"; |
||||
reg = <0x54200000 0x00040000>; |
||||
interrupts = <0 73 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_DISP1>, |
||||
<&tegra_car TEGRA20_CLK_PLL_P>; |
||||
clock-names = "dc", "parent"; |
||||
resets = <&tegra_car 27>; |
||||
reset-names = "dc"; |
||||
|
||||
rgb { |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
dc@54240000 { |
||||
compatible = "nvidia,tegra20-dc"; |
||||
reg = <0x54240000 0x00040000>; |
||||
interrupts = <0 74 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_DISP2>, |
||||
<&tegra_car TEGRA20_CLK_PLL_P>; |
||||
clock-names = "dc", "parent"; |
||||
resets = <&tegra_car 26>; |
||||
reset-names = "dc"; |
||||
|
||||
rgb { |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
hdmi { |
||||
compatible = "nvidia,tegra20-hdmi"; |
||||
reg = <0x54280000 0x00040000>; |
||||
interrupts = <0 75 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_HDMI>, |
||||
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>; |
||||
clock-names = "hdmi", "parent"; |
||||
resets = <&tegra_car 51>; |
||||
reset-names = "hdmi"; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
tvo { |
||||
compatible = "nvidia,tegra20-tvo"; |
||||
reg = <0x542c0000 0x00040000>; |
||||
interrupts = <0 76 0x04>; |
||||
clocks = <&tegra_car TEGRA20_CLK_TVO>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
dsi { |
||||
compatible = "nvidia,tegra20-dsi"; |
||||
reg = <0x54300000 0x00040000>; |
||||
clocks = <&tegra_car TEGRA20_CLK_DSI>, |
||||
<&tegra_car TEGRA20_CLK_PLL_D_OUT0>; |
||||
clock-names = "dsi", "parent"; |
||||
resets = <&tegra_car 48>; |
||||
reset-names = "dsi"; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
|
||||
... |
||||
}; |
@ -0,0 +1,110 @@ |
||||
display-timing bindings |
||||
======================= |
||||
|
||||
display-timings node |
||||
-------------------- |
||||
|
||||
required properties: |
||||
- none |
||||
|
||||
optional properties: |
||||
- native-mode: The native mode for the display, in case multiple modes are |
||||
provided. When omitted, assume the first node is the native. |
||||
|
||||
timing subnode |
||||
-------------- |
||||
|
||||
required properties: |
||||
- hactive, vactive: display resolution |
||||
- hfront-porch, hback-porch, hsync-len: horizontal display timing parameters |
||||
in pixels |
||||
vfront-porch, vback-porch, vsync-len: vertical display timing parameters in |
||||
lines |
||||
- clock-frequency: display clock in Hz |
||||
|
||||
optional properties: |
||||
- hsync-active: hsync pulse is active low/high/ignored |
||||
- vsync-active: vsync pulse is active low/high/ignored |
||||
- de-active: data-enable pulse is active low/high/ignored |
||||
- pixelclk-active: with |
||||
- active high = drive pixel data on rising edge/ |
||||
sample data on falling edge |
||||
- active low = drive pixel data on falling edge/ |
||||
sample data on rising edge |
||||
- ignored = ignored |
||||
- interlaced (bool): boolean to enable interlaced mode |
||||
- doublescan (bool): boolean to enable doublescan mode |
||||
- doubleclk (bool): boolean to enable doubleclock mode |
||||
|
||||
All the optional properties that are not bool follow the following logic: |
||||
<1>: high active |
||||
<0>: low active |
||||
omitted: not used on hardware |
||||
|
||||
There are different ways of describing the capabilities of a display. The |
||||
devicetree representation corresponds to the one commonly found in datasheets |
||||
for displays. If a display supports multiple signal timings, the native-mode |
||||
can be specified. |
||||
|
||||
The parameters are defined as: |
||||
|
||||
+----------+-------------------------------------+----------+-------+ |
||||
| | ↑ | | | |
||||
| | |vback_porch | | | |
||||
| | ↓ | | | |
||||
+----------#######################################----------+-------+ |
||||
| # ↑ # | | |
||||
| # | # | | |
||||
| hback # | # hfront | hsync | |
||||
| porch # | hactive # porch | len | |
||||
|<-------->#<-------+--------------------------->#<-------->|<----->| |
||||
| # | # | | |
||||
| # |vactive # | | |
||||
| # | # | | |
||||
| # ↓ # | | |
||||
+----------#######################################----------+-------+ |
||||
| | ↑ | | | |
||||
| | |vfront_porch | | | |
||||
| | ↓ | | | |
||||
+----------+-------------------------------------+----------+-------+ |
||||
| | ↑ | | | |
||||
| | |vsync_len | | | |
||||
| | ↓ | | | |
||||
+----------+-------------------------------------+----------+-------+ |
||||
|
||||
Example: |
||||
|
||||
display-timings { |
||||
native-mode = <&timing0>; |
||||
timing0: 1080p24 { |
||||
/* 1920x1080p24 */ |
||||
clock-frequency = <52000000>; |
||||
hactive = <1920>; |
||||
vactive = <1080>; |
||||
hfront-porch = <25>; |
||||
hback-porch = <25>; |
||||
hsync-len = <25>; |
||||
vback-porch = <2>; |
||||
vfront-porch = <2>; |
||||
vsync-len = <2>; |
||||
hsync-active = <1>; |
||||
}; |
||||
}; |
||||
|
||||
Every required property also supports the use of ranges, so the commonly used |
||||
datasheet description with minimum, typical and maximum values can be used. |
||||
|
||||
Example: |
||||
|
||||
timing1: timing { |
||||
/* 1920x1080p24 */ |
||||
clock-frequency = <148500000>; |
||||
hactive = <1920>; |
||||
vactive = <1080>; |
||||
hsync-len = <0 44 60>; |
||||
hfront-porch = <80 88 95>; |
||||
hback-porch = <100 148 160>; |
||||
vfront-porch = <0 4 6>; |
||||
vback-porch = <0 36 50>; |
||||
vsync-len = <0 5 6>; |
||||
}; |
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* Copyright 2014 Google Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <displayport.h> |
||||
#include <errno.h> |
||||
|
||||
int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size) |
||||
{ |
||||
struct dm_display_port_ops *ops = display_port_get_ops(dev); |
||||
|
||||
if (!ops || !ops->read_edid) |
||||
return -ENOSYS; |
||||
return ops->read_edid(dev, buf, buf_size); |
||||
} |
||||
|
||||
int display_port_enable(struct udevice *dev, int panel_bpp, |
||||
const struct display_timing *timing) |
||||
{ |
||||
struct dm_display_port_ops *ops = display_port_get_ops(dev); |
||||
|
||||
if (!ops || !ops->enable) |
||||
return -ENOSYS; |
||||
return ops->enable(dev, panel_bpp, timing); |
||||
} |
||||
|
||||
UCLASS_DRIVER(display_port) = { |
||||
.id = UCLASS_DISPLAY_PORT, |
||||
.name = "display_port", |
||||
}; |
@ -0,0 +1,10 @@ |
||||
#
|
||||
# Copyright (c) 2014 Google, Inc
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += display.o
|
||||
obj-y += dp.o
|
||||
obj-y += sor.o
|
||||
obj-y += tegra124-lcd.o
|
@ -0,0 +1,472 @@ |
||||
/*
|
||||
* Copyright 2014 Google Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Extracted from Chromium coreboot commit 3f59b13d |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <edid.h> |
||||
#include <errno.h> |
||||
#include <displayport.h> |
||||
#include <edid.h> |
||||
#include <fdtdec.h> |
||||
#include <lcd.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/pwm.h> |
||||
#include <asm/arch-tegra/dc.h> |
||||
#include "displayport.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* return in 1000ths of a Hertz */ |
||||
static int tegra_dc_calc_refresh(const struct display_timing *timing) |
||||
{ |
||||
int h_total, v_total, refresh; |
||||
int pclk = timing->pixelclock.typ; |
||||
|
||||
h_total = timing->hactive.typ + timing->hfront_porch.typ + |
||||
timing->hback_porch.typ + timing->hsync_len.typ; |
||||
v_total = timing->vactive.typ + timing->vfront_porch.typ + |
||||
timing->vback_porch.typ + timing->vsync_len.typ; |
||||
if (!pclk || !h_total || !v_total) |
||||
return 0; |
||||
refresh = pclk / h_total; |
||||
refresh *= 1000; |
||||
refresh /= v_total; |
||||
|
||||
return refresh; |
||||
} |
||||
|
||||
static void print_mode(const struct display_timing *timing) |
||||
{ |
||||
int refresh = tegra_dc_calc_refresh(timing); |
||||
|
||||
debug("MODE:%dx%d@%d.%03uHz pclk=%d\n", |
||||
timing->hactive.typ, timing->vactive.typ, refresh / 1000, |
||||
refresh % 1000, timing->pixelclock.typ); |
||||
} |
||||
|
||||
static int update_display_mode(struct dc_ctlr *disp_ctrl, |
||||
const struct display_timing *timing, |
||||
int href_to_sync, int vref_to_sync) |
||||
{ |
||||
print_mode(timing); |
||||
|
||||
writel(0x1, &disp_ctrl->disp.disp_timing_opt); |
||||
|
||||
writel(vref_to_sync << 16 | href_to_sync, |
||||
&disp_ctrl->disp.ref_to_sync); |
||||
|
||||
writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, |
||||
&disp_ctrl->disp.sync_width); |
||||
|
||||
writel(((timing->vback_porch.typ - vref_to_sync) << 16) | |
||||
timing->hback_porch.typ, &disp_ctrl->disp.back_porch); |
||||
|
||||
writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | |
||||
timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); |
||||
|
||||
writel(timing->hactive.typ | (timing->vactive.typ << 16), |
||||
&disp_ctrl->disp.disp_active); |
||||
|
||||
/**
|
||||
* We want to use PLLD_out0, which is PLLD / 2: |
||||
* PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. |
||||
* |
||||
* Currently most panels work inside clock range 50MHz~100MHz, and PLLD |
||||
* has some requirements to have VCO in range 500MHz~1000MHz (see |
||||
* clock.c for more detail). To simplify calculation, we set |
||||
* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values |
||||
* may be calculated by clock_display, to allow wider frequency range. |
||||
* |
||||
* Note ShiftClockDiv is a 7.1 format value. |
||||
*/ |
||||
const u32 shift_clock_div = 1; |
||||
writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | |
||||
((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, |
||||
&disp_ctrl->disp.disp_clk_ctrl); |
||||
debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__, |
||||
timing->pixelclock.typ, shift_clock_div); |
||||
return 0; |
||||
} |
||||
|
||||
static u32 tegra_dc_poll_register(void *reg, |
||||
u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_us) |
||||
{ |
||||
u32 temp = timeout_us; |
||||
u32 reg_val = 0; |
||||
|
||||
do { |
||||
udelay(poll_interval_us); |
||||
reg_val = readl(reg); |
||||
if (timeout_us > poll_interval_us) |
||||
timeout_us -= poll_interval_us; |
||||
else |
||||
break; |
||||
} while ((reg_val & mask) != exp_val); |
||||
|
||||
if ((reg_val & mask) == exp_val) |
||||
return 0; /* success */ |
||||
|
||||
return temp; |
||||
} |
||||
|
||||
int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl) |
||||
{ |
||||
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); |
||||
|
||||
if (tegra_dc_poll_register(&disp_ctrl->cmd.state_ctrl, |
||||
GENERAL_ACT_REQ, 0, 100, |
||||
DC_POLL_TIMEOUT_MS * 1000)) { |
||||
debug("dc timeout waiting for DC to stop\n"); |
||||
return -ETIMEDOUT; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct display_timing min_mode = { |
||||
.hsync_len = { .typ = 1 }, |
||||
.vsync_len = { .typ = 1 }, |
||||
.hback_porch = { .typ = 20 }, |
||||
.vback_porch = { .typ = 0 }, |
||||
.hactive = { .typ = 16 }, |
||||
.vactive = { .typ = 16 }, |
||||
.hfront_porch = { .typ = 1 }, |
||||
.vfront_porch = { .typ = 2 }, |
||||
}; |
||||
|
||||
/* Disable windows and set minimum raster timings */ |
||||
void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, |
||||
int *dc_reg_ctx) |
||||
{ |
||||
const int href_to_sync = 0, vref_to_sync = 1; |
||||
int selected_windows, i; |
||||
|
||||
selected_windows = readl(&disp_ctrl->cmd.disp_win_header); |
||||
|
||||
/* Store and clear window options */ |
||||
for (i = 0; i < DC_N_WINDOWS; ++i) { |
||||
writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); |
||||
dc_reg_ctx[i] = readl(&disp_ctrl->win.win_opt); |
||||
writel(0, &disp_ctrl->win.win_opt); |
||||
writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); |
||||
} |
||||
|
||||
writel(selected_windows, &disp_ctrl->cmd.disp_win_header); |
||||
|
||||
/* Store current raster timings and set minimum timings */ |
||||
dc_reg_ctx[i++] = readl(&disp_ctrl->disp.ref_to_sync); |
||||
writel(href_to_sync | (vref_to_sync << 16), |
||||
&disp_ctrl->disp.ref_to_sync); |
||||
|
||||
dc_reg_ctx[i++] = readl(&disp_ctrl->disp.sync_width); |
||||
writel(min_mode.hsync_len.typ | (min_mode.vsync_len.typ << 16), |
||||
&disp_ctrl->disp.sync_width); |
||||
|
||||
dc_reg_ctx[i++] = readl(&disp_ctrl->disp.back_porch); |
||||
writel(min_mode.hback_porch.typ | (min_mode.vback_porch.typ << 16), |
||||
&disp_ctrl->disp.back_porch); |
||||
|
||||
dc_reg_ctx[i++] = readl(&disp_ctrl->disp.front_porch); |
||||
writel(min_mode.hfront_porch.typ | (min_mode.vfront_porch.typ << 16), |
||||
&disp_ctrl->disp.front_porch); |
||||
|
||||
dc_reg_ctx[i++] = readl(&disp_ctrl->disp.disp_active); |
||||
writel(min_mode.hactive.typ | (min_mode.vactive.typ << 16), |
||||
&disp_ctrl->disp.disp_active); |
||||
|
||||
writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl); |
||||
} |
||||
|
||||
/* Restore previous windows status and raster timings */ |
||||
void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, |
||||
int *dc_reg_ctx) |
||||
{ |
||||
int selected_windows, i; |
||||
|
||||
selected_windows = readl(&disp_ctrl->cmd.disp_win_header); |
||||
|
||||
for (i = 0; i < DC_N_WINDOWS; ++i) { |
||||
writel(WINDOW_A_SELECT << i, &disp_ctrl->cmd.disp_win_header); |
||||
writel(dc_reg_ctx[i], &disp_ctrl->win.win_opt); |
||||
writel(WIN_A_ACT_REQ << i, &disp_ctrl->cmd.state_ctrl); |
||||
} |
||||
|
||||
writel(selected_windows, &disp_ctrl->cmd.disp_win_header); |
||||
|
||||
writel(dc_reg_ctx[i++], &disp_ctrl->disp.ref_to_sync); |
||||
writel(dc_reg_ctx[i++], &disp_ctrl->disp.sync_width); |
||||
writel(dc_reg_ctx[i++], &disp_ctrl->disp.back_porch); |
||||
writel(dc_reg_ctx[i++], &disp_ctrl->disp.front_porch); |
||||
writel(dc_reg_ctx[i++], &disp_ctrl->disp.disp_active); |
||||
|
||||
writel(GENERAL_UPDATE, &disp_ctrl->cmd.state_ctrl); |
||||
} |
||||
|
||||
static int tegra_depth_for_bpp(int bpp) |
||||
{ |
||||
switch (bpp) { |
||||
case 32: |
||||
return COLOR_DEPTH_R8G8B8A8; |
||||
case 16: |
||||
return COLOR_DEPTH_B5G6R5; |
||||
default: |
||||
debug("Unsupported LCD bit depth"); |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
static int update_window(struct dc_ctlr *disp_ctrl, |
||||
u32 frame_buffer, int fb_bits_per_pixel, |
||||
const struct display_timing *timing) |
||||
{ |
||||
const u32 colour_white = 0xffffff; |
||||
int colour_depth; |
||||
u32 val; |
||||
|
||||
writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
||||
|
||||
writel(((timing->vactive.typ << 16) | timing->hactive.typ), |
||||
&disp_ctrl->win.size); |
||||
writel(((timing->vactive.typ << 16) | |
||||
(timing->hactive.typ * fb_bits_per_pixel / 8)), |
||||
&disp_ctrl->win.prescaled_size); |
||||
writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / |
||||
32 * 32), &disp_ctrl->win.line_stride); |
||||
|
||||
colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel); |
||||
if (colour_depth == -1) |
||||
return -EINVAL; |
||||
|
||||
writel(colour_depth, &disp_ctrl->win.color_depth); |
||||
|
||||
writel(frame_buffer, &disp_ctrl->winbuf.start_addr); |
||||
writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT, |
||||
&disp_ctrl->win.dda_increment); |
||||
|
||||
writel(colour_white, &disp_ctrl->disp.blend_background_color); |
||||
writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, |
||||
&disp_ctrl->cmd.disp_cmd); |
||||
|
||||
writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); |
||||
|
||||
val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
||||
val |= GENERAL_UPDATE | WIN_A_UPDATE; |
||||
writel(val, &disp_ctrl->cmd.state_ctrl); |
||||
|
||||
/* Enable win_a */ |
||||
val = readl(&disp_ctrl->win.win_opt); |
||||
writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int tegra_dc_init(struct dc_ctlr *disp_ctrl) |
||||
{ |
||||
/* do not accept interrupts during initialization */ |
||||
writel(0x00000000, &disp_ctrl->cmd.int_mask); |
||||
writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, |
||||
&disp_ctrl->cmd.state_access); |
||||
writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
||||
writel(0x00000000, &disp_ctrl->win.win_opt); |
||||
writel(0x00000000, &disp_ctrl->win.byte_swap); |
||||
writel(0x00000000, &disp_ctrl->win.buffer_ctrl); |
||||
|
||||
writel(0x00000000, &disp_ctrl->win.pos); |
||||
writel(0x00000000, &disp_ctrl->win.h_initial_dda); |
||||
writel(0x00000000, &disp_ctrl->win.v_initial_dda); |
||||
writel(0x00000000, &disp_ctrl->win.dda_increment); |
||||
writel(0x00000000, &disp_ctrl->win.dv_ctrl); |
||||
|
||||
writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); |
||||
writel(0x00000000, &disp_ctrl->win.blend_match_select); |
||||
writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); |
||||
writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); |
||||
|
||||
writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); |
||||
writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); |
||||
writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); |
||||
|
||||
writel(0x00000000, &disp_ctrl->com.crc_checksum); |
||||
writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); |
||||
writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); |
||||
writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); |
||||
writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); |
||||
writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void dump_config(int panel_bpp, struct display_timing *timing) |
||||
{ |
||||
printf("timing->hactive.typ = %d\n", timing->hactive.typ); |
||||
printf("timing->vactive.typ = %d\n", timing->vactive.typ); |
||||
printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); |
||||
|
||||
printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); |
||||
printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); |
||||
printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); |
||||
|
||||
printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); |
||||
printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); |
||||
printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); |
||||
|
||||
printf("panel_bits_per_pixel = %d\n", panel_bpp); |
||||
} |
||||
|
||||
static int display_update_config_from_edid(struct udevice *dp_dev, |
||||
int *panel_bppp, |
||||
struct display_timing *timing) |
||||
{ |
||||
u8 buf[EDID_SIZE]; |
||||
int bpc, ret; |
||||
|
||||
ret = display_port_read_edid(dp_dev, buf, sizeof(buf)); |
||||
if (ret < 0) |
||||
return ret; |
||||
ret = edid_get_timing(buf, ret, timing, &bpc); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* Use this information if valid */ |
||||
if (bpc != -1) |
||||
*panel_bppp = bpc * 3; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/* Somewhat torturous method */ |
||||
static int get_backlight_info(const void *blob, struct gpio_desc *vdd, |
||||
struct gpio_desc *enable, int *pwmp) |
||||
{ |
||||
int sor, panel, backlight, power; |
||||
const u32 *prop; |
||||
int len; |
||||
int ret; |
||||
|
||||
*pwmp = 0; |
||||
sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); |
||||
if (sor < 0) |
||||
return -ENOENT; |
||||
panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel"); |
||||
if (panel < 0) |
||||
return -ENOENT; |
||||
backlight = fdtdec_lookup_phandle(blob, panel, "backlight"); |
||||
if (backlight < 0) |
||||
return -ENOENT; |
||||
ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0, |
||||
enable, GPIOD_IS_OUT); |
||||
if (ret) |
||||
return ret; |
||||
prop = fdt_getprop(blob, backlight, "pwms", &len); |
||||
if (!prop || len != 3 * sizeof(u32)) |
||||
return -EINVAL; |
||||
*pwmp = fdt32_to_cpu(prop[1]); |
||||
|
||||
power = fdtdec_lookup_phandle(blob, backlight, "power-supply"); |
||||
if (power < 0) |
||||
return -ENOENT; |
||||
ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd, |
||||
GPIOD_IS_OUT); |
||||
if (ret) |
||||
goto err; |
||||
|
||||
return 0; |
||||
|
||||
err: |
||||
dm_gpio_free(NULL, enable); |
||||
return ret; |
||||
} |
||||
|
||||
int display_init(void *lcdbase, int fb_bits_per_pixel, |
||||
struct display_timing *timing) |
||||
{ |
||||
struct dc_ctlr *dc_ctlr; |
||||
const void *blob = gd->fdt_blob; |
||||
struct udevice *dp_dev; |
||||
const int href_to_sync = 1, vref_to_sync = 1; |
||||
int panel_bpp = 18; /* default 18 bits per pixel */ |
||||
u32 plld_rate; |
||||
struct gpio_desc vdd_gpio, enable_gpio; |
||||
int pwm; |
||||
int node; |
||||
int ret; |
||||
|
||||
ret = uclass_get_device(UCLASS_DISPLAY_PORT, 0, &dp_dev); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); |
||||
if (node < 0) |
||||
return -ENOENT; |
||||
dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); |
||||
if (fdtdec_decode_display_timing(blob, node, 0, timing)) |
||||
return -EINVAL; |
||||
|
||||
ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); |
||||
if (ret) { |
||||
debug("%s: Failed to decode EDID, using defaults\n", __func__); |
||||
dump_config(panel_bpp, timing); |
||||
} |
||||
|
||||
if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { |
||||
dm_gpio_set_value(&vdd_gpio, 1); |
||||
debug("%s: backlight vdd setting gpio %08x to %d\n", |
||||
__func__, gpio_get_number(&vdd_gpio), 1); |
||||
} |
||||
|
||||
/*
|
||||
* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER |
||||
* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the |
||||
* update_display_mode() for detail. |
||||
*/ |
||||
plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); |
||||
if (plld_rate == 0) { |
||||
printf("dc: clock init failed\n"); |
||||
return -EIO; |
||||
} else if (plld_rate != timing->pixelclock.typ * 2) { |
||||
debug("dc: plld rounded to %u\n", plld_rate); |
||||
timing->pixelclock.typ = plld_rate / 2; |
||||
} |
||||
|
||||
/* Init dc */ |
||||
ret = tegra_dc_init(dc_ctlr); |
||||
if (ret) { |
||||
debug("dc: init failed\n"); |
||||
return ret; |
||||
} |
||||
|
||||
/* Configure dc mode */ |
||||
ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); |
||||
if (ret) { |
||||
debug("dc: failed to configure display mode\n"); |
||||
return ret; |
||||
} |
||||
|
||||
/* Enable dp */ |
||||
ret = display_port_enable(dp_dev, panel_bpp, timing); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* Set up Tegra PWM to drive the panel backlight */ |
||||
pwm_enable(pwm, 0, 220, 0x2e); |
||||
udelay(10 * 1000); |
||||
|
||||
if (dm_gpio_is_valid(&enable_gpio)) { |
||||
dm_gpio_set_value(&enable_gpio, 1); |
||||
debug("%s: backlight enable setting gpio %08x to %d\n", |
||||
__func__, gpio_get_number(&enable_gpio), 1); |
||||
} |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,412 @@ |
||||
/*
|
||||
* Copyright (c) 2014, NVIDIA Corporation. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef _TEGRA_DISPLAYPORT_H |
||||
#define _TEGRA_DISPLAYPORT_H |
||||
|
||||
#include <linux/drm_dp_helper.h> |
||||
|
||||
struct dpaux_ctlr { |
||||
u32 reserved0; |
||||
u32 intr_en_aux; |
||||
u32 reserved2_4; |
||||
u32 intr_aux; |
||||
}; |
||||
|
||||
#define DPAUX_INTR_EN_AUX 0x1 |
||||
#define DPAUX_INTR_AUX 0x5 |
||||
#define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i)) |
||||
#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i)) |
||||
#define DPAUX_DP_AUXADDR 0x29 |
||||
#define DPAUX_DP_AUXCTL 0x2d |
||||
#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0 |
||||
#define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff |
||||
#define DPAUX_DP_AUXCTL_CMD_SHIFT 12 |
||||
#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) |
||||
#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) |
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16 |
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) |
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) |
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) |
||||
#define DPAUX_DP_AUXCTL_RST_SHIFT 31 |
||||
#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) |
||||
#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) |
||||
#define DPAUX_DP_AUXSTAT 0x31 |
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28 |
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) |
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20 |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) |
||||
#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16 |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) |
||||
#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) |
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11 |
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) |
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) |
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10 |
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) |
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) |
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9 |
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) |
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) |
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8 |
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) |
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) |
||||
#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0 |
||||
#define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) |
||||
#define DPAUX_HPD_CONFIG (0x3d) |
||||
#define DPAUX_HPD_IRQ_CONFIG 0x41 |
||||
#define DPAUX_DP_AUX_CONFIG 0x45 |
||||
#define DPAUX_HYBRID_PADCTL 0x49 |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15 |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14 |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) |
||||
#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12 |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8 |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2 |
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1 |
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) |
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) |
||||
#define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0 |
||||
#define DPAUX_HYBRID_PADCTL_MODE_AUX 0 |
||||
#define DPAUX_HYBRID_PADCTL_MODE_I2C 1 |
||||
#define DPAUX_HYBRID_SPARE 0x4d |
||||
#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0 |
||||
#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1 |
||||
|
||||
#define DP_AUX_DEFER_MAX_TRIES 7 |
||||
#define DP_AUX_TIMEOUT_MAX_TRIES 2 |
||||
#define DP_POWER_ON_MAX_TRIES 3 |
||||
|
||||
#define DP_AUX_MAX_BYTES 16 |
||||
|
||||
#define DP_AUX_TIMEOUT_MS 40 |
||||
#define DP_DPCP_RETRY_SLEEP_NS 400 |
||||
|
||||
static const u32 tegra_dp_vs_regs[][4][4] = { |
||||
/* postcursor2 L0 */ |
||||
{ |
||||
/* pre-emphasis: L0, L1, L2, L3 */ |
||||
{0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */ |
||||
{0x1e, 0x25, 0x2d}, /* L1 */ |
||||
{0x28, 0x32}, /* L2 */ |
||||
{0x3c}, /* L3 */ |
||||
}, |
||||
|
||||
/* postcursor2 L1 */ |
||||
{ |
||||
{0x12, 0x17, 0x1b, 0x25}, |
||||
{0x1c, 0x23, 0x2a}, |
||||
{0x25, 0x2f}, |
||||
{0x39}, |
||||
}, |
||||
|
||||
/* postcursor2 L2 */ |
||||
{ |
||||
{0x12, 0x16, 0x1a, 0x22}, |
||||
{0x1b, 0x20, 0x27}, |
||||
{0x24, 0x2d}, |
||||
{0x36}, |
||||
}, |
||||
|
||||
/* postcursor2 L3 */ |
||||
{ |
||||
{0x11, 0x14, 0x17, 0x1f}, |
||||
{0x19, 0x1e, 0x24}, |
||||
{0x22, 0x2a}, |
||||
{0x32}, |
||||
}, |
||||
}; |
||||
|
||||
static const u32 tegra_dp_pe_regs[][4][4] = { |
||||
/* postcursor2 L0 */ |
||||
{ |
||||
/* pre-emphasis: L0, L1, L2, L3 */ |
||||
{0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */ |
||||
{0x00, 0x0f, 0x1e}, /* L1 */ |
||||
{0x00, 0x14}, /* L2 */ |
||||
{0x00}, /* L3 */ |
||||
}, |
||||
|
||||
/* postcursor2 L1 */ |
||||
{ |
||||
{0x00, 0x0a, 0x14, 0x28}, |
||||
{0x00, 0x0f, 0x1e}, |
||||
{0x00, 0x14}, |
||||
{0x00}, |
||||
}, |
||||
|
||||
/* postcursor2 L2 */ |
||||
{ |
||||
{0x00, 0x0a, 0x14, 0x28}, |
||||
{0x00, 0x0f, 0x1e}, |
||||
{0x00, 0x14}, |
||||
{0x00}, |
||||
}, |
||||
|
||||
/* postcursor2 L3 */ |
||||
{ |
||||
{0x00, 0x0a, 0x14, 0x28}, |
||||
{0x00, 0x0f, 0x1e}, |
||||
{0x00, 0x14}, |
||||
{0x00}, |
||||
}, |
||||
}; |
||||
|
||||
static const u32 tegra_dp_pc_regs[][4][4] = { |
||||
/* postcursor2 L0 */ |
||||
{ |
||||
/* pre-emphasis: L0, L1, L2, L3 */ |
||||
{0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */ |
||||
{0x00, 0x00, 0x00}, /* L1 */ |
||||
{0x00, 0x00}, /* L2 */ |
||||
{0x00}, /* L3 */ |
||||
}, |
||||
|
||||
/* postcursor2 L1 */ |
||||
{ |
||||
{0x02, 0x02, 0x04, 0x05}, |
||||
{0x02, 0x04, 0x05}, |
||||
{0x04, 0x05}, |
||||
{0x05}, |
||||
}, |
||||
|
||||
/* postcursor2 L2 */ |
||||
{ |
||||
{0x04, 0x05, 0x08, 0x0b}, |
||||
{0x05, 0x09, 0x0b}, |
||||
{0x08, 0x0a}, |
||||
{0x0b}, |
||||
}, |
||||
|
||||
/* postcursor2 L3 */ |
||||
{ |
||||
{0x05, 0x09, 0x0b, 0x12}, |
||||
{0x09, 0x0d, 0x12}, |
||||
{0x0b, 0x0f}, |
||||
{0x12}, |
||||
}, |
||||
}; |
||||
|
||||
static const u32 tegra_dp_tx_pu[][4][4] = { |
||||
/* postcursor2 L0 */ |
||||
{ |
||||
/* pre-emphasis: L0, L1, L2, L3 */ |
||||
{0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */ |
||||
{0x30, 0x40, 0x60}, /* L1 */ |
||||
{0x40, 0x60}, /* L2 */ |
||||
{0x60}, /* L3 */ |
||||
}, |
||||
|
||||
/* postcursor2 L1 */ |
||||
{ |
||||
{0x20, 0x20, 0x30, 0x50}, |
||||
{0x30, 0x40, 0x50}, |
||||
{0x40, 0x50}, |
||||
{0x60}, |
||||
}, |
||||
|
||||
/* postcursor2 L2 */ |
||||
{ |
||||
{0x20, 0x20, 0x30, 0x40}, |
||||
{0x30, 0x30, 0x40}, |
||||
{0x40, 0x50}, |
||||
{0x60}, |
||||
}, |
||||
|
||||
/* postcursor2 L3 */ |
||||
{ |
||||
{0x20, 0x20, 0x20, 0x40}, |
||||
{0x30, 0x30, 0x40}, |
||||
{0x40, 0x40}, |
||||
{0x60}, |
||||
}, |
||||
}; |
||||
|
||||
enum { |
||||
DRIVECURRENT_LEVEL0 = 0, |
||||
DRIVECURRENT_LEVEL1 = 1, |
||||
DRIVECURRENT_LEVEL2 = 2, |
||||
DRIVECURRENT_LEVEL3 = 3, |
||||
}; |
||||
|
||||
enum { |
||||
PREEMPHASIS_DISABLED = 0, |
||||
PREEMPHASIS_LEVEL1 = 1, |
||||
PREEMPHASIS_LEVEL2 = 2, |
||||
PREEMPHASIS_LEVEL3 = 3, |
||||
}; |
||||
|
||||
enum { |
||||
POSTCURSOR2_LEVEL0 = 0, |
||||
POSTCURSOR2_LEVEL1 = 1, |
||||
POSTCURSOR2_LEVEL2 = 2, |
||||
POSTCURSOR2_LEVEL3 = 3, |
||||
POSTCURSOR2_SUPPORTED |
||||
}; |
||||
|
||||
static inline int tegra_dp_is_max_vs(u32 pe, u32 vs) |
||||
{ |
||||
return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1; |
||||
} |
||||
|
||||
static inline int tegra_dp_is_max_pe(u32 pe, u32 vs) |
||||
{ |
||||
return (pe < (PREEMPHASIS_LEVEL3 - vs)) ? 0 : 1; |
||||
} |
||||
|
||||
static inline int tegra_dp_is_max_pc(u32 pc) |
||||
{ |
||||
return (pc < POSTCURSOR2_LEVEL3) ? 0 : 1; |
||||
} |
||||
|
||||
/* DPCD definitions which are not defined in drm_dp_helper.h */ |
||||
#define DP_DPCD_REV_MAJOR_SHIFT 4 |
||||
#define DP_DPCD_REV_MAJOR_MASK (0xf << 4) |
||||
#define DP_DPCD_REV_MINOR_SHIFT 0 |
||||
#define DP_DPCD_REV_MINOR_MASK 0xf |
||||
|
||||
#define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6 |
||||
#define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa |
||||
#define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4 |
||||
|
||||
#define DP_MAX_LANE_COUNT_LANE_1 0x1 |
||||
#define DP_MAX_LANE_COUNT_LANE_2 0x2 |
||||
#define DP_MAX_LANE_COUNT_LANE_4 0x4 |
||||
#define DP_MAX_LANE_COUNT_TPS3_SUPPORTED_YES (1 << 6) |
||||
#define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7) |
||||
|
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 |
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) |
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) |
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 |
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) |
||||
#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F (0x00000000 << 5) |
||||
|
||||
#define DP_MAX_DOWNSPREAD_VAL_NONE 0 |
||||
#define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1 |
||||
#define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6) |
||||
|
||||
#define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1 |
||||
#define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1) |
||||
|
||||
#define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7) |
||||
|
||||
#define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5) |
||||
#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) |
||||
#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) |
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0 |
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1 |
||||
|
||||
#define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f |
||||
#define NV_DPCD_TRAINING_LANE2_3_SET2 0x110 |
||||
#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2) |
||||
#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F (0 << 2) |
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6) |
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F (0 << 6) |
||||
#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 |
||||
#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 |
||||
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 |
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) |
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) |
||||
|
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) |
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) |
||||
#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) |
||||
|
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 |
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) |
||||
#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) |
||||
#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) |
||||
#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) |
||||
#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) |
||||
|
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 |
||||
#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 |
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 |
||||
#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) |
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 |
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) |
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 |
||||
#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) |
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) |
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 |
||||
#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) |
||||
|
||||
#define NV_DPCD_TRAINING_AUX_RD_INTERVAL (0x0000000E) |
||||
#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F (0x00000000 << 2) |
||||
#endif |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,922 @@ |
||||
/*
|
||||
* Copyright (c) 2011-2013, NVIDIA Corporation. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef _VIDEO_TEGRA124_SOR_H |
||||
#define _VIDEO_TEGRA124_SOR_H |
||||
|
||||
#define SUPER_STATE0 0x1 |
||||
#define SUPER_STATE0_UPDATE_SHIFT 0 |
||||
#define SUPER_STATE0_UPDATE_DEFAULT_MASK 0x1 |
||||
#define SUPER_STATE1 0x2 |
||||
#define SUPER_STATE1_ATTACHED_SHIFT 3 |
||||
#define SUPER_STATE1_ATTACHED_NO (0 << 3) |
||||
#define SUPER_STATE1_ATTACHED_YES (1 << 3) |
||||
#define SUPER_STATE1_ASY_ORMODE_SHIFT 2 |
||||
#define SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2) |
||||
#define SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2) |
||||
#define SUPER_STATE1_ASY_HEAD_OP_SHIFT 0 |
||||
#define SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK 0x3 |
||||
#define SUPER_STATE1_ASY_HEAD_OP_SLEEP 0 |
||||
#define SUPER_STATE1_ASY_HEAD_OP_SNOOZE 1 |
||||
#define SUPER_STATE1_ASY_HEAD_OP_AWAKE 2 |
||||
#define STATE0 0x3 |
||||
#define STATE0_UPDATE_SHIFT 0 |
||||
#define STATE0_UPDATE_DEFAULT_MASK 0x1 |
||||
#define STATE1 0x4 |
||||
#define STATE1_ASY_PIXELDEPTH_SHIFT 17 |
||||
#define STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17) |
||||
#define STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17) |
||||
#define STATE1_ASY_REPLICATE_SHIFT 15 |
||||
#define STATE1_ASY_REPLICATE_DEFAULT_MASK (3 << 15) |
||||
#define STATE1_ASY_REPLICATE_OFF (0 << 15) |
||||
#define STATE1_ASY_REPLICATE_X2 (1 << 15) |
||||
#define STATE1_ASY_REPLICATE_X4 (2 << 15) |
||||
#define STATE1_ASY_DEPOL_SHIFT 14 |
||||
#define STATE1_ASY_DEPOL_DEFAULT_MASK (1 << 14) |
||||
#define STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14) |
||||
#define STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14) |
||||
#define STATE1_ASY_VSYNCPOL_SHIFT 13 |
||||
#define STATE1_ASY_VSYNCPOL_DEFAULT_MASK (1 << 13) |
||||
#define STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13) |
||||
#define STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) |
||||
#define STATE1_ASY_HSYNCPOL_SHIFT 12 |
||||
#define STATE1_ASY_HSYNCPOL_DEFAULT_MASK (1 << 12) |
||||
#define STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12) |
||||
#define STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12) |
||||
#define STATE1_ASY_PROTOCOL_SHIFT 8 |
||||
#define STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8) |
||||
#define STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8) |
||||
#define STATE1_ASY_PROTOCOL_DP_A (8 << 8) |
||||
#define STATE1_ASY_PROTOCOL_DP_B (9 << 8) |
||||
#define STATE1_ASY_PROTOCOL_CUSTOM (15 << 8) |
||||
#define STATE1_ASY_CRCMODE_SHIFT 6 |
||||
#define STATE1_ASY_CRCMODE_DEFAULT_MASK (3 << 6) |
||||
#define STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6) |
||||
#define STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6) |
||||
#define STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6) |
||||
#define STATE1_ASY_SUBOWNER_SHIFT 4 |
||||
#define STATE1_ASY_SUBOWNER_DEFAULT_MASK (3 << 4) |
||||
#define STATE1_ASY_SUBOWNER_NONE (0 << 4) |
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4) |
||||
#define STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4) |
||||
#define STATE1_ASY_SUBOWNER_BOTH (3 << 4) |
||||
#define STATE1_ASY_OWNER_SHIFT 0 |
||||
#define STATE1_ASY_OWNER_DEFAULT_MASK 0xf |
||||
#define STATE1_ASY_OWNER_NONE 0 |
||||
#define STATE1_ASY_OWNER_HEAD0 1 |
||||
#define STATE1_ASY_OWNER_HEAD1 2 |
||||
#define NV_HEAD_STATE0(i) 0x5 |
||||
#define NV_HEAD_STATE0_INTERLACED_SHIFT 4 |
||||
#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (3 << 4) |
||||
#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4) |
||||
#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4) |
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT 3 |
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (1 << 3) |
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3) |
||||
#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3) |
||||
#define NV_HEAD_STATE0_DYNRANGE_SHIFT 2 |
||||
#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (1 << 2) |
||||
#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2) |
||||
#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2) |
||||
#define NV_HEAD_STATE0_COLORSPACE_SHIFT 0 |
||||
#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK 0x3 |
||||
#define NV_HEAD_STATE0_COLORSPACE_RGB 0 |
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_601 1 |
||||
#define NV_HEAD_STATE0_COLORSPACE_YUV_709 2 |
||||
#define NV_HEAD_STATE1(i) (7 + i) |
||||
#define NV_HEAD_STATE1_VTOTAL_SHIFT 16 |
||||
#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16) |
||||
#define NV_HEAD_STATE1_HTOTAL_SHIFT 0 |
||||
#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK 0x7fff |
||||
#define NV_HEAD_STATE2(i) (9 + i) |
||||
#define NV_HEAD_STATE2_VSYNC_END_SHIFT 16 |
||||
#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16) |
||||
#define NV_HEAD_STATE2_HSYNC_END_SHIFT 0 |
||||
#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK 0x7fff |
||||
#define NV_HEAD_STATE3(i) (0xb + i) |
||||
#define NV_HEAD_STATE3_VBLANK_END_SHIFT 16 |
||||
#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16) |
||||
#define NV_HEAD_STATE3_HBLANK_END_SHIFT 0 |
||||
#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK 0x7fff |
||||
#define NV_HEAD_STATE4(i) (0xd + i) |
||||
#define NV_HEAD_STATE4_VBLANK_START_SHIFT 16 |
||||
#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) |
||||
#define NV_HEAD_STATE4_HBLANK_START_SHIFT 0 |
||||
#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK 0x7fff |
||||
#define NV_HEAD_STATE5(i) (0xf + i) |
||||
#define CRC_CNTRL 0x11 |
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_SHIFT 0 |
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_NO 0 |
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_YES 1 |
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_DIS 0 |
||||
#define CRC_CNTRL_ARM_CRC_ENABLE_EN 1 |
||||
#define CLK_CNTRL 0x13 |
||||
#define CLK_CNTRL_DP_CLK_SEL_SHIFT 0 |
||||
#define CLK_CNTRL_DP_CLK_SEL_MASK 0x3 |
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK 0 |
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK 1 |
||||
#define CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK 2 |
||||
#define CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK 3 |
||||
#define CLK_CNTRL_DP_LINK_SPEED_SHIFT 2 |
||||
#define CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) |
||||
#define CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2) |
||||
#define CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2) |
||||
#define CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2) |
||||
#define CAP 0x14 |
||||
#define CAP_DP_A_SHIFT 24 |
||||
#define CAP_DP_A_DEFAULT_MASK (1 << 24) |
||||
#define CAP_DP_A_FALSE (0 << 24) |
||||
#define CAP_DP_A_TRUE (1 << 24) |
||||
#define CAP_DP_B_SHIFT 25 |
||||
#define CAP_DP_B_DEFAULT_MASK (1 << 24) |
||||
#define CAP_DP_B_FALSE (0 << 24) |
||||
#define CAP_DP_B_TRUE (1 << 24) |
||||
#define PWR 0x15 |
||||
#define PWR_SETTING_NEW_SHIFT 31 |
||||
#define PWR_SETTING_NEW_DEFAULT_MASK (1 << 31) |
||||
#define PWR_SETTING_NEW_DONE (0 << 31) |
||||
#define PWR_SETTING_NEW_PENDING (1 << 31) |
||||
#define PWR_SETTING_NEW_TRIGGER (1 << 31) |
||||
#define PWR_MODE_SHIFT 28 |
||||
#define PWR_MODE_DEFAULT_MASK (1 << 28) |
||||
#define PWR_MODE_NORMAL (0 << 28) |
||||
#define PWR_MODE_SAFE (1 << 28) |
||||
#define PWR_HALT_DELAY_SHIFT 24 |
||||
#define PWR_HALT_DELAY_DEFAULT_MASK (1 << 24) |
||||
#define PWR_HALT_DELAY_DONE (0 << 24) |
||||
#define PWR_HALT_DELAY_ACTIVE (1 << 24) |
||||
#define PWR_SAFE_START_SHIFT 17 |
||||
#define PWR_SAFE_START_DEFAULT_MASK (1 << 17) |
||||
#define PWR_SAFE_START_NORMAL (0 << 17) |
||||
#define PWR_SAFE_START_ALT (1 << 17) |
||||
#define PWR_SAFE_STATE_SHIFT 16 |
||||
#define PWR_SAFE_STATE_DEFAULT_MASK (1 << 16) |
||||
#define PWR_SAFE_STATE_PD (0 << 16) |
||||
#define PWR_SAFE_STATE_PU (1 << 16) |
||||
#define PWR_NORMAL_START_SHIFT 1 |
||||
#define PWR_NORMAL_START_DEFAULT_MASK (1 << 1) |
||||
#define PWR_NORMAL_START_NORMAL (0 << 16) |
||||
#define PWR_NORMAL_START_ALT (1 << 16) |
||||
#define PWR_NORMAL_STATE_SHIFT 0 |
||||
#define PWR_NORMAL_STATE_DEFAULT_MASK 0x1 |
||||
#define PWR_NORMAL_STATE_PD 0 |
||||
#define PWR_NORMAL_STATE_PU 1 |
||||
#define TEST 0x16 |
||||
#define TEST_TESTMUX_SHIFT 24 |
||||
#define TEST_TESTMUX_DEFAULT_MASK (0xff << 24) |
||||
#define TEST_TESTMUX_AVSS (0 << 24) |
||||
#define TEST_TESTMUX_CLOCKIN (2 << 24) |
||||
#define TEST_TESTMUX_PLL_VOL (4 << 24) |
||||
#define TEST_TESTMUX_SLOWCLKINT (8 << 24) |
||||
#define TEST_TESTMUX_AVDD (16 << 24) |
||||
#define TEST_TESTMUX_VDDREG (32 << 24) |
||||
#define TEST_TESTMUX_REGREF_VDDREG (64 << 24) |
||||
#define TEST_TESTMUX_REGREF_AVDD (128 << 24) |
||||
#define TEST_CRC_SHIFT 23 |
||||
#define TEST_CRC_PRE_SERIALIZE (0 << 23) |
||||
#define TEST_CRC_POST_DESERIALIZE (1 << 23) |
||||
#define TEST_TPAT_SHIFT 20 |
||||
#define TEST_TPAT_DEFAULT_MASK (7 << 20) |
||||
#define TEST_TPAT_LO (0 << 20) |
||||
#define TEST_TPAT_TDAT (1 << 20) |
||||
#define TEST_TPAT_RAMP (2 << 20) |
||||
#define TEST_TPAT_WALK (3 << 20) |
||||
#define TEST_TPAT_MAXSTEP (4 << 20) |
||||
#define TEST_TPAT_MINSTEP (5 << 20) |
||||
#define TEST_DSRC_SHIFT 16 |
||||
#define TEST_DSRC_DEFAULT_MASK (3 << 16) |
||||
#define TEST_DSRC_NORMAL (0 << 16) |
||||
#define TEST_DSRC_DEBUG (1 << 16) |
||||
#define TEST_DSRC_TGEN (2 << 16) |
||||
#define TEST_HEAD_NUMBER_SHIFT 12 |
||||
#define TEST_HEAD_NUMBER_DEFAULT_MASK (3 << 12) |
||||
#define TEST_HEAD_NUMBER_NONE (0 << 12) |
||||
#define TEST_HEAD_NUMBER_HEAD0 (1 << 12) |
||||
#define TEST_HEAD_NUMBER_HEAD1 (2 << 12) |
||||
#define TEST_ATTACHED_SHIFT 10 |
||||
#define TEST_ATTACHED_DEFAULT_MASK (1 << 10) |
||||
#define TEST_ATTACHED_FALSE (0 << 10) |
||||
#define TEST_ATTACHED_TRUE (1 << 10) |
||||
#define TEST_ACT_HEAD_OPMODE_SHIFT 8 |
||||
#define TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (3 << 8) |
||||
#define TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8) |
||||
#define TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8) |
||||
#define TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8) |
||||
#define TEST_INVD_SHIFT 6 |
||||
#define TEST_INVD_DISABLE (0 << 6) |
||||
#define TEST_INVD_ENABLE (1 << 6) |
||||
#define TEST_TEST_ENABLE_SHIFT 1 |
||||
#define TEST_TEST_ENABLE_DISABLE (0 << 1) |
||||
#define TEST_TEST_ENABLE_ENABLE (1 << 1) |
||||
#define PLL0 0x17 |
||||
#define PLL0_ICHPMP_SHFIT 24 |
||||
#define PLL0_ICHPMP_DEFAULT_MASK (0xf << 24) |
||||
#define PLL0_VCOCAP_SHIFT 8 |
||||
#define PLL0_VCOCAP_DEFAULT_MASK (0xf << 8) |
||||
#define PLL0_PLLREG_LEVEL_SHIFT 6 |
||||
#define PLL0_PLLREG_LEVEL_DEFAULT_MASK (3 << 6) |
||||
#define PLL0_PLLREG_LEVEL_V25 (0 << 6) |
||||
#define PLL0_PLLREG_LEVEL_V15 (1 << 6) |
||||
#define PLL0_PLLREG_LEVEL_V35 (2 << 6) |
||||
#define PLL0_PLLREG_LEVEL_V45 (3 << 6) |
||||
#define PLL0_PULLDOWN_SHIFT 5 |
||||
#define PLL0_PULLDOWN_DEFAULT_MASK (1 << 5) |
||||
#define PLL0_PULLDOWN_DISABLE (0 << 5) |
||||
#define PLL0_PULLDOWN_ENABLE (1 << 5) |
||||
#define PLL0_RESISTORSEL_SHIFT 4 |
||||
#define PLL0_RESISTORSEL_DEFAULT_MASK (1 << 4) |
||||
#define PLL0_RESISTORSEL_INT (0 << 4) |
||||
#define PLL0_RESISTORSEL_EXT (1 << 4) |
||||
#define PLL0_VCOPD_SHIFT 2 |
||||
#define PLL0_VCOPD_MASK (1 << 2) |
||||
#define PLL0_VCOPD_RESCIND (0 << 2) |
||||
#define PLL0_VCOPD_ASSERT (1 << 2) |
||||
#define PLL0_PWR_SHIFT 0 |
||||
#define PLL0_PWR_MASK 1 |
||||
#define PLL0_PWR_ON 0 |
||||
#define PLL0_PWR_OFF 1 |
||||
#define PLL1_TMDS_TERM_SHIFT 8 |
||||
#define PLL1_TMDS_TERM_DISABLE (0 << 8) |
||||
#define PLL1_TMDS_TERM_ENABLE (1 << 8) |
||||
#define PLL1 0x18 |
||||
#define PLL1_TERM_COMPOUT_SHIFT 15 |
||||
#define PLL1_TERM_COMPOUT_LOW (0 << 15) |
||||
#define PLL1_TERM_COMPOUT_HIGH (1 << 15) |
||||
#define PLL2 0x19 |
||||
#define PLL2_DCIR_PLL_RESET_SHIFT 0 |
||||
#define PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) |
||||
#define PLL2_DCIR_PLL_RESET_ALLOW (1 << 0) |
||||
#define PLL2_AUX1_SHIFT 17 |
||||
#define PLL2_AUX1_SEQ_MASK (1 << 17) |
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17) |
||||
#define PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17) |
||||
#define PLL2_AUX2_SHIFT 18 |
||||
#define PLL2_AUX2_MASK (1 << 18) |
||||
#define PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18) |
||||
#define PLL2_AUX2_ALLOW_POWERDOWN (1 << 18) |
||||
#define PLL2_AUX6_SHIFT 22 |
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22) |
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22) |
||||
#define PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22) |
||||
#define PLL2_AUX7_SHIFT 23 |
||||
#define PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23) |
||||
#define PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23) |
||||
#define PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23) |
||||
#define PLL2_AUX8_SHIFT 24 |
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24) |
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) |
||||
#define PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) |
||||
#define PLL2_AUX9_SHIFT 25 |
||||
#define PLL2_AUX9_LVDSEN_ALLOW (0 << 25) |
||||
#define PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25) |
||||
#define PLL3 0x1a |
||||
#define PLL3_PLLVDD_MODE_SHIFT 13 |
||||
#define PLL3_PLLVDD_MODE_MASK (1 << 13) |
||||
#define PLL3_PLLVDD_MODE_V1_8 (0 << 13) |
||||
#define PLL3_PLLVDD_MODE_V3_3 (1 << 13) |
||||
#define CSTM 0x1b |
||||
#define CSTM_ROTDAT_SHIFT 28 |
||||
#define CSTM_ROTDAT_DEFAULT_MASK (7 << 28) |
||||
#define CSTM_ROTCLK_SHIFT 24 |
||||
#define CSTM_ROTCLK_DEFAULT_MASK (0xf << 24) |
||||
#define CSTM_LVDS_EN_SHIFT 16 |
||||
#define CSTM_LVDS_EN_DISABLE (0 << 16) |
||||
#define CSTM_LVDS_EN_ENABLE (1 << 16) |
||||
#define CSTM_LINKACTB_SHIFT 15 |
||||
#define CSTM_LINKACTB_DISABLE (0 << 15) |
||||
#define CSTM_LINKACTB_ENABLE (1 << 15) |
||||
#define CSTM_LINKACTA_SHIFT 14 |
||||
#define CSTM_LINKACTA_DISABLE (0 << 14) |
||||
#define CSTM_LINKACTA_ENABLE (1 << 14) |
||||
#define LVDS 0x1c |
||||
#define LVDS_ROTDAT_SHIFT 28 |
||||
#define LVDS_ROTDAT_DEFAULT_MASK (7 << 28) |
||||
#define LVDS_ROTDAT_RST (0 << 28) |
||||
#define LVDS_ROTCLK_SHIFT 24 |
||||
#define LVDS_ROTCLK_DEFAULT_MASK (0xf << 24) |
||||
#define LVDS_ROTCLK_RST (0 << 24) |
||||
#define LVDS_PLLDIV_SHIFT 21 |
||||
#define LVDS_PLLDIV_DEFAULT_MASK (1 << 21) |
||||
#define LVDS_PLLDIV_BY_7 (0 << 21) |
||||
#define LVDS_BALANCED_SHIFT 19 |
||||
#define LVDS_BALANCED_DEFAULT_MASK (1 << 19) |
||||
#define LVDS_BALANCED_DISABLE (0 << 19) |
||||
#define LVDS_BALANCED_ENABLE (1 << 19) |
||||
#define LVDS_NEW_MODE_SHIFT 18 |
||||
#define LVDS_NEW_MODE_DEFAULT_MASK (1 << 18) |
||||
#define LVDS_NEW_MODE_DISABLE (0 << 18) |
||||
#define LVDS_NEW_MODE_ENABLE (1 << 18) |
||||
#define LVDS_DUP_SYNC_SHIFT 17 |
||||
#define LVDS_DUP_SYNC_DEFAULT_MASK (1 << 17) |
||||
#define LVDS_DUP_SYNC_DISABLE (0 << 17) |
||||
#define LVDS_DUP_SYNC_ENABLE (1 << 17) |
||||
#define LVDS_LVDS_EN_SHIFT 16 |
||||
#define LVDS_LVDS_EN_DEFAULT_MASK (1 << 16) |
||||
#define LVDS_LVDS_EN_ENABLE (1 << 16) |
||||
#define LVDS_LINKACTB_SHIFT 15 |
||||
#define LVDS_LINKACTB_DEFAULT_MASK (1 << 15) |
||||
#define LVDS_LINKACTB_DISABLE (0 << 15) |
||||
#define LVDS_LINKACTB_ENABLE (1 << 15) |
||||
#define LVDS_LINKACTA_SHIFT 14 |
||||
#define LVDS_LINKACTA_DEFAULT_MASK (1 << 14) |
||||
#define LVDS_LINKACTA_ENABLE (1 << 14) |
||||
#define LVDS_MODE_SHIFT 12 |
||||
#define LVDS_MODE_DEFAULT_MASK (3 << 12) |
||||
#define LVDS_MODE_LVDS (0 << 12) |
||||
#define LVDS_UPPER_SHIFT 11 |
||||
#define LVDS_UPPER_DEFAULT_MASK (1 << 11) |
||||
#define LVDS_UPPER_FALSE (0 << 11) |
||||
#define LVDS_UPPER_TRUE (1 << 11) |
||||
#define LVDS_PD_TXCB_SHIFT 9 |
||||
#define LVDS_PD_TXCB_DEFAULT_MASK (1 << 9) |
||||
#define LVDS_PD_TXCB_ENABLE (0 << 9) |
||||
#define LVDS_PD_TXCB_DISABLE (1 << 9) |
||||
#define LVDS_PD_TXCA_SHIFT 8 |
||||
#define LVDS_PD_TXCA_DEFAULT_MASK (1 << 8) |
||||
#define LVDS_PD_TXCA_ENABLE (0 << 8) |
||||
#define LVDS_PD_TXDB_3_SHIFT 7 |
||||
#define LVDS_PD_TXDB_3_DEFAULT_MASK (1 << 7) |
||||
#define LVDS_PD_TXDB_3_ENABLE (0 << 7) |
||||
#define LVDS_PD_TXDB_3_DISABLE (1 << 7) |
||||
#define LVDS_PD_TXDB_2_SHIFT 6 |
||||
#define LVDS_PD_TXDB_2_DEFAULT_MASK (1 << 6) |
||||
#define LVDS_PD_TXDB_2_ENABLE (0 << 6) |
||||
#define LVDS_PD_TXDB_2_DISABLE (1 << 6) |
||||
#define LVDS_PD_TXDB_1_SHIFT 5 |
||||
#define LVDS_PD_TXDB_1_DEFAULT_MASK (1 << 5) |
||||
#define LVDS_PD_TXDB_1_ENABLE (0 << 5) |
||||
#define LVDS_PD_TXDB_1_DISABLE (1 << 5) |
||||
#define LVDS_PD_TXDB_0_SHIFT 4 |
||||
#define LVDS_PD_TXDB_0_DEFAULT_MASK (1 << 4) |
||||
#define LVDS_PD_TXDB_0_ENABLE (0 << 4) |
||||
#define LVDS_PD_TXDB_0_DISABLE (1 << 4) |
||||
#define LVDS_PD_TXDA_3_SHIFT 3 |
||||
#define LVDS_PD_TXDA_3_DEFAULT_MASK (1 << 3) |
||||
#define LVDS_PD_TXDA_3_ENABLE (0 << 3) |
||||
#define LVDS_PD_TXDA_3_DISABLE (1 << 3) |
||||
#define LVDS_PD_TXDA_2_SHIFT 2 |
||||
#define LVDS_PD_TXDA_2_DEFAULT_MASK (1 << 2) |
||||
#define LVDS_PD_TXDA_2_ENABLE (0 << 2) |
||||
#define LVDS_PD_TXDA_1_SHIFT 1 |
||||
#define LVDS_PD_TXDA_1_DEFAULT_MASK (1 << 1) |
||||
#define LVDS_PD_TXDA_1_ENABLE (0 << 1) |
||||
#define LVDS_PD_TXDA_0_SHIFT 0 |
||||
#define LVDS_PD_TXDA_0_DEFAULT_MASK 0x1 |
||||
#define LVDS_PD_TXDA_0_ENABLE 0 |
||||
#define CRCA 0x1d |
||||
#define CRCA_VALID_FALSE 0 |
||||
#define CRCA_VALID_TRUE 1 |
||||
#define CRCA_VALID_RST 1 |
||||
#define CRCB 0x1e |
||||
#define CRCB_CRC_DEFAULT_MASK 0xffffffff |
||||
#define SEQ_CTL 0x20 |
||||
#define SEQ_CTL_SWITCH_SHIFT 30 |
||||
#define SEQ_CTL_SWITCH_MASK (1 << 30) |
||||
#define SEQ_CTL_SWITCH_WAIT (0 << 30) |
||||
#define SEQ_CTL_SWITCH_FORCE (1 << 30) |
||||
#define SEQ_CTL_STATUS_SHIFT 28 |
||||
#define SEQ_CTL_STATUS_MASK (1 << 28) |
||||
#define SEQ_CTL_STATUS_STOPPED (0 << 28) |
||||
#define SEQ_CTL_STATUS_RUNNING (1 << 28) |
||||
#define SEQ_CTL_PC_SHIFT 16 |
||||
#define SEQ_CTL_PC_MASK (0xf << 16) |
||||
#define SEQ_CTL_PD_PC_ALT_SHIFT 12 |
||||
#define SEQ_CTL_PD_PC_ALT_MASK (0xf << 12) |
||||
#define SEQ_CTL_PD_PC_SHIFT 8 |
||||
#define SEQ_CTL_PD_PC_MASK (0xf << 8) |
||||
#define SEQ_CTL_PU_PC_ALT_SHIFT 4 |
||||
#define SEQ_CTL_PU_PC_ALT_MASK (0xf << 4) |
||||
#define SEQ_CTL_PU_PC_SHIFT 0 |
||||
#define SEQ_CTL_PU_PC_MASK 0xf |
||||
#define LANE_SEQ_CTL 0x21 |
||||
#define LANE_SEQ_CTL_SETTING_NEW_SHIFT 31 |
||||
#define LANE_SEQ_CTL_SETTING_MASK (1 << 31) |
||||
#define LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31) |
||||
#define LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31) |
||||
#define LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31) |
||||
#define LANE_SEQ_CTL_SEQ_STATE_SHIFT 28 |
||||
#define LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28) |
||||
#define LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28) |
||||
#define LANE_SEQ_CTL_SEQUENCE_SHIFT 20 |
||||
#define LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) |
||||
#define LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) |
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT 16 |
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16) |
||||
#define LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16) |
||||
#define LANE_SEQ_CTL_DELAY_SHIFT 12 |
||||
#define LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12) |
||||
#define LANE_SEQ_CTL_LANE9_STATE_SHIFT 9 |
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9) |
||||
#define LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9) |
||||
#define LANE_SEQ_CTL_LANE8_STATE_SHIFT 8 |
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8) |
||||
#define LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8) |
||||
#define LANE_SEQ_CTL_LANE7_STATE_SHIFT 7 |
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7) |
||||
#define LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7) |
||||
#define LANE_SEQ_CTL_LANE6_STATE_SHIFT 6 |
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6) |
||||
#define LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6) |
||||
#define LANE_SEQ_CTL_LANE5_STATE_SHIFT 5 |
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5) |
||||
#define LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5) |
||||
#define LANE_SEQ_CTL_LANE4_STATE_SHIFT 4 |
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4) |
||||
#define LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4) |
||||
#define LANE_SEQ_CTL_LANE3_STATE_SHIFT 3 |
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3) |
||||
#define LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3) |
||||
#define LANE_SEQ_CTL_LANE2_STATE_SHIFT 2 |
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2) |
||||
#define LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2) |
||||
#define LANE_SEQ_CTL_LANE1_STATE_SHIFT 1 |
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1) |
||||
#define LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1) |
||||
#define LANE_SEQ_CTL_LANE0_STATE_SHIFT 0 |
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERUP 0 |
||||
#define LANE_SEQ_CTL_LANE0_STATE_POWERDOWN 1 |
||||
#define SEQ_INST(i) (0x22 + i) |
||||
#define SEQ_INST_PLL_PULLDOWN_SHIFT 31 |
||||
#define SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31) |
||||
#define SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31) |
||||
#define SEQ_INST_POWERDOWN_MACRO_SHIFT 30 |
||||
#define SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30) |
||||
#define SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30) |
||||
#define SEQ_INST_ASSERT_PLL_RESET_SHIFT 29 |
||||
#define SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29) |
||||
#define SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29) |
||||
#define SEQ_INST_BLANK_V_SHIFT 28 |
||||
#define SEQ_INST_BLANK_V_NORMAL (0 << 28) |
||||
#define SEQ_INST_BLANK_V_INACTIVE (1 << 28) |
||||
#define SEQ_INST_BLANK_H_SHIFT 27 |
||||
#define SEQ_INST_BLANK_H_NORMAL (0 << 27) |
||||
#define SEQ_INST_BLANK_H_INACTIVE (1 << 27) |
||||
#define SEQ_INST_BLANK_DE_SHIFT 26 |
||||
#define SEQ_INST_BLANK_DE_NORMAL (0 << 26) |
||||
#define SEQ_INST_BLANK_DE_INACTIVE (1 << 26) |
||||
#define SEQ_INST_BLACK_DATA_SHIFT 25 |
||||
#define SEQ_INST_BLACK_DATA_NORMAL (0 << 25) |
||||
#define SEQ_INST_BLACK_DATA_BLACK (1 << 25) |
||||
#define SEQ_INST_TRISTATE_IOS_SHIFT 24 |
||||
#define SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24) |
||||
#define SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24) |
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT 23 |
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23) |
||||
#define SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23) |
||||
#define SEQ_INST_PIN_B_SHIFT 22 |
||||
#define SEQ_INST_PIN_B_LOW (0 << 22) |
||||
#define SEQ_INST_PIN_B_HIGH (1 << 22) |
||||
#define SEQ_INST_PIN_A_SHIFT 21 |
||||
#define SEQ_INST_PIN_A_LOW (0 << 21) |
||||
#define SEQ_INST_PIN_A_HIGH (1 << 21) |
||||
#define SEQ_INST_SEQUENCE_SHIFT 19 |
||||
#define SEQ_INST_SEQUENCE_UP (0 << 19) |
||||
#define SEQ_INST_SEQUENCE_DOWN (1 << 19) |
||||
#define SEQ_INST_LANE_SEQ_SHIFT 18 |
||||
#define SEQ_INST_LANE_SEQ_STOP (0 << 18) |
||||
#define SEQ_INST_LANE_SEQ_RUN (1 << 18) |
||||
#define SEQ_INST_PDPORT_SHIFT 17 |
||||
#define SEQ_INST_PDPORT_NO (0 << 17) |
||||
#define SEQ_INST_PDPORT_YES (1 << 17) |
||||
#define SEQ_INST_PDPLL_SHIFT 16 |
||||
#define SEQ_INST_PDPLL_NO (0 << 16) |
||||
#define SEQ_INST_PDPLL_YES (1 << 16) |
||||
#define SEQ_INST_HALT_SHIFT 15 |
||||
#define SEQ_INST_HALT_FALSE (0 << 15) |
||||
#define SEQ_INST_HALT_TRUE (1 << 15) |
||||
#define SEQ_INST_WAIT_UNITS_SHIFT 12 |
||||
#define SEQ_INST_WAIT_UNITS_DEFAULT_MASK (3 << 12) |
||||
#define SEQ_INST_WAIT_UNITS_US (0 << 12) |
||||
#define SEQ_INST_WAIT_UNITS_MS (1 << 12) |
||||
#define SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) |
||||
#define SEQ_INST_WAIT_TIME_SHIFT 0 |
||||
#define SEQ_INST_WAIT_TIME_DEFAULT_MASK 0x3ff |
||||
#define PWM_DIV 0x32 |
||||
#define PWM_DIV_DIVIDE_DEFAULT_MASK 0xffffff |
||||
#define PWM_CTL 0x33 |
||||
#define PWM_CTL_SETTING_NEW_SHIFT 31 |
||||
#define PWM_CTL_SETTING_NEW_DONE (0 << 31) |
||||
#define PWM_CTL_SETTING_NEW_PENDING (1 << 31) |
||||
#define PWM_CTL_SETTING_NEW_TRIGGER (1 << 31) |
||||
#define PWM_CTL_CLKSEL_SHIFT 30 |
||||
#define PWM_CTL_CLKSEL_PCLK (0 << 30) |
||||
#define PWM_CTL_CLKSEL_XTAL (1 << 30) |
||||
#define PWM_CTL_DUTY_CYCLE_SHIFT 0 |
||||
#define PWM_CTL_DUTY_CYCLE_MASK 0xffffff |
||||
#define MSCHECK 0x49 |
||||
#define MSCHECK_CTL_SHIFT 31 |
||||
#define MSCHECK_CTL_CLEAR (0 << 31) |
||||
#define MSCHECK_CTL_RUN (1 << 31) |
||||
#define XBAR_CTRL 0x4a |
||||
#define DP_LINKCTL(i) (0x4c + (i)) |
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT 31 |
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31) |
||||
#define DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31) |
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_SHIFT 28 |
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28) |
||||
#define DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) |
||||
#define DP_LINKCTL_LANECOUNT_SHIFT 16 |
||||
#define DP_LINKCTL_LANECOUNT_MASK (0x1f << 16) |
||||
#define DP_LINKCTL_LANECOUNT_ZERO (0 << 16) |
||||
#define DP_LINKCTL_LANECOUNT_ONE (1 << 16) |
||||
#define DP_LINKCTL_LANECOUNT_TWO (3 << 16) |
||||
#define DP_LINKCTL_LANECOUNT_FOUR (15 << 16) |
||||
#define DP_LINKCTL_ENHANCEDFRAME_SHIFT 14 |
||||
#define DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14) |
||||
#define DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14) |
||||
#define DP_LINKCTL_SYNCMODE_SHIFT 10 |
||||
#define DP_LINKCTL_SYNCMODE_DISABLE (0 << 10) |
||||
#define DP_LINKCTL_SYNCMODE_ENABLE (1 << 10) |
||||
#define DP_LINKCTL_TUSIZE_SHIFT 2 |
||||
#define DP_LINKCTL_TUSIZE_MASK (0x7f << 2) |
||||
#define DP_LINKCTL_ENABLE_SHIFT 0 |
||||
#define DP_LINKCTL_ENABLE_NO 0 |
||||
#define DP_LINKCTL_ENABLE_YES 1 |
||||
#define DC(i) (0x4e + (i)) |
||||
#define DC_LANE3_DP_LANE3_SHIFT 24 |
||||
#define DC_LANE3_DP_LANE3_MASK (0xff << 24) |
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24) |
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24) |
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24) |
||||
#define DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24) |
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24) |
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24) |
||||
#define DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24) |
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24) |
||||
#define DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24) |
||||
#define DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24) |
||||
#define DC_LANE2_DP_LANE0_SHIFT 16 |
||||
#define DC_LANE2_DP_LANE0_MASK (0xff << 16) |
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16) |
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16) |
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16) |
||||
#define DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16) |
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16) |
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16) |
||||
#define DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16) |
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16) |
||||
#define DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16) |
||||
#define DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16) |
||||
#define DC_LANE1_DP_LANE1_SHIFT 8 |
||||
#define DC_LANE1_DP_LANE1_MASK (0xff << 8) |
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8) |
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8) |
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8) |
||||
#define DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8) |
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8) |
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8) |
||||
#define DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8) |
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8) |
||||
#define DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8) |
||||
#define DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8) |
||||
#define DC_LANE0_DP_LANE2_SHIFT 0 |
||||
#define DC_LANE0_DP_LANE2_MASK 0xff |
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL0 17 |
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL0 21 |
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL0 26 |
||||
#define DC_LANE0_DP_LANE2_P3_LEVEL0 34 |
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL1 26 |
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL1 32 |
||||
#define DC_LANE0_DP_LANE2_P2_LEVEL1 39 |
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL2 34 |
||||
#define DC_LANE0_DP_LANE2_P1_LEVEL2 43 |
||||
#define DC_LANE0_DP_LANE2_P0_LEVEL3 51 |
||||
#define LANE_DRIVE_CURRENT(i) (0x4e + (i)) |
||||
#define PR(i) (0x52 + (i)) |
||||
#define PR_LANE3_DP_LANE3_SHIFT 24 |
||||
#define PR_LANE3_DP_LANE3_MASK (0xff << 24) |
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24) |
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24) |
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24) |
||||
#define PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24) |
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24) |
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24) |
||||
#define PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24) |
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24) |
||||
#define PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24) |
||||
#define PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24) |
||||
#define PR_LANE2_DP_LANE0_SHIFT 16 |
||||
#define PR_LANE2_DP_LANE0_MASK (0xff << 16) |
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16) |
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16) |
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16) |
||||
#define PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16) |
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16) |
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16) |
||||
#define PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16) |
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16) |
||||
#define PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16) |
||||
#define PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16) |
||||
#define PR_LANE1_DP_LANE1_SHIFT 8 |
||||
#define PR_LANE1_DP_LANE1_MASK (0xff >> 8) |
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8) |
||||
#define PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8) |
||||
#define PR_LANE0_DP_LANE2_SHIFT 0 |
||||
#define PR_LANE0_DP_LANE2_MASK 0xff |
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL0 0 |
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL0 0 |
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL0 0 |
||||
#define PR_LANE0_DP_LANE2_D3_LEVEL0 0 |
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL1 4 |
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL1 6 |
||||
#define PR_LANE0_DP_LANE2_D2_LEVEL1 17 |
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL2 8 |
||||
#define PR_LANE0_DP_LANE2_D1_LEVEL2 13 |
||||
#define PR_LANE0_DP_LANE2_D0_LEVEL3 17 |
||||
#define LANE4_PREEMPHASIS(i) (0x54 + (i)) |
||||
#define POSTCURSOR(i) (0x56 + (i)) |
||||
#define DP_CONFIG(i) (0x58 + (i)) |
||||
#define DP_CONFIG_RD_RESET_VAL_SHIFT 31 |
||||
#define DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31) |
||||
#define DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31) |
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT 28 |
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28) |
||||
#define DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28) |
||||
#define DP_CONFIG_ACTIVESYM_CNTL_SHIFT 26 |
||||
#define DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26) |
||||
#define DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26) |
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_SHIFT 24 |
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) |
||||
#define DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) |
||||
#define DP_CONFIG_ACTIVESYM_FRAC_SHIFT 16 |
||||
#define DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16) |
||||
#define DP_CONFIG_ACTIVESYM_COUNT_SHIFT 8 |
||||
#define DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8) |
||||
#define DP_CONFIG_WATERMARK_SHIFT 0 |
||||
#define DP_CONFIG_WATERMARK_MASK 0x3f |
||||
#define DP_MN(i) (0x5a + i) |
||||
#define DP_MN_M_MOD_SHIFT 30 |
||||
#define DP_MN_M_MOD_DEFAULT_MASK (3 << 30) |
||||
#define DP_MN_M_MOD_NONE (0 << 30) |
||||
#define DP_MN_M_MOD_INC (1 << 30) |
||||
#define DP_MN_M_MOD_DEC (2 << 30) |
||||
#define DP_MN_M_DELTA_SHIFT 24 |
||||
#define DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24) |
||||
#define DP_MN_N_VAL_SHIFT 0 |
||||
#define DP_MN_N_VAL_DEFAULT_MASK 0xffffff |
||||
#define DP_PADCTL(i) (0x5c + (i)) |
||||
#define DP_PADCTL_SPARE_SHIFT 25 |
||||
#define DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25) |
||||
#define DP_PADCTL_VCO_2X_SHIFT 24 |
||||
#define DP_PADCTL_VCO_2X_DISABLE (0 << 24) |
||||
#define DP_PADCTL_VCO_2X_ENABLE (1 << 24) |
||||
#define DP_PADCTL_PAD_CAL_PD_SHIFT 23 |
||||
#define DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23) |
||||
#define DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23) |
||||
#define DP_PADCTL_TX_PU_SHIFT 22 |
||||
#define DP_PADCTL_TX_PU_DISABLE (0 << 22) |
||||
#define DP_PADCTL_TX_PU_ENABLE (1 << 22) |
||||
#define DP_PADCTL_TX_PU_MASK (1 << 22) |
||||
#define DP_PADCTL_REG_CTRL_SHIFT 20 |
||||
#define DP_PADCTL_REG_CTRL_DEFAULT_MASK (3 << 20) |
||||
#define DP_PADCTL_VCMMODE_SHIFT 16 |
||||
#define DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16) |
||||
#define DP_PADCTL_VCMMODE_TRISTATE (0 << 16) |
||||
#define DP_PADCTL_VCMMODE_TEST_MUX (1 << 16) |
||||
#define DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) |
||||
#define DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) |
||||
#define DP_PADCTL_TX_PU_VALUE_SHIFT 8 |
||||
#define DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) |
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT 7 |
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) |
||||
#define DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) |
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT 6 |
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) |
||||
#define DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) |
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT 5 |
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) |
||||
#define DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) |
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT 4 |
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) |
||||
#define DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) |
||||
#define DP_PADCTL_PD_TXD_3_SHIFT 3 |
||||
#define DP_PADCTL_PD_TXD_3_YES (0 << 3) |
||||
#define DP_PADCTL_PD_TXD_3_NO (1 << 3) |
||||
#define DP_PADCTL_PD_TXD_0_SHIFT 2 |
||||
#define DP_PADCTL_PD_TXD_0_YES (0 << 2) |
||||
#define DP_PADCTL_PD_TXD_0_NO (1 << 2) |
||||
#define DP_PADCTL_PD_TXD_1_SHIFT 1 |
||||
#define DP_PADCTL_PD_TXD_1_YES (0 << 1) |
||||
#define DP_PADCTL_PD_TXD_1_NO (1 << 1) |
||||
#define DP_PADCTL_PD_TXD_2_SHIFT 0 |
||||
#define DP_PADCTL_PD_TXD_2_YES 0 |
||||
#define DP_PADCTL_PD_TXD_2_NO 1 |
||||
#define DP_DEBUG(i) (0x5e + i) |
||||
#define DP_SPARE(i) (0x60 + (i)) |
||||
#define DP_SPARE_REG_SHIFT 3 |
||||
#define DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3) |
||||
#define DP_SPARE_SOR_CLK_SEL_SHIFT 2 |
||||
#define DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (1 << 2) |
||||
#define DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2) |
||||
#define DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2) |
||||
#define DP_SPARE_PANEL_SHIFT 1 |
||||
#define DP_SPARE_PANEL_EXTERNAL (0 << 1) |
||||
#define DP_SPARE_PANEL_INTERNAL (1 << 1) |
||||
#define DP_SPARE_SEQ_ENABLE_SHIFT 0 |
||||
#define DP_SPARE_SEQ_ENABLE_NO 0 |
||||
#define DP_SPARE_SEQ_ENABLE_YES 1 |
||||
#define DP_AUDIO_CTRL 0x62 |
||||
#define DP_AUDIO_HBLANK_SYMBOLS 0x63 |
||||
#define DP_AUDIO_HBLANK_SYMBOLS_MASK 0x1ffff |
||||
#define DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT 0 |
||||
#define DP_AUDIO_VBLANK_SYMBOLS 0x64 |
||||
#define DP_AUDIO_VBLANK_SYMBOLS_MASK 0x1ffff |
||||
#define DP_AUDIO_VBLANK_SYMBOLS_SHIFT 0 |
||||
#define DP_GENERIC_INFOFRAME_HEADER 0x65 |
||||
#define DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i)) |
||||
#define DP_TPG 0x6d |
||||
#define DP_TPG_LANE3_CHANNELCODING_SHIFT 30 |
||||
#define DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30) |
||||
#define DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30) |
||||
#define DP_TPG_LANE3_SCRAMBLEREN_SHIFT 28 |
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) |
||||
#define DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) |
||||
#define DP_TPG_LANE3_PATTERN_SHIFT 24 |
||||
#define DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24) |
||||
#define DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_D102 (4 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_CSTM (7 << 24) |
||||
#define DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24) |
||||
#define DP_TPG_LANE2_CHANNELCODING_SHIFT 22 |
||||
#define DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22) |
||||
#define DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22) |
||||
#define DP_TPG_LANE2_SCRAMBLEREN_SHIFT 20 |
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (3 << 20) |
||||
#define DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20) |
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) |
||||
#define DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) |
||||
#define DP_TPG_LANE2_PATTERN_SHIFT 16 |
||||
#define DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16) |
||||
#define DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_D102 (4 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_CSTM (7 << 16) |
||||
#define DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16) |
||||
#define DP_TPG_LANE1_CHANNELCODING_SHIFT 14 |
||||
#define DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14) |
||||
#define DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14) |
||||
#define DP_TPG_LANE1_SCRAMBLEREN_SHIFT 12 |
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (3 << 12) |
||||
#define DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12) |
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) |
||||
#define DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) |
||||
#define DP_TPG_LANE1_PATTERN_SHIFT 8 |
||||
#define DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8) |
||||
#define DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_D102 (4 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_CSTM (7 << 8) |
||||
#define DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8) |
||||
#define DP_TPG_LANE0_CHANNELCODING_SHIFT 6 |
||||
#define DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6) |
||||
#define DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6) |
||||
#define DP_TPG_LANE0_SCRAMBLEREN_SHIFT 4 |
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (3 << 4) |
||||
#define DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4) |
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) |
||||
#define DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) |
||||
#define DP_TPG_LANE0_PATTERN_SHIFT 0 |
||||
#define DP_TPG_LANE0_PATTERN_DEFAULT_MASK 0xf |
||||
#define DP_TPG_LANE0_PATTERN_NOPATTERN 0 |
||||
#define DP_TPG_LANE0_PATTERN_TRAINING1 1 |
||||
#define DP_TPG_LANE0_PATTERN_TRAINING2 2 |
||||
#define DP_TPG_LANE0_PATTERN_TRAINING3 3 |
||||
#define DP_TPG_LANE0_PATTERN_D102 4 |
||||
#define DP_TPG_LANE0_PATTERN_SBLERRRATE 5 |
||||
#define DP_TPG_LANE0_PATTERN_PRBS7 6 |
||||
#define DP_TPG_LANE0_PATTERN_CSTM 7 |
||||
#define DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 8 |
||||
|
||||
enum { |
||||
training_pattern_disabled = 0, |
||||
training_pattern_1 = 1, |
||||
training_pattern_2 = 2, |
||||
training_pattern_3 = 3, |
||||
training_pattern_none = 0xff |
||||
}; |
||||
|
||||
enum tegra_dc_sor_protocol { |
||||
SOR_DP, |
||||
SOR_LVDS, |
||||
}; |
||||
|
||||
#define SOR_LINK_SPEED_G1_62 6 |
||||
#define SOR_LINK_SPEED_G2_7 10 |
||||
#define SOR_LINK_SPEED_G5_4 20 |
||||
#define SOR_LINK_SPEED_LVDS 7 |
||||
|
||||
struct tegra_dp_link_config { |
||||
int is_valid; |
||||
|
||||
/* Supported configuration */ |
||||
u8 max_link_bw; |
||||
u8 max_lane_count; |
||||
int downspread; |
||||
int support_enhanced_framing; |
||||
u32 bits_per_pixel; |
||||
int alt_scramber_reset_cap; /* true for eDP */ |
||||
int only_enhanced_framing; /* enhanced_frame_en ignored */ |
||||
int frame_in_ms; |
||||
|
||||
/* Actual configuration */ |
||||
u8 link_bw; |
||||
u8 lane_count; |
||||
int enhanced_framing; |
||||
int scramble_ena; |
||||
|
||||
u32 activepolarity; |
||||
u32 active_count; |
||||
u32 tu_size; |
||||
u32 active_frac; |
||||
u32 watermark; |
||||
|
||||
s32 hblank_sym; |
||||
s32 vblank_sym; |
||||
|
||||
/* Training data */ |
||||
u32 drive_current; |
||||
u32 preemphasis; |
||||
u32 postcursor; |
||||
u8 aux_rd_interval; |
||||
u8 tps3_supported; |
||||
}; |
||||
|
||||
struct tegra_dc_sor_data { |
||||
void *base; |
||||
void *pmc_base; |
||||
u8 portnum; /* 0 or 1 */ |
||||
int power_is_up; |
||||
}; |
||||
|
||||
#define TEGRA_SOR_TIMEOUT_MS 1000 |
||||
#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000 |
||||
|
||||
int tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *link_cfg); |
||||
int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd); |
||||
void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, |
||||
u8 training_pattern, const struct tegra_dp_link_config *link_cfg); |
||||
void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw); |
||||
void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count); |
||||
void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, |
||||
int power_up); |
||||
void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int); |
||||
void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, |
||||
u8 *lane_count); |
||||
void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *link_cfg); |
||||
void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *link_cfg); |
||||
int tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *link_cfg); |
||||
int tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *cfg); |
||||
void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); |
||||
void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, |
||||
u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); |
||||
|
||||
int tegra_dc_sor_attach(struct tegra_dc_sor_data *sor, |
||||
const struct tegra_dp_link_config *link_cfg, |
||||
const struct display_timing *timing); |
||||
int tegra_dc_sor_detach(struct tegra_dc_sor_data *sor); |
||||
|
||||
void tegra_dc_sor_disable_win_short_raster(struct dc_ctlr *disp_ctrl, |
||||
int *dc_reg_ctx); |
||||
int tegra_dc_sor_general_act(struct dc_ctlr *disp_ctrl); |
||||
void tegra_dc_sor_restore_win_and_raster(struct dc_ctlr *disp_ctrl, |
||||
int *dc_reg_ctx); |
||||
|
||||
int tegra_dc_sor_init(struct tegra_dc_sor_data **sorp); |
||||
#endif |
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright 2014 Google Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <lcd.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/arch-tegra/clk_rst.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch-tegra/dc.h> |
||||
#include <asm/io.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
enum { |
||||
/* Maximum LCD size we support */ |
||||
LCD_MAX_WIDTH = 1920, |
||||
LCD_MAX_HEIGHT = 1200, |
||||
LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ |
||||
}; |
||||
|
||||
vidinfo_t panel_info = { |
||||
/* Insert a value here so that we don't end up in the BSS */ |
||||
.vl_col = -1, |
||||
}; |
||||
|
||||
int tegra_lcd_check_next_stage(const void *blob, int wait) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void tegra_lcd_early_init(const void *blob) |
||||
{ |
||||
/*
|
||||
* Go with the maximum size for now. We will fix this up after |
||||
* relocation. These values are only used for memory alocation. |
||||
*/ |
||||
panel_info.vl_col = LCD_MAX_WIDTH; |
||||
panel_info.vl_row = LCD_MAX_HEIGHT; |
||||
panel_info.vl_bpix = LCD_MAX_LOG2_BPP; |
||||
} |
||||
|
||||
static int tegra124_lcd_init(void *lcdbase) |
||||
{ |
||||
struct display_timing timing; |
||||
int ret; |
||||
|
||||
clock_set_up_plldp(); |
||||
clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, |
||||
408000000, NULL); |
||||
|
||||
clock_enable(PERIPH_ID_HOST1X); |
||||
clock_enable(PERIPH_ID_DISP1); |
||||
clock_enable(PERIPH_ID_PWM); |
||||
clock_enable(PERIPH_ID_DPAUX); |
||||
clock_enable(PERIPH_ID_SOR0); |
||||
|
||||
udelay(2); |
||||
|
||||
reset_set_enable(PERIPH_ID_HOST1X, 0); |
||||
reset_set_enable(PERIPH_ID_DISP1, 0); |
||||
reset_set_enable(PERIPH_ID_PWM, 0); |
||||
reset_set_enable(PERIPH_ID_DPAUX, 0); |
||||
reset_set_enable(PERIPH_ID_SOR0, 0); |
||||
|
||||
ret = display_init(lcdbase, 1 << LCD_BPP, &timing); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
panel_info.vl_col = roundup(timing.hactive.typ, 16); |
||||
panel_info.vl_row = timing.vactive.typ; |
||||
|
||||
lcd_set_flush_dcache(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void lcd_ctrl_init(void *lcdbase) |
||||
{ |
||||
ulong start; |
||||
int ret; |
||||
|
||||
start = get_timer(0); |
||||
ret = tegra124_lcd_init(lcdbase); |
||||
debug("LCD init took %lu ms\n", get_timer(start)); |
||||
if (ret) |
||||
printf("%s: Error %d\n", __func__, ret); |
||||
} |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
} |
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright 2014 Google Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _DISPLAYPORT_H |
||||
#define _DISPLAYPORT_H |
||||
|
||||
struct udevice; |
||||
struct display_timing; |
||||
|
||||
/**
|
||||
* display_port_read_edid() - Read information from EDID |
||||
* |
||||
* @dev: Device to read from |
||||
* @buf: Buffer to read into (should be EDID_SIZE bytes) |
||||
* @buf_size: Buffer size (should be EDID_SIZE) |
||||
* @return number of bytes read, <=0 for error |
||||
*/ |
||||
int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size); |
||||
|
||||
/**
|
||||
* display_port_enable() - Enable a display port device |
||||
* |
||||
* @dev: Device to enable |
||||
* @panel_bpp: Number of bits per pixel for panel |
||||
* @timing: Display timings |
||||
* @return 0 if OK, -ve on error |
||||
*/ |
||||
int display_port_enable(struct udevice *dev, int panel_bpp, |
||||
const struct display_timing *timing); |
||||
|
||||
struct dm_display_port_ops { |
||||
/**
|
||||
* read_edid() - Read information from EDID |
||||
* |
||||
* @dev: Device to read from |
||||
* @buf: Buffer to read into (should be EDID_SIZE bytes) |
||||
* @buf_size: Buffer size (should be EDID_SIZE) |
||||
* @return number of bytes read, <=0 for error |
||||
*/ |
||||
int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size); |
||||
|
||||
/**
|
||||
* enable() - Enable the display port device |
||||
* |
||||
* @dev: Device to enable |
||||
* @panel_bpp: Number of bits per pixel for panel |
||||
* @timing: Display timings |
||||
* @return 0 if OK, -ve on error |
||||
*/ |
||||
int (*enable)(struct udevice *dev, int panel_bpp, |
||||
const struct display_timing *timing); |
||||
}; |
||||
|
||||
#define display_port_get_ops(dev) \ |
||||
((struct dm_display_port_ops *)(dev)->driver->ops) |
||||
|
||||
#endif |
@ -0,0 +1,406 @@ |
||||
/*
|
||||
* Copyright © 2008 Keith Packard |
||||
* |
||||
* Permission to use, copy, modify, distribute, and sell this software and its |
||||
* documentation for any purpose is hereby granted without fee, provided that |
||||
* the above copyright notice appear in all copies and that both that copyright |
||||
* notice and this permission notice appear in supporting documentation, and |
||||
* that the name of the copyright holders not be used in advertising or |
||||
* publicity pertaining to distribution of the software without specific, |
||||
* written prior permission. The copyright holders make no representations |
||||
* about the suitability of this software for any purpose. It is provided "as |
||||
* is" without express or implied warranty. |
||||
* |
||||
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
||||
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
||||
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
||||
* OF THIS SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _DRM_DP_HELPER_H_ |
||||
#define _DRM_DP_HELPER_H_ |
||||
|
||||
/*
|
||||
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
||||
* DP and DPCD versions are independent. Differences from 1.0 are not noted, |
||||
* 1.0 devices basically don't exist in the wild. |
||||
* |
||||
* Abbreviations, in chronological order: |
||||
* |
||||
* eDP: Embedded DisplayPort version 1 |
||||
* DPI: DisplayPort Interoperability Guideline v1.1a |
||||
* 1.2: DisplayPort 1.2 |
||||
* MST: Multistream Transport - part of DP 1.2a |
||||
* |
||||
* 1.2 formally includes both eDP and DPI definitions. |
||||
*/ |
||||
|
||||
#define DP_AUX_I2C_WRITE 0x0 |
||||
#define DP_AUX_I2C_READ 0x1 |
||||
#define DP_AUX_I2C_STATUS 0x2 |
||||
#define DP_AUX_I2C_MOT 0x4 |
||||
#define DP_AUX_NATIVE_WRITE 0x8 |
||||
#define DP_AUX_NATIVE_READ 0x9 |
||||
|
||||
#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
||||
#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
||||
#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
||||
#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
||||
|
||||
#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
||||
#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
||||
#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
||||
#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
||||
|
||||
/* AUX CH addresses */ |
||||
/* DPCD */ |
||||
#define DP_DPCD_REV 0x000 |
||||
|
||||
#define DP_MAX_LINK_RATE 0x001 |
||||
|
||||
#define DP_MAX_LANE_COUNT 0x002 |
||||
# define DP_MAX_LANE_COUNT_MASK 0x1f |
||||
# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
||||
# define DP_ENHANCED_FRAME_CAP (1 << 7) |
||||
|
||||
#define DP_MAX_DOWNSPREAD 0x003 |
||||
# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
||||
|
||||
#define DP_NORP 0x004 |
||||
|
||||
#define DP_DOWNSTREAMPORT_PRESENT 0x005 |
||||
# define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
||||
# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
||||
# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
||||
# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
||||
# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
||||
# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
||||
# define DP_FORMAT_CONVERSION (1 << 3) |
||||
# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
||||
|
||||
#define DP_DOWN_STREAM_PORT_COUNT 0x007 |
||||
# define DP_PORT_COUNT_MASK 0x0f |
||||
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
||||
# define DP_OUI_SUPPORT (1 << 7) |
||||
|
||||
#define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
||||
# define DP_I2C_SPEED_1K 0x01 |
||||
# define DP_I2C_SPEED_5K 0x02 |
||||
# define DP_I2C_SPEED_10K 0x04 |
||||
# define DP_I2C_SPEED_100K 0x08 |
||||
# define DP_I2C_SPEED_400K 0x10 |
||||
# define DP_I2C_SPEED_1M 0x20 |
||||
|
||||
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
||||
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
||||
|
||||
/* Multiple stream transport */ |
||||
#define DP_FAUX_CAP 0x020 /* 1.2 */ |
||||
# define DP_FAUX_CAP_1 (1 << 0) |
||||
|
||||
#define DP_MSTM_CAP 0x021 /* 1.2 */ |
||||
# define DP_MST_CAP (1 << 0) |
||||
|
||||
#define DP_GUID 0x030 /* 1.2 */ |
||||
|
||||
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
||||
# define DP_PSR_IS_SUPPORTED 1 |
||||
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
||||
# define DP_PSR_NO_TRAIN_ON_EXIT 1 |
||||
# define DP_PSR_SETUP_TIME_330 (0 << 1) |
||||
# define DP_PSR_SETUP_TIME_275 (1 << 1) |
||||
# define DP_PSR_SETUP_TIME_220 (2 << 1) |
||||
# define DP_PSR_SETUP_TIME_165 (3 << 1) |
||||
# define DP_PSR_SETUP_TIME_110 (4 << 1) |
||||
# define DP_PSR_SETUP_TIME_55 (5 << 1) |
||||
# define DP_PSR_SETUP_TIME_0 (6 << 1) |
||||
# define DP_PSR_SETUP_TIME_MASK (7 << 1) |
||||
# define DP_PSR_SETUP_TIME_SHIFT 1 |
||||
|
||||
/*
|
||||
* 0x80-0x8f describe downstream port capabilities, but there are two layouts |
||||
* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
||||
* each port's descriptor is one byte wide. If it was set, each port's is |
||||
* four bytes wide, starting with the one byte from the base info. As of |
||||
* DP interop v1.1a only VGA defines additional detail. |
||||
*/ |
||||
|
||||
/* offset 0 */ |
||||
#define DP_DOWNSTREAM_PORT_0 0x80 |
||||
# define DP_DS_PORT_TYPE_MASK (7 << 0) |
||||
# define DP_DS_PORT_TYPE_DP 0 |
||||
# define DP_DS_PORT_TYPE_VGA 1 |
||||
# define DP_DS_PORT_TYPE_DVI 2 |
||||
# define DP_DS_PORT_TYPE_HDMI 3 |
||||
# define DP_DS_PORT_TYPE_NON_EDID 4 |
||||
# define DP_DS_PORT_HPD (1 << 3) |
||||
/* offset 1 for VGA is maximum megapixels per second / 8 */ |
||||
/* offset 2 */ |
||||
# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
||||
# define DP_DS_VGA_8BPC 0 |
||||
# define DP_DS_VGA_10BPC 1 |
||||
# define DP_DS_VGA_12BPC 2 |
||||
# define DP_DS_VGA_16BPC 3 |
||||
|
||||
/* link configuration */ |
||||
#define DP_LINK_BW_SET 0x100 |
||||
# define DP_LINK_BW_1_62 0x06 |
||||
# define DP_LINK_BW_2_7 0x0a |
||||
# define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
||||
|
||||
#define DP_LANE_COUNT_SET 0x101 |
||||
# define DP_LANE_COUNT_MASK 0x0f |
||||
# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
||||
|
||||
#define DP_TRAINING_PATTERN_SET 0x102 |
||||
# define DP_TRAINING_PATTERN_DISABLE 0 |
||||
# define DP_TRAINING_PATTERN_1 1 |
||||
# define DP_TRAINING_PATTERN_2 2 |
||||
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
||||
# define DP_TRAINING_PATTERN_MASK 0x3 |
||||
|
||||
# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
||||
# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) |
||||
# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) |
||||
# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) |
||||
# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) |
||||
|
||||
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
||||
# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
||||
|
||||
# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
||||
# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
||||
# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
||||
# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
||||
|
||||
#define DP_TRAINING_LANE0_SET 0x103 |
||||
#define DP_TRAINING_LANE1_SET 0x104 |
||||
#define DP_TRAINING_LANE2_SET 0x105 |
||||
#define DP_TRAINING_LANE3_SET 0x106 |
||||
|
||||
# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
||||
# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
||||
# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
||||
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) |
||||
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) |
||||
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) |
||||
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) |
||||
|
||||
# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
||||
# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) |
||||
# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) |
||||
# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) |
||||
# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) |
||||
|
||||
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
||||
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
||||
|
||||
#define DP_DOWNSPREAD_CTRL 0x107 |
||||
# define DP_SPREAD_AMP_0_5 (1 << 4) |
||||
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
||||
# define DP_SET_ANSI_8B10B (1 << 0) |
||||
|
||||
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
||||
/* bitmask as for DP_I2C_SPEED_CAP */ |
||||
|
||||
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
||||
|
||||
#define DP_MSTM_CTRL 0x111 /* 1.2 */ |
||||
# define DP_MST_EN (1 << 0) |
||||
# define DP_UP_REQ_EN (1 << 1) |
||||
# define DP_UPSTREAM_IS_SRC (1 << 2) |
||||
|
||||
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
||||
# define DP_PSR_ENABLE (1 << 0) |
||||
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
||||
# define DP_PSR_CRC_VERIFICATION (1 << 2) |
||||
# define DP_PSR_FRAME_CAPTURE (1 << 3) |
||||
|
||||
#define DP_ADAPTER_CTRL 0x1a0 |
||||
# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) |
||||
|
||||
#define DP_BRANCH_DEVICE_CTRL 0x1a1 |
||||
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) |
||||
|
||||
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 |
||||
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 |
||||
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 |
||||
|
||||
#define DP_SINK_COUNT 0x200 |
||||
/* prior to 1.2 bit 7 was reserved mbz */ |
||||
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
||||
# define DP_SINK_CP_READY (1 << 6) |
||||
|
||||
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
||||
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
||||
# define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
||||
# define DP_CP_IRQ (1 << 2) |
||||
# define DP_MCCS_IRQ (1 << 3) |
||||
# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ |
||||
# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ |
||||
# define DP_SINK_SPECIFIC_IRQ (1 << 6) |
||||
|
||||
#define DP_LANE0_1_STATUS 0x202 |
||||
#define DP_LANE2_3_STATUS 0x203 |
||||
# define DP_LANE_CR_DONE (1 << 0) |
||||
# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
||||
# define DP_LANE_SYMBOL_LOCKED (1 << 2) |
||||
|
||||
#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
||||
DP_LANE_CHANNEL_EQ_DONE | \
|
||||
DP_LANE_SYMBOL_LOCKED) |
||||
|
||||
#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
||||
|
||||
#define DP_INTERLANE_ALIGN_DONE (1 << 0) |
||||
#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
||||
#define DP_LINK_STATUS_UPDATED (1 << 7) |
||||
|
||||
#define DP_SINK_STATUS 0x205 |
||||
#define DP_SINK_STATUS_PORT0_IN_SYNC (1 << 0) |
||||
|
||||
#define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
||||
#define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
||||
|
||||
#define DP_ADJUST_REQUEST_LANE0_1 0x206 |
||||
#define DP_ADJUST_REQUEST_LANE2_3 0x207 |
||||
# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
||||
# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
||||
# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
||||
# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
||||
|
||||
#define DP_TEST_REQUEST 0x218 |
||||
# define DP_TEST_LINK_TRAINING (1 << 0) |
||||
# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
||||
# define DP_TEST_LINK_EDID_READ (1 << 2) |
||||
# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
||||
# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
||||
|
||||
#define DP_TEST_LINK_RATE 0x219 |
||||
# define DP_LINK_RATE_162 (0x6) |
||||
# define DP_LINK_RATE_27 (0xa) |
||||
|
||||
#define DP_TEST_LANE_COUNT 0x220 |
||||
|
||||
#define DP_TEST_PATTERN 0x221 |
||||
|
||||
#define DP_TEST_CRC_R_CR 0x240 |
||||
#define DP_TEST_CRC_G_Y 0x242 |
||||
#define DP_TEST_CRC_B_CB 0x244 |
||||
|
||||
#define DP_TEST_SINK_MISC 0x246 |
||||
#define DP_TEST_CRC_SUPPORTED (1 << 5) |
||||
|
||||
#define DP_TEST_RESPONSE 0x260 |
||||
# define DP_TEST_ACK (1 << 0) |
||||
# define DP_TEST_NAK (1 << 1) |
||||
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
||||
|
||||
#define DP_TEST_EDID_CHECKSUM 0x261 |
||||
|
||||
#define DP_TEST_SINK 0x270 |
||||
#define DP_TEST_SINK_START (1 << 0) |
||||
|
||||
#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
||||
# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) |
||||
# define DP_PAYLOAD_ACT_HANDLED (1 << 1) |
||||
|
||||
#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ |
||||
/* up to ID_SLOT_63 at 0x2ff */ |
||||
|
||||
#define DP_SOURCE_OUI 0x300 |
||||
#define DP_SINK_OUI 0x400 |
||||
#define DP_BRANCH_OUI 0x500 |
||||
|
||||
#define DP_SET_POWER 0x600 |
||||
# define DP_SET_POWER_D0 0x1 |
||||
# define DP_SET_POWER_D3 0x2 |
||||
# define DP_SET_POWER_MASK 0x3 |
||||
|
||||
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
||||
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
||||
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
||||
#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ |
||||
|
||||
#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ |
||||
/* 0-5 sink count */ |
||||
# define DP_SINK_COUNT_CP_READY (1 << 6) |
||||
|
||||
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ |
||||
|
||||
#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ |
||||
|
||||
#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ |
||||
|
||||
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
||||
# define DP_PSR_LINK_CRC_ERROR (1 << 0) |
||||
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
||||
|
||||
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
||||
# define DP_PSR_CAPS_CHANGE (1 << 0) |
||||
|
||||
#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
||||
# define DP_PSR_SINK_INACTIVE 0 |
||||
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
||||
# define DP_PSR_SINK_ACTIVE_RFB 2 |
||||
# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
||||
# define DP_PSR_SINK_ACTIVE_RESYNC 4 |
||||
# define DP_PSR_SINK_INTERNAL_ERROR 7 |
||||
# define DP_PSR_SINK_STATE_MASK 0x07 |
||||
|
||||
/* DP 1.2 Sideband message defines */ |
||||
/* peer device type - DP 1.2a Table 2-92 */ |
||||
#define DP_PEER_DEVICE_NONE 0x0 |
||||
#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 |
||||
#define DP_PEER_DEVICE_MST_BRANCHING 0x2 |
||||
#define DP_PEER_DEVICE_SST_SINK 0x3 |
||||
#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 |
||||
|
||||
/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ |
||||
#define DP_LINK_ADDRESS 0x01 |
||||
#define DP_CONNECTION_STATUS_NOTIFY 0x02 |
||||
#define DP_ENUM_PATH_RESOURCES 0x10 |
||||
#define DP_ALLOCATE_PAYLOAD 0x11 |
||||
#define DP_QUERY_PAYLOAD 0x12 |
||||
#define DP_RESOURCE_STATUS_NOTIFY 0x13 |
||||
#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 |
||||
#define DP_REMOTE_DPCD_READ 0x20 |
||||
#define DP_REMOTE_DPCD_WRITE 0x21 |
||||
#define DP_REMOTE_I2C_READ 0x22 |
||||
#define DP_REMOTE_I2C_WRITE 0x23 |
||||
#define DP_POWER_UP_PHY 0x24 |
||||
#define DP_POWER_DOWN_PHY 0x25 |
||||
#define DP_SINK_EVENT_NOTIFY 0x30 |
||||
#define DP_QUERY_STREAM_ENC_STATUS 0x38 |
||||
|
||||
/* DP 1.2 MST sideband nak reasons - table 2.84 */ |
||||
#define DP_NAK_WRITE_FAILURE 0x01 |
||||
#define DP_NAK_INVALID_READ 0x02 |
||||
#define DP_NAK_CRC_FAILURE 0x03 |
||||
#define DP_NAK_BAD_PARAM 0x04 |
||||
#define DP_NAK_DEFER 0x05 |
||||
#define DP_NAK_LINK_FAILURE 0x06 |
||||
#define DP_NAK_NO_RESOURCES 0x07 |
||||
#define DP_NAK_DPCD_FAIL 0x08 |
||||
#define DP_NAK_I2C_NAK 0x09 |
||||
#define DP_NAK_ALLOCATE_FAIL 0x0a |
||||
|
||||
#define MODE_I2C_START 1 |
||||
#define MODE_I2C_WRITE 2 |
||||
#define MODE_I2C_READ 4 |
||||
#define MODE_I2C_STOP 8 |
||||
|
||||
/* Rest of file omitted as it is not used in U-Boot */ |
||||
|
||||
#endif /* _DRM_DP_HELPER_H_ */ |
Loading…
Reference in new issue