Add support for Seagate BlackArmor NAS220 Signed-off-by: Evgeni Dobrev <evgeni@studio-punkt.com>master
Evgeni Dobrev
11 years ago
committed by
Tom Rini
parent
4cf84ccbaf
commit
9637c4b2dd
@ -0,0 +1,12 @@ |
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if TARGET_NAS220 |
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config SYS_BOARD |
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default "nas220" |
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config SYS_VENDOR |
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default "Seagate" |
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config SYS_CONFIG_NAME |
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default "nas220" |
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endif |
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@ -0,0 +1,6 @@ |
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NAS220 BOARD |
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M: Evgeni Dobrev <evgeni@studio-punkt.com> |
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S: Maintained |
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F: board/Seagate/nas220/ |
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F: include/configs/nas220.h |
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F: configs/nas220_defconfig |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := nas220.o
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@ -0,0 +1,151 @@ |
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# |
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# Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> |
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# |
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# Based on sheevaplug/kwbimage.cfg originally written by |
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# Prafulla Wadaskar <prafulla@marvell.com> |
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# (C) Copyright 2009 |
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# Marvell Semiconductor <www.marvell.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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# Refer doc/README.kwbimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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# Boot Media configurations |
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BOOT_FROM nand |
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NAND_ECC_MODE default |
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NAND_PAGE_SIZE 0x0200 |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1b1b1b9b |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000618 # DDR Configuration register |
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# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) |
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# bit23-14: zero |
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# bit24: 1= enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: zero |
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# bit31-30: 01 |
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DATA 0xFFD01404 0x35143000 # DDR Controller Control Low |
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# bit 4: 0=addr/cmd in smame cycle |
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# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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# bit14: 0=input buffer always powered up |
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# bit18: 1=cpu lock transaction enabled |
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0=no additional STARTBURST delay |
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DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1) |
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# bit7-4: TRCD |
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# bit11- 8: TRP |
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# bit15-12: TWR |
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# bit19-16: TWTR |
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# bit20: TRAS msb |
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# bit23-21: 0x0 |
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# bit27-24: TRRD |
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# bit31-28: TRTP |
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DATA 0xFFD0140C 0x00000819 # DDR Timing (High) |
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# bit6-0: TRFC |
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# bit8-7: TR2R |
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# bit10-9: TR2W |
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# bit12-11: TW2W |
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# bit31-13: zero required |
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DATA 0xFFD01410 0x0000000d # DDR Address Control |
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# bit1-0: 00, Cs0width=x8 |
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# bit3-2: 11, Cs0size=1Gb |
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# bit5-4: 00, Cs1width=nonexistent |
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# bit7-6: 00, Cs1size =nonexistent |
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# bit9-8: 00, Cs2width=nonexistent |
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# bit11-10: 00, Cs2size =nonexistent |
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# bit13-12: 00, Cs3width=nonexistent |
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# bit15-14: 00, Cs3size =nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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# bit0: 0, OpenPage enabled |
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# bit31-1: 0 required |
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DATA 0xFFD01418 0x00000000 # DDR Operation |
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# bit3-0: 0x0, DDR cmd |
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# bit31-4: 0 required |
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DATA 0xFFD0141C 0x00000632 # DDR Mode |
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# bit2-0: 2, BurstLen=2 required |
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# bit3: 0, BurstType=0 required |
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# bit6-4: 4, CL=5 |
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# bit7: 0, TestMode=0 normal |
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# bit8: 0, DLL reset=0 normal |
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# bit11-9: 6, auto-precharge write recovery ???????????? |
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# bit12: 0, PD must be zero |
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# bit31-13: 0 required |
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DATA 0xFFD01420 0x00000040 # DDR Extended Mode |
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# bit0: 0, DDR DLL enabled |
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# bit1: 0, DDR drive strenght normal |
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# bit2: 0, DDR ODT control lsd (disabled) |
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# bit5-3: 000, required |
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# bit6: 1, DDR ODT control msb, (disabled) |
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# bit9-7: 000, required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0, required |
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# bit12: 0, DDR output buffer enabled |
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# bit31-13: 0 required |
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DATA 0xFFD01424 0x0000F07F # DDR Controller Control High |
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# bit2-0: 111, required |
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# bit3 : 1 , MBUS Burst Chop disabled |
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# bit6-4: 111, required |
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# bit7 : 0 |
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# bit8 : 0 |
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# bit9 : 0 , no half clock cycle addition to dataout |
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 1111 required |
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# bit31-16: 0 required |
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DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 00, CS0 hit selected |
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# bit23-4: ones, required |
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# bit31-24: 0x07, Size (i.e. 128MB) |
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DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 |
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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# bit1-0: 00, ODT0 controlled by ODT Control (low) register above |
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# bit3-2: 01, ODT1 active NEVER! |
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# bit31-4: zero, required |
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DATA 0xFFD0149C 0x0000E803 # CPU ODT Control |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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#bit0=1, enable DDR init upon this register write |
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DATA 0xffd01620 0x00465000 |
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# End of Header extension |
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DATA 0x0 0x0 |
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@ -0,0 +1,118 @@ |
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/*
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* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> |
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* |
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* Based on sheevaplug.c originally written by |
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* Prafulla Wadaskar <prafulla@marvell.com> |
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <miiphy.h> |
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#include <asm/arch/soc.h> |
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#include <asm/arch/mpp.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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/*
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* default gpio configuration |
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*/ |
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mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH, |
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NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH); |
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/* Multi-Purpose Pins Functionality configuration */ |
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static const u32 kwmpp_config[] = { |
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MPP0_NF_IO2, |
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MPP1_NF_IO3, |
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MPP2_NF_IO4, |
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MPP3_NF_IO5, |
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MPP4_NF_IO6, |
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MPP5_NF_IO7, |
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MPP6_SYSRST_OUTn, |
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MPP7_SPI_SCn, |
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MPP8_TW_SDA, |
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MPP9_TW_SCK, |
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MPP10_UART0_TXD, |
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MPP11_UART0_RXD, |
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MPP12_GPO, |
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MPP13_GPIO, |
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MPP14_GPIO, |
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MPP15_SATA0_ACTn, |
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MPP16_SATA1_ACTn, |
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MPP17_SATA0_PRESENTn, |
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MPP18_NF_IO0, |
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MPP19_NF_IO1, |
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MPP20_GPIO, |
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MPP21_GPIO, |
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MPP22_GPIO, |
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MPP23_GPIO, |
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MPP24_GPIO, |
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MPP25_GPIO, |
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MPP26_GPIO, |
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MPP27_GPIO, |
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MPP28_GPIO, |
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MPP29_GPIO, |
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MPP30_GPIO, |
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MPP31_GPIO, |
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MPP32_GPIO, |
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MPP33_GPIO, |
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MPP34_GPIO, |
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MPP35_GPIO, |
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0 |
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}; |
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kirkwood_mpp_conf(kwmpp_config, NULL); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/*
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* arch number of board |
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*/ |
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gd->bd->bi_arch_number = MACH_TYPE_NAS220; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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return 0; |
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} |
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#ifdef CONFIG_RESET_PHY_R |
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/* Configure and enable MV88E1116 PHY */ |
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void reset_phy(void) |
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{ |
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u16 reg; |
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u16 devadr; |
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char *name = "egiga0"; |
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if (miiphy_set_current_dev(name)) |
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return; |
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/* command to read PHY dev address */ |
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { |
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printf("Err..%s could not read PHY dev address\n", __func__); |
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return; |
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} |
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/*
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* Enable RGMII delay on Tx and Rx for CPU port |
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* Ref: sec 4.7.2 of chip datasheet |
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*/ |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
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/* reset the phy */ |
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miiphy_reset(name, devadr); |
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printf("88E1116 Initialized on %s\n", name); |
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} |
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#endif /* CONFIG_RESET_PHY_R */ |
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@ -0,0 +1,3 @@ |
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CONFIG_ARM=y |
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CONFIG_KIRKWOOD=y |
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CONFIG_TARGET_NAS220=y |
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@ -0,0 +1,168 @@ |
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/*
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* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> |
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* |
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* based on work from: |
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CONFIG_NAS220_H |
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#define _CONFIG_NAS220_H |
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/*
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* Machine type definition and ID |
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*/ |
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#define MACH_TYPE_NAS220 MACH_TYPE_RD88F6192_NAS |
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#define CONFIG_MACH_TYPE MACH_TYPE_NAS220 |
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#define CONFIG_IDENT_STRING "\nNAS 220" |
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/*
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* High Level Configuration Options (easy to change) |
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*/ |
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#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ |
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#define CONFIG_KW88F6192 /* SOC Name */ |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
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/* power-on led, regulator, sata0, sata1 */ |
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#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) |
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#define NAS220_GE_OE_VAL_HIGH (0) |
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#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) |
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#define NAS220_GE_OE_HIGH (~(0)) |
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/* PHY related */ |
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#define MV88E1116_LED_FCTRL_REG 10 |
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#define MV88E1116_CPRSP_CR3_REG 21 |
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#define MV88E1116_MAC_CTRL_REG 21 |
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#define MV88E1116_PGADR_REG 22 |
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
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/*
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* Commands configuration |
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*/ |
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_NAND |
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#define CONFIG_CMD_SAVEENV |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_USB |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_IDE |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
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/*
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* mv-common.h should be defined after CMD configs since it used them |
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* to enable certain macros |
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*/ |
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#include "mv-common.h" |
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/* Remove or override few declarations from mv-common.h */ |
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#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */ |
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#define CONFIG_SYS_PROMPT "nas220> " |
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/*
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* Environment variables configurations |
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*/ |
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#ifdef CONFIG_CMD_NAND |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_SECT_SIZE 0x10000 |
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#else |
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#define CONFIG_ENV_IS_NOWHERE |
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#endif |
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#define CONFIG_ENV_SIZE 0x10000 |
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#define CONFIG_ENV_OFFSET 0xa0000 |
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/*
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* Default environment variables |
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*/ |
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#define CONFIG_BOOTCOMMAND "" |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"bootargs=console=ttyS0,115200\0" \
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"mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\
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"0x010000@0xa0000(env),"\
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"0x500000@0xc0000(uimage),"\
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"0x1a40000@0x5c0000(rootfs)\0" \
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"mtdids=nand0=orion_nand\0"\
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"bootdelay=-1\0"\
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"autostart=no\0"\
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"autoload=no\0" |
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/*
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* Ethernet Driver configuration |
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*/ |
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#ifdef CONFIG_CMD_NET |
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#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ |
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#define CONFIG_PHY_BASE_ADR 8 |
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#endif /* CONFIG_CMD_NET */ |
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/*
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* USB/EHCI |
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*/ |
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#ifdef CONFIG_CMD_USB |
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#define CONFIG_USB_EHCI /* Enable EHCI USB support */ |
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#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ |
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#define CONFIG_EHCI_IS_TDI |
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#define CONFIG_USB_STORAGE |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_SUPPORT_VFAT |
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#endif /* CONFIG_CMD_USB */ |
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/*
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* File system |
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*/ |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_JFFS2 |
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#define CONFIG_JFFS2_NAND |
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#define CONFIG_JFFS2_LZO |
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#define CONFIG_CMD_UBI |
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#define CONFIG_CMD_UBIFS |
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#define CONFIG_RBTREE |
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
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#define CONFIG_MTD_PARTITIONS |
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#define CONFIG_CMD_MTDPARTS |
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#define CONFIG_LZO |
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/*
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* SATA |
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*/ |
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#ifdef CONFIG_MVSATA_IDE |
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#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET |
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#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET |
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#endif |
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/*
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* Device Tree |
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*/ |
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#define CONFIG_OF_LIBFDT |
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/*
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* EFI partition |
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*/ |
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#define CONFIG_EFI_PARTITION |
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/*
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* Date Time |
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*/ |
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#ifdef CONFIG_CMD_DATE |
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#define CONFIG_RTC_MV |
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#endif /* CONFIG_CMD_DATE */ |
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#define CONFIG_KIRKWOOD_GPIO |
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#endif /* _CONFIG_NAS220_H */ |
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