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@ -14,7 +14,7 @@ |
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#include "mux_data.h" |
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#ifdef CONFIG_USB_EHCI |
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#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) |
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#include <usb.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/clock.h> |
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@ -72,6 +72,35 @@ int board_eth_init(bd_t *bis) |
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return 0; |
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} |
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#if defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_XHCI_OMAP) |
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static void enable_host_clocks(void) |
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{ |
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int auxclk; |
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int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | |
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OPTFCLKEN_HSIC480M_P3_CLK | |
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OPTFCLKEN_HSIC60M_P2_CLK | |
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OPTFCLKEN_HSIC480M_P2_CLK | |
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OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); |
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/* Enable port 2 and 3 clocks*/ |
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setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); |
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/* Enable port 2 and 3 usb host ports tll clocks*/ |
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setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, |
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(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); |
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#ifdef CONFIG_USB_XHCI_OMAP |
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/* Enable the USB OTG Super speed clocks */ |
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setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, |
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(OPTFCLKEN_REFCLK960M | OTG_SS_CLKCTRL_MODULEMODE_HW)); |
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#endif |
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auxclk = readl((*prcm)->scrm_auxclk1); |
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/* Request auxilary clock */ |
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auxclk |= AUXCLK_ENABLE_MASK; |
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writel(auxclk, (*prcm)->scrm_auxclk1); |
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} |
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#endif |
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/**
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* @brief misc_init_r - Configure EVM board specific configurations |
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* such as power configurations, ethernet initialization as phase2 of |
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@ -84,6 +113,7 @@ int misc_init_r(void) |
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#ifdef CONFIG_PALMAS_POWER |
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palmas_init_settings(); |
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#endif |
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return 0; |
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} |
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@ -129,26 +159,9 @@ static struct omap_usbhs_board_data usbhs_bdata = { |
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.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, |
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}; |
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static void enable_host_clocks(void) |
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{ |
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int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | |
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OPTFCLKEN_HSIC480M_P3_CLK | |
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OPTFCLKEN_HSIC60M_P2_CLK | |
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OPTFCLKEN_HSIC480M_P2_CLK | |
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OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); |
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/* Enable port 2 and 3 clocks*/ |
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setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); |
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/* Enable port 2 and 3 usb host ports tll clocks*/ |
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setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, |
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(OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); |
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} |
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
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{ |
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int ret; |
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int auxclk; |
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int reg; |
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uint8_t device_mac[6]; |
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@ -171,11 +184,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
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eth_setenv_enetaddr("usbethaddr", device_mac); |
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} |
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auxclk = readl((*prcm)->scrm_auxclk1); |
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/* Request auxilary clock */ |
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auxclk |= AUXCLK_ENABLE_MASK; |
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writel(auxclk, (*prcm)->scrm_auxclk1); |
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ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); |
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if (ret < 0) { |
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puts("Failed to initialize ehci\n"); |
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@ -203,3 +211,23 @@ void usb_hub_reset_devices(int port) |
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} |
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} |
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#endif |
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#ifdef CONFIG_USB_XHCI_OMAP |
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/**
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* @brief board_usb_init - Configure EVM board specific configurations |
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* for the LDO's and clocks for the USB blocks. |
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* |
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* @return 0 |
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*/ |
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int board_usb_init(void) |
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{ |
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int ret; |
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#ifdef CONFIG_PALMAS_USB_SS_PWR |
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ret = palmas_enable_ss_ldo(); |
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#endif |
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enable_host_clocks(); |
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return 0; |
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} |
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#endif |
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