Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMAC

All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
master
Ben Warren 16 years ago
parent 9eb79bd885
commit 96e21f86e8
  1. 9
      cpu/ppc4xx/4xx_enet.c
  2. 1
      cpu/ppc4xx/Makefile
  3. 1
      include/configs/AR405.h
  4. 1
      include/configs/ASH405.h
  5. 1
      include/configs/CMS700.h
  6. 1
      include/configs/CPCI405.h
  7. 1
      include/configs/CPCI4052.h
  8. 1
      include/configs/CPCI405AB.h
  9. 1
      include/configs/CPCI405DT.h
  10. 1
      include/configs/CPCIISER4.h
  11. 2
      include/configs/CRAYL1.h
  12. 1
      include/configs/DP405.h
  13. 1
      include/configs/DU405.h
  14. 1
      include/configs/DU440.h
  15. 1
      include/configs/ERIC.h
  16. 1
      include/configs/EXBITGEN.h
  17. 1
      include/configs/G2000.h
  18. 1
      include/configs/HH405.h
  19. 1
      include/configs/HUB405.h
  20. 1
      include/configs/JSE.h
  21. 1
      include/configs/KAREF.h
  22. 1
      include/configs/METROBOX.h
  23. 1
      include/configs/MIP405.h
  24. 1
      include/configs/OCRTC.h
  25. 1
      include/configs/ORSG.h
  26. 1
      include/configs/PCI405.h
  27. 1
      include/configs/PIP405.h
  28. 1
      include/configs/PLU405.h
  29. 1
      include/configs/PMC405.h
  30. 1
      include/configs/PMC440.h
  31. 1
      include/configs/PPChameleonEVB.h
  32. 1
      include/configs/VOH405.h
  33. 1
      include/configs/VOM405.h
  34. 1
      include/configs/W7OLMC.h
  35. 1
      include/configs/W7OLMG.h
  36. 1
      include/configs/WUH405.h
  37. 1
      include/configs/XPEDITE1K.h
  38. 1
      include/configs/alpr.h
  39. 1
      include/configs/amcc-common.h
  40. 1
      include/configs/csb272.h
  41. 1
      include/configs/csb472.h
  42. 1
      include/configs/korat.h
  43. 1
      include/configs/lwmon5.h
  44. 1
      include/configs/netstal-common.h
  45. 1
      include/configs/p3p440.h
  46. 1
      include/configs/pcs440ep.h
  47. 1
      include/configs/quad100hd.h
  48. 1
      include/configs/sbc405.h
  49. 2
      include/configs/sc3.h
  50. 1
      include/configs/zeus.h
  51. 5
      net/eth.c

@ -91,13 +91,6 @@
#include <miiphy.h>
#include <malloc.h>
/*
* Only compile for platform with AMCC EMAC ethernet controller and
* network support enabled.
* Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
*/
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
@ -2131,5 +2124,3 @@ int emac4xx_miiphy_initialize (bd_t * bis)
return 0;
}
#endif /* !defined(CONFIG_NET_MULTI) */
#endif

@ -38,6 +38,7 @@ COBJS += 44x_spd_ddr2.o
ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
COBJS += 4xx_ibm_ddr2_autocalib.o
endif
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS += 4xx_pci.o
COBJS += 4xx_pcie.o
COBJS += bedbug_405.o

@ -67,6 +67,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -56,6 +56,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -52,6 +52,7 @@
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1

@ -52,6 +52,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -54,6 +54,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -54,6 +54,7 @@
#undef CONFIG_LOADS_ECHO /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -53,6 +53,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -50,6 +50,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -39,6 +39,8 @@
#define CONFIG_SYS_CLK_FREQ 25000000
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */

@ -52,6 +52,7 @@
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */

@ -54,6 +54,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -253,6 +253,7 @@
int du440_phy_addr(int devnum);
#endif
#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */

@ -93,6 +93,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */

@ -88,6 +88,7 @@
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_PPC4xx_EMAC
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

@ -80,6 +80,7 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY1_ADDR 1 /* PHY address */

@ -64,6 +64,7 @@
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1

@ -54,6 +54,7 @@
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -132,6 +132,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */

@ -157,6 +157,7 @@
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */

@ -221,6 +221,7 @@
/*-----------------------------------------------------------------------
* Networking
*----------------------------------------------------------------------*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */

@ -336,6 +336,7 @@
/************************************************************
* Ethernet Stuff
***********************************************************/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */

@ -50,6 +50,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -50,6 +50,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -63,6 +63,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */

@ -278,6 +278,7 @@
/************************************************************
* Ethernet Stuff
***********************************************************/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
/************************************************************

@ -54,6 +54,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -56,6 +56,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -315,6 +315,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */

@ -104,6 +104,7 @@
#undef CONFIG_EXT_PHY
#define CONFIG_NET_MULTI 1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#ifndef CONFIG_EXT_PHY
#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */

@ -55,6 +55,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -53,6 +53,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -65,6 +65,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */

@ -65,6 +65,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */

@ -54,6 +54,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */

@ -167,6 +167,7 @@ extern void out32(unsigned int, unsigned long);
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */

@ -198,6 +198,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */

@ -45,6 +45,7 @@
/*
* Ethernet/EMAC/PHY
*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII /* MII PHY management */
#define CONFIG_NET_MULTI
#define CONFIG_NETCONSOLE /* include NetConsole support */

@ -180,6 +180,7 @@
* MII PHY configuration
*
*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */

@ -179,6 +179,7 @@
* MII PHY configuration
*
*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */

@ -215,6 +215,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */

@ -326,6 +326,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */

@ -58,6 +58,7 @@
/*
* Ethernet/EMAC/PHY
*/
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#if defined(CONFIG_440)

@ -158,6 +158,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x1c /* PHY address */
#define CONFIG_HAS_ETH1

@ -218,6 +218,7 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1 /* required for netconsole */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */

@ -45,6 +45,7 @@
#define CONFIG_ENV_IS_IN_EEPROM
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_PPC4xx_EMAC
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_MII 1 /* MII PHY management */

@ -58,6 +58,7 @@
#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */

@ -166,6 +166,8 @@
/* #define CONFIG_EEPRO100_SROM_WRITE */
/* #define CONFIG_SHOW_MAC */
#define CONFIG_EEPRO100
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* add 405GP MII PHY management */
#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */

@ -46,6 +46,7 @@
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0x01 /* PHY address */
#define CONFIG_HAS_ETH1 1

@ -153,7 +153,7 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_DB64460) || defined(CONFIG_P3Mx)
mv6446x_eth_initialize(bis);
#endif
#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000)
#if defined(CONFIG_PPC4xx_EMAC)
ppc_4xx_eth_initialize(bis);
#endif
if (!eth_devices) {
@ -485,8 +485,7 @@ int eth_initialize(bd_t *bis)
#if defined(CONFIG_AT91RM9200)
at91rm9200_miiphy_initialize(bis);
#endif
#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) \
&& !defined(CONFIG_AP1000) && !defined(CONFIG_405)
#if defined(CONFIG_PPC4xx_EMAC)
emac4xx_miiphy_initialize(bis);
#endif
#if defined(CONFIG_MCF52x2)

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