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@ -12,7 +12,7 @@ |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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@ -58,9 +58,9 @@ void cpu_init_f (void) |
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/* Enable UART pins */ |
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mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | |
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MCF_GPIO_PAR_UART_U0RXD | |
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MCF_GPIO_PAR_UART_U1RXD_UART1 | |
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MCF_GPIO_PAR_UART_U1TXD_UART1); |
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MCF_GPIO_PAR_UART_U0RXD | |
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MCF_GPIO_PAR_UART_U1RXD_UART1 | |
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MCF_GPIO_PAR_UART_U1TXD_UART1); |
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/* Enable Ethernet pins */ |
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mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); |
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@ -69,7 +69,7 @@ void cpu_init_f (void) |
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/*
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* initialize higher level parts of CPU like timers |
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*/ |
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int cpu_init_r (void) |
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int cpu_init_r (void) |
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{ |
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return (0); |
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} |
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@ -97,7 +97,7 @@ void cpu_init_f (void) |
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regp->sysctrl_reg.sc_scr = CFG_SCR; |
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regp->sysctrl_reg.sc_spr = CFG_SPR; |
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/* Setup Ports: */ |
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/* Setup Ports: */ |
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regp->gpio_reg.gpio_pacnt = CFG_PACNT; |
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regp->gpio_reg.gpio_paddr = CFG_PADDR; |
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regp->gpio_reg.gpio_padat = CFG_PADAT; |
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@ -147,15 +147,15 @@ void cpu_init_f (void) |
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ |
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/* enable instruction cache now */ |
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icache_enable(); |
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/* enable instruction cache now */ |
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icache_enable(); |
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} |
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/*
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* initialize higher level parts of CPU like timers |
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*/ |
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int cpu_init_r (void) |
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int cpu_init_r (void) |
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{ |
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return (0); |
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} |
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@ -178,7 +178,7 @@ void cpu_init_f (void) |
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/*
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* initialize higher level parts of CPU like timers |
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*/ |
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int cpu_init_r (void) |
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int cpu_init_r (void) |
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{ |
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return (0); |
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} |
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@ -202,23 +202,23 @@ void cpu_init_f (void) |
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volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); |
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unsigned long pllcr; |
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#ifdef CFG_FAST_CLK |
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ |
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pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ |
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#else |
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ |
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pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ |
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#endif |
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ |
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ |
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ |
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */ |
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ |
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udelay(0x20); /* Wait for a lock ... */ |
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cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ |
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mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ |
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ |
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pllcr ^= 0x00000001; /* Set pll bypass to 1 */ |
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mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ |
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udelay(0x20); /* Wait for a lock ... */ |
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#endif /* #ifndef CFG_PLL_BYPASS */ |
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/*
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* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins |
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* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins |
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* which is their primary function. |
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* ~Jeremy |
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* (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins |
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* which is their primary function. |
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* ~Jeremy |
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*/ |
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mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); |
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mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); |
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@ -233,7 +233,7 @@ void cpu_init_f (void) |
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* (Internal Register Display) command |
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* ~Jeremy |
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* |
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*/ |
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*/ |
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mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ |
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mbar_writeByte(MCFSIM_SYPCR, 0x00); |
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mbar_writeByte(MCFSIM_SWIVR, 0x0f); |
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@ -252,9 +252,9 @@ void cpu_init_f (void) |
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mbar_writeByte(MCFSIM_QSPIICR, 0x00); |
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mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); |
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ |
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mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ |
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mbar2_writeByte(MCFSIM_SPURVEC, 0x00); |
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mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ |
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mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ |
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/* Setup interrupt priorities for gpio7 */ |
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/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ |
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@ -282,7 +282,7 @@ void cpu_init_f (void) |
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/*
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* initialize higher level parts of CPU like timers |
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*/ |
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int cpu_init_r (void) |
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int cpu_init_r (void) |
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{ |
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return (0); |
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} |
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