* prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>master
parent
1b34f00c28
commit
98250e8e17
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#
|
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# (C) Copyright 2000-2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(SOC).a
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SOBJS += lowlevel_init.o
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COBJS += reset.o
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COBJS += timer.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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all: $(obj).depend $(LIB) |
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$(LIB): $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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|
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,164 @@ |
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/* |
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* |
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* Modified for the at91rm9200dk board by |
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* (C) Copyright 2004 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_mc.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_pio.h> |
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#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
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_MTEXT_BASE: |
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#undef START_FROM_MEM |
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#ifdef START_FROM_MEM |
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.word TEXT_BASE-PHYS_FLASH_1 |
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#else |
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.word TEXT_BASE
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#endif |
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.globl lowlevel_init
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lowlevel_init: |
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ldr r1, =AT91_ASM_PMC_MOR |
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/* Main oscillator Enable register */ |
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#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR |
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ldr r0, =0x0000FF01 /* Enable main oscillator */ |
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#else |
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ldr r0, =0x0000FF00 /* Disable main oscillator */ |
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#endif |
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str r0, [r1] /*AT91C_CKGR_MOR] */ |
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/* Add loop to compensate Main Oscillator startup time */ |
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ldr r0, =0x00000010 |
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LoopOsc: |
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subs r0, r0, #1 |
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bhi LoopOsc |
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/* memory control configuration */ |
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/* this isn't very elegant, but what the heck */ |
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ldr r0, =SMRDATA |
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ldr r1, _MTEXT_BASE |
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sub r0, r0, r1 |
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add r2, r0, #80 |
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pllloop: |
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/* the address */ |
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ldr r1, [r0], #4 |
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/* the value */ |
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ldr r3, [r0], #4 |
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str r3, [r1] |
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cmp r2, r0 |
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bne pllloop |
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/* delay - this is all done by guess */ |
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ldr r0, =0x00010000 |
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/* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ |
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lock: |
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subs r0, r0, #1 |
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bhi lock |
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ldr r0, =SMRDATA1 |
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ldr r1, _MTEXT_BASE |
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sub r0, r0, r1 |
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add r2, r0, #176 |
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sdinit: |
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/* the address */ |
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ldr r1, [r0], #4 |
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/* the value */ |
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ldr r3, [r0], #4 |
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str r3, [r1] |
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cmp r2, r0 |
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bne sdinit |
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/* switch from FastBus to Asynchronous clock mode */ |
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mrc p15, 0, r0, c1, c0, 0 |
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orr r0, r0, #ARM920T_CONTROL |
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mcr p15, 0, r0, c1, c0, 0 |
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/* everything is fine now */ |
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mov pc, lr |
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.ltorg |
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SMRDATA: |
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.word AT91_ASM_MC_EBI_CFG
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.word CONFIG_SYS_EBI_CFGR_VAL
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.word AT91_ASM_MC_SMC_CSR0
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.word CONFIG_SYS_SMC_CSR0_VAL
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.word AT91_ASM_PMC_PLLAR
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.word CONFIG_SYS_PLLAR_VAL
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.word AT91_ASM_PMC_PLLBR
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.word CONFIG_SYS_PLLBR_VAL
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.word AT91_ASM_PMC_MCKR
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.word CONFIG_SYS_MCKR_VAL
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/* here there's a delay */ |
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SMRDATA1: |
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.word AT91_ASM_PIOC_ASR
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.word CONFIG_SYS_PIOC_ASR_VAL
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.word AT91_ASM_PIOC_BSR
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.word CONFIG_SYS_PIOC_BSR_VAL
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.word AT91_ASM_PIOC_PDR
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.word CONFIG_SYS_PIOC_PDR_VAL
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.word AT91_ASM_MC_EBI_CSA
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.word CONFIG_SYS_EBI_CSA_VAL
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.word AT91_ASM_MC_SDRAMC_CR
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.word CONFIG_SYS_SDRC_CR_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL1
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL2
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.word CONFIG_SYS_SDRAM1
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_TR
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.word CONFIG_SYS_SDRC_TR_VAL
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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.word AT91_ASM_MC_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL3
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.word CONFIG_SYS_SDRAM
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.word CONFIG_SYS_SDRAM_VAL
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/* SMRDATA1 is 176 bytes long */ |
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
@ -0,0 +1,59 @@ |
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/*
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* (C) Copyright 2002 |
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* Lineo, Inc. <www.lineo.com> |
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* Bernhard Kuhn <bkuhn@lineo.com> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_st.h> |
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void board_reset(void) __attribute__((__weak__)); |
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void reset_cpu(ulong ignored) |
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{ |
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at91_st_t *st = (at91_st_t *) AT91_ST_BASE; |
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#if defined(CONFIG_AT91RM9200_USART) |
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/*shutdown the console to avoid strange chars during reset */ |
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serial_exit(); |
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#endif |
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if (board_reset) |
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board_reset(); |
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/* Reset the cpu by setting up the watchdog timer */ |
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writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2), |
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&st->wdmr); |
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writel(AT91_ST_CR_WDRST, &st->cr); |
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/* and let it timeout */ |
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while (1) |
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; |
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/* Never reached */ |
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} |
@ -0,0 +1,163 @@ |
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/*
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* (C) Copyright 2002 |
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* Lineo, Inc. <www.lineo.com> |
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* Bernhard Kuhn <bkuhn@lineo.com> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/hardware.h> |
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#include <asm/arch/at91_tc.h> |
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#include <asm/arch/at91_pmc.h> |
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/* the number of clocks per CONFIG_SYS_HZ */ |
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#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) |
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static u32 timestamp; |
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static u32 lastinc; |
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int timer_init(void) |
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{ |
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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|
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/* enables TC1.0 clock */ |
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writel(1 << AT91_ID_TC0, &pmc->pcer); /* enable clock */ |
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writel(0, &tc->bcr); |
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writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | |
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AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr); |
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writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); |
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/* set to MCLK/2 and restart the timer
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when the value in TC_RC is reached */ |
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writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); |
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writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */ |
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writel(TIMER_LOAD_VAL, &tc->tc[0].rc); |
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writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); |
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lastinc = 0; |
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timestamp = 0; |
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return 0; |
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} |
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|
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/*
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* timer without interrupts |
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*/ |
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|
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void reset_timer(void) |
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{ |
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reset_timer_masked(); |
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} |
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|
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ulong get_timer(ulong base) |
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{ |
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return get_timer_masked() - base; |
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} |
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|
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void set_timer(ulong t) |
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{ |
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timestamp = t; |
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} |
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|
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void __udelay(unsigned long usec) |
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{ |
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udelay_masked(usec); |
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} |
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|
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void reset_timer_masked(void) |
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{ |
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/* reset time */ |
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; |
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lastinc = readl(&tc->tc[0].cv) & 0x0000ffff; |
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timestamp = 0; |
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} |
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|
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ulong get_timer_raw(void) |
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{ |
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at91_tc_t *tc = (at91_tc_t *) AT91_TC_BASE; |
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u32 now; |
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|
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now = readl(&tc->tc[0].cv) & 0x0000ffff; |
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|
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if (now >= lastinc) { |
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/* normal mode */ |
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timestamp += now - lastinc; |
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} else { |
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/* we have an overflow ... */ |
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timestamp += now + TIMER_LOAD_VAL - lastinc; |
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} |
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lastinc = now; |
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|
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return timestamp; |
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} |
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|
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ulong get_timer_masked(void) |
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{ |
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return get_timer_raw()/TIMER_LOAD_VAL; |
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} |
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|
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void udelay_masked(unsigned long usec) |
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{ |
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u32 tmo; |
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u32 endtime; |
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signed long diff; |
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|
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tmo = CONFIG_SYS_HZ_CLOCK / 1000; |
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tmo *= usec; |
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tmo /= 1000; |
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|
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endtime = get_timer_raw() + tmo; |
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|
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do { |
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u32 now = get_timer_raw(); |
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diff = endtime - now; |
||||
} while (diff >= 0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
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* On ARM it just returns the timer value. |
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*/ |
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unsigned long long get_ticks(void) |
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{ |
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return get_timer(0); |
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} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
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ulong get_tbclk(void) |
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{ |
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return CONFIG_SYS_HZ; |
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} |
@ -0,0 +1,97 @@ |
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/*
|
||||
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91_MC_H |
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#define AT91_MC_H |
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|
||||
#define AT91_ASM_MC_EBI_CSA (AT91_MC_BASE + 0x60) |
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#define AT91_ASM_MC_EBI_CFG (AT91_MC_BASE + 0x64) |
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#define AT91_ASM_MC_SMC_CSR0 (AT91_MC_BASE + 0x70) |
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#define AT91_ASM_MC_SDRAMC_MR (AT91_MC_BASE + 0x90) |
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#define AT91_ASM_MC_SDRAMC_TR (AT91_MC_BASE + 0x94) |
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#define AT91_ASM_MC_SDRAMC_CR (AT91_MC_BASE + 0x98) |
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|
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#ifndef __ASSEMBLY__ |
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|
||||
typedef struct at91_ebi { |
||||
u32 csa; /* 0x00 Chip Select Assignment Register */ |
||||
u32 cfgr; /* 0x04 Configuration Register */ |
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u32 reserved[2]; |
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} __attribute__ ((packed)) at91_ebi_t; |
||||
|
||||
#define AT91_EBI_CSA_CS0A 0x0001 |
||||
#define AT91_EBI_CSA_CS1A 0x0002 |
||||
|
||||
#define AT91_EBI_CSA_CS3A 0x0008 |
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#define AT91_EBI_CSA_CS4A 0x0010 |
||||
|
||||
typedef struct at91_sdramc { |
||||
u32 mr; /* 0x00 SDRAMC Mode Register */ |
||||
u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ |
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u32 cr; /* 0x08 SDRAMC Configuration Register */ |
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u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ |
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u32 lpr; /* 0x10 SDRAMC Low Power Register */ |
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u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ |
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u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ |
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u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ |
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u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ |
||||
u32 reserved[3]; |
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} __attribute__ ((packed)) at91_sdramc_t; |
||||
|
||||
typedef struct at91_smc { |
||||
u32 csr[8]; /* 0x00 SDRAMC Mode Register */ |
||||
} __attribute__ ((packed)) at91_smc_t; |
||||
|
||||
#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) |
||||
#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) |
||||
#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 |
||||
#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 |
||||
#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 |
||||
#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 |
||||
#define AT91_SMC_CSR_DRP 0x00008000 |
||||
#define AT91_SMC_CSR_DBW_8 0x00004000 |
||||
#define AT91_SMC_CSR_DBW_16 0x00002000 |
||||
#define AT91_SMC_CSR_BAT_8 0x00000000 |
||||
#define AT91_SMC_CSR_BAT_16 0x00001000 |
||||
#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) |
||||
#define AT91_SMC_CSR_WSEN 0x00000080 |
||||
#define AT91_SMC_CSR_NWS(x) (x & 0x7F) |
||||
|
||||
typedef struct at91_bfc { |
||||
u32 mr; /* 0x00 SDRAMC Mode Register */ |
||||
} __attribute__ ((packed)) at91_bfc_t; |
||||
|
||||
typedef struct at91_mc { |
||||
u32 rcr; /* 0x00 MC Remap Control Register */ |
||||
u32 asr; /* 0x04 MC Abort Status Register */ |
||||
u32 aasr; /* 0x08 MC Abort Address Status Reg */ |
||||
u32 mpr; /* 0x0C MC Master Priority Register */ |
||||
u32 reserved1[20]; /* 0x10-0x5C */ |
||||
at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ |
||||
at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ |
||||
at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ |
||||
at91_bfc_t bfc; /* 0xC0 BFC User Interface */ |
||||
u32 reserved2[15]; |
||||
} __attribute__ ((packed)) at91_mc_t; |
||||
|
||||
#endif |
||||
#endif |
@ -0,0 +1,46 @@ |
||||
/*
|
||||
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91_ST_H |
||||
#define AT91_ST_H |
||||
|
||||
typedef struct at91_st { |
||||
|
||||
u32 cr; |
||||
u32 pimr; |
||||
u32 wdmr; |
||||
u32 rtmr; |
||||
u32 sr; |
||||
u32 ier; |
||||
u32 idr; |
||||
u32 imr; |
||||
u32 rtar; |
||||
u32 crtr; |
||||
} __attribute__ ((packed)) at91_st_t ; |
||||
|
||||
#define AT91_ST_CR_WDRST 1 |
||||
|
||||
#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF) |
||||
#define AT91_ST_WDMR_RSTEN 0x00010000 |
||||
#define AT91_ST_WDMR_EXTEN 0x00020000 |
||||
|
||||
#endif |
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91_TC_H |
||||
#define AT91_TC_H |
||||
|
||||
typedef struct at91_tcc { |
||||
u32 ccr; /* 0x00 Channel Control Register */ |
||||
u32 cmr; /* 0x04 Channel Mode Register */ |
||||
u32 reserved1[2]; |
||||
u32 cv; /* 0x10 Counter Value */ |
||||
u32 ra; /* 0x14 Register A */ |
||||
u32 rb; /* 0x18 Register B */ |
||||
u32 rc; /* 0x1C Register C */ |
||||
u32 sr; /* 0x20 Status Register */ |
||||
u32 ier; /* 0x24 Interrupt Enable Register */ |
||||
u32 idr; /* 0x28 Interrupt Disable Register */ |
||||
u32 imr; /* 0x2C Interrupt Mask Register */ |
||||
u32 reserved3[4]; |
||||
} __attribute__ ((packed)) at91_tcc_t; |
||||
|
||||
#define AT91_TC_CCR_CLKEN 0x00000001 |
||||
#define AT91_TC_CCR_CLKDIS 0x00000002 |
||||
#define AT91_TC_CCR_SWTRG 0x00000004 |
||||
|
||||
#define AT91_TC_CMR_CPCTRG 0x00004000 |
||||
|
||||
#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 |
||||
#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 |
||||
#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 |
||||
#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 |
||||
#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 |
||||
#define AT91_TC_CMR_TCCLKS_XC0 0x00000005 |
||||
#define AT91_TC_CMR_TCCLKS_XC1 0x00000006 |
||||
#define AT91_TC_CMR_TCCLKS_XC2 0x00000007 |
||||
|
||||
typedef struct at91_tc { |
||||
at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ |
||||
u32 bcr; /* 0xC0 TC Block Control Register */ |
||||
u32 bmr; /* 0xC4 TC Block Mode Register */ |
||||
} __attribute__ ((packed)) at91_tc_t; |
||||
|
||||
#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 |
||||
#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 |
||||
#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 |
||||
#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 |
||||
|
||||
#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 |
||||
#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 |
||||
#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 |
||||
#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C |
||||
|
||||
#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 |
||||
#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 |
||||
#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 |
||||
#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 |
||||
|
||||
#endif |
@ -0,0 +1,135 @@ |
||||
/*
|
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __AT91RM9200_H__ |
||||
#define __AT91RM9200_H__ |
||||
|
||||
/* Periperial Identifiers */ |
||||
|
||||
#define AT91_ID_SYS 1 /* System Peripheral */ |
||||
#define AT91_ID_PIOA 2 /* PIO port A */ |
||||
#define AT91_ID_PIOB 3 /* PIO port B */ |
||||
#define AT91_ID_PIOC 4 /* PIO port C */ |
||||
#define AT91_ID_PIOD 5 /* PIO port D BGA only */ |
||||
#define AT91_ID_USART0 6 /* USART 0 */ |
||||
#define AT91_ID_USART1 7 /* USART 1 */ |
||||
#define AT91_ID_USART2 8 /* USART 2 */ |
||||
#define AT91_ID_USART3 9 /* USART 3 */ |
||||
#define AT91_ID_MCI 10 /* Multimedia Card Interface */ |
||||
#define AT91_ID_UDP 11 /* USB Device Port */ |
||||
#define AT91_ID_TWI 12 /* Two Wire Interface */ |
||||
#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ |
||||
#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */ |
||||
#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */ |
||||
#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */ |
||||
#define AT91_ID_TC0 17 /* Timer Counter 0 */ |
||||
#define AT91_ID_TC1 18 /* Timer Counter 1 */ |
||||
#define AT91_ID_TC2 19 /* Timer Counter 2 */ |
||||
#define AT91_ID_TC3 20 /* Timer Counter 3 */ |
||||
#define AT91_ID_TC4 21 /* Timer Counter 4 */ |
||||
#define AT91_ID_TC5 22 /* Timer Counter 5 */ |
||||
#define AT91_ID_UHP 23 /* OHCI USB Host Port */ |
||||
#define AT91_ID_EMAC 24 /* Ethernet MAC */ |
||||
#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */ |
||||
#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */ |
||||
|
||||
#define AT91_USB_HOST_BASE 0x00300000 |
||||
|
||||
#define AT91_TC_BASE 0xFFFA0000 |
||||
#define AT91_UDP_BASE 0xFFFB0000 |
||||
#define AT91_MCI_BASE 0xFFFB4000 |
||||
#define AT91_TWI_BASE 0xFFFB8000 |
||||
#define AT91_EMAC_BASE 0xFFFBC000 |
||||
#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */ |
||||
#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */ |
||||
#define AT91_SPI_BASE 0xFFFE0000 |
||||
|
||||
#define AT91_AIC_BASE 0xFFFFF000 |
||||
#define AT91_DBGU_BASE 0xFFFFF200 |
||||
#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */ |
||||
#define AT91_PMC_BASE 0xFFFFFC00 |
||||
#define AT91_ST_BASE 0xFFFFFD00 |
||||
#define AT91_ST_BASE 0xFFFFFD00 |
||||
#define AT91_RTC_BASE 0xFFFFFE00 |
||||
#define AT91_MC_BASE 0xFFFFFF00 |
||||
|
||||
|
||||
/* AT91RM9200 Periperial Multiplexing A */ |
||||
/* Port A */ |
||||
#define AT91_PMX_AA_EREFCK 0x00000080 |
||||
#define AT91_PMX_AA_ETXCK 0x00000080 |
||||
#define AT91_PMX_AA_ETXEN 0x00000100 |
||||
#define AT91_PMX_AA_ETX0 0x00000200 |
||||
#define AT91_PMX_AA_ETX1 0x00000400 |
||||
#define AT91_PMX_AA_ECRS 0x00000800 |
||||
#define AT91_PMX_AA_ECRSDV 0x00000800 |
||||
#define AT91_PMX_AA_ERX0 0x00001000 |
||||
#define AT91_PMX_AA_ERX1 0x00002000 |
||||
#define AT91_PMX_AA_ERXER 0x00004000 |
||||
#define AT91_PMX_AA_EMDC 0x00008000 |
||||
#define AT91_PMX_AA_EMDIO 0x00010000 |
||||
|
||||
#define AT91_PMX_AA_TXD2 0x00810000 |
||||
|
||||
#define AT91_PMX_AA_TWD 0x02000000 |
||||
#define AT91_PMX_AA_TWCK 0x04000000 |
||||
|
||||
/* Port B */ |
||||
#define AT91_PMX_BA_ERXCK 0x00080000 |
||||
#define AT91_PMX_BA_ECOL 0x00040000 |
||||
#define AT91_PMX_BA_ERXDV 0x00020000 |
||||
#define AT91_PMX_BA_ERX3 0x00010000 |
||||
#define AT91_PMX_BA_ERX2 0x00008000 |
||||
#define AT91_PMX_BA_ETXER 0x00004000 |
||||
#define AT91_PMX_BA_ETX3 0x00002000 |
||||
#define AT91_PMX_BA_ETX2 0x00001000 |
||||
|
||||
/* Port B */ |
||||
|
||||
#define AT91_PMX_CA_BFCK 0x00000001 |
||||
#define AT91_PMX_CA_BFRDY 0x00000002 |
||||
#define AT91_PMX_CA_SMOE 0x00000002 |
||||
#define AT91_PMX_CA_BFAVD 0x00000004 |
||||
#define AT91_PMX_CA_BFBAA 0x00000008 |
||||
#define AT91_PMX_CA_SMWE 0x00000008 |
||||
#define AT91_PMX_CA_BFOE 0x00000010 |
||||
#define AT91_PMX_CA_BFWE 0x00000020 |
||||
#define AT91_PMX_CA_NWAIT 0x00000040 |
||||
#define AT91_PMX_CA_A23 0x00000080 |
||||
#define AT91_PMX_CA_A24 0x00000100 |
||||
#define AT91_PMX_CA_A25 0x00000200 |
||||
#define AT91_PMX_CA_CFRNW 0x00000200 |
||||
#define AT91_PMX_CA_NCS4 0x00000400 |
||||
#define AT91_PMX_CA_CFCS 0x00000400 |
||||
#define AT91_PMX_CA_NCS5 0x00000800 |
||||
#define AT91_PMX_CA_CFCE1 0x00001000 |
||||
#define AT91_PMX_CA_NCS6 0x00001000 |
||||
#define AT91_PMX_CA_CFCE2 0x00002000 |
||||
#define AT91_PMX_CA_NCS7 0x00002000 |
||||
#define AT91_PMX_CA_D16_31 0xFFFF0000 |
||||
|
||||
#define AT91_CPU_NAME "AT91RM9200" |
||||
|
||||
#endif |
Loading…
Reference in new issue