Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>master
parent
1386233da3
commit
9879842c6f
@ -1,49 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
#include <mach/sbc-regs.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sbc_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* system bus output enable */ |
||||
tmp = readl(PC0CTRL); |
||||
tmp &= 0xfffffcff; |
||||
writel(tmp, PC0CTRL); |
||||
|
||||
/* XECS1: sub/boot memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
||||
|
||||
/* XECS0: boot/sub memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); |
||||
|
||||
/* XECS3: peripherals */ |
||||
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); |
||||
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); |
||||
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); |
||||
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); |
||||
|
||||
/* base address regsiters */ |
||||
writel(0x0000bc01, SBBASE0); |
||||
writel(0x0400bc01, SBBASE1); |
||||
writel(0x0800bf01, SBBASE3); |
||||
|
||||
/* enable access to sub memory when boot swap is on */ |
||||
if (boot_is_swapped()) |
||||
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */ |
||||
|
||||
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */ |
||||
} |
@ -1,42 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
#include <mach/sbc-regs.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sbc_init(void) |
||||
{ |
||||
/* XECS0: boot/sub memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04); |
||||
|
||||
/* XECS1: sub/boot memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
||||
|
||||
/* XECS3: peripherals */ |
||||
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30); |
||||
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31); |
||||
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32); |
||||
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34); |
||||
|
||||
writel(0x0000bc01, SBBASE0); /* boot memory */ |
||||
writel(0x0400bc01, SBBASE1); /* sub memory */ |
||||
writel(0x0800bf01, SBBASE3); /* peripherals */ |
||||
|
||||
/* enable access to sub memory when boot swap is on */ |
||||
if (boot_is_swapped()) |
||||
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */ |
||||
|
||||
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */ |
||||
writel(0x00000001, SG_LOADPINCTRL); |
||||
} |
@ -1,37 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
#include <mach/sbc-regs.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sbc_init(void) |
||||
{ |
||||
/* only address/data multiplex mode is supported */ |
||||
|
||||
/* XECS0 : boot/sub memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00); |
||||
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01); |
||||
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02); |
||||
|
||||
/* XECS1 : sub/boot memory (boot swap = off/on) */ |
||||
writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); |
||||
writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); |
||||
writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); |
||||
|
||||
/* XECS2 : peripherals */ |
||||
writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20); |
||||
writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21); |
||||
writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22); |
||||
|
||||
/* base address regsiters */ |
||||
writel(0x0000bc01, SBBASE0); |
||||
writel(0x0400bc01, SBBASE1); |
||||
writel(0x0800bf01, SBBASE2); |
||||
|
||||
sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ |
||||
} |
@ -1,57 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <linux/io.h> |
||||
#include <mach/sbc-regs.h> |
||||
#include <mach/sg-regs.h> |
||||
|
||||
void sbc_init(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/* system bus output enable */ |
||||
tmp = readl(PC0CTRL); |
||||
tmp &= 0xfffffcff; |
||||
writel(tmp, PC0CTRL); |
||||
|
||||
/*
|
||||
* SBCTRL0* does not need settings because PH1-sLD8 has no support for |
||||
* XECS0. The boot swap must be enabled to boot from the support card. |
||||
*/ |
||||
|
||||
if (boot_is_swapped()) { |
||||
/* XECS1 : boot memory if boot swap is on */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14); |
||||
} |
||||
|
||||
/* XECS4 : sub memory */ |
||||
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40); |
||||
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41); |
||||
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42); |
||||
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44); |
||||
|
||||
/* XECS5 : peripherals */ |
||||
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50); |
||||
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51); |
||||
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52); |
||||
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54); |
||||
|
||||
/* base address regsiters */ |
||||
writel(0x0000bc01, SBBASE0); /* boot memory */ |
||||
writel(0x0900bfff, SBBASE1); /* dummy */ |
||||
writel(0x0400bc01, SBBASE4); /* sub memory */ |
||||
writel(0x0800bf01, SBBASE5); /* peripherals */ |
||||
|
||||
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */ |
||||
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */ |
||||
|
||||
/* dummy read to assure write process */ |
||||
readl(SG_PINCTRL(0)); |
||||
} |
Loading…
Reference in new issue