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@ -162,12 +162,12 @@ static int lq035q1_control(unsigned char reg, unsigned short value) |
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/* enable and disable PPI functions */ |
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void EnablePPI(void) |
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{ |
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*pPPI_CONTROL |= PORT_EN; |
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bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); |
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} |
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void DisablePPI(void) |
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{ |
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*pPPI_CONTROL &= ~PORT_EN; |
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bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); |
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} |
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void Init_Ports(void) |
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@ -182,119 +182,123 @@ void Init_Ports(void) |
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void Init_PPI(void) |
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{ |
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*pPPI_DELAY = H_START; |
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*pPPI_COUNT = (H_ACTPIX-1); |
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*pPPI_FRAME = V_LINES; |
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bfin_write_PPI_DELAY(H_START); |
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bfin_write_PPI_COUNT(H_ACTPIX - 1); |
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bfin_write_PPI_FRAME(V_LINES); |
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/* PPI control, to be replaced with definitions */ |
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*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ |
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bfin_write_PPI_CONTROL( |
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PPI_TX_MODE | /* output mode , PORT_DIR */ |
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PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ |
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PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ |
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PPI_PACK_EN | /* packing enabled PACK_EN */ |
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PPI_POLS_1; /* faling edge syncs POLS */ |
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PPI_POLS_1 /* faling edge syncs POLS */ |
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); |
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} |
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void Init_DMA(void *dst) |
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{ |
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*pDMA0_START_ADDR = dst; |
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bfin_write_DMA0_START_ADDR(dst); |
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/* X count */ |
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*pDMA0_X_COUNT = H_ACTPIX / 2; |
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*pDMA0_X_MODIFY = DMA_BUS_SIZE / 8; |
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bfin_write_DMA0_X_COUNT(H_ACTPIX / 2); |
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bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8); |
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/* Y count */ |
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*pDMA0_Y_COUNT = V_LINES; |
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*pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8; |
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bfin_write_DMA0_Y_COUNT(V_LINES); |
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bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8); |
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/* DMA Config */ |
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*pDMA0_CONFIG = |
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bfin_write_DMA0_CONFIG( |
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WDSIZE_16 | /* 16 bit DMA */ |
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DMA2D | /* 2D DMA */ |
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FLOW_AUTO; /* autobuffer mode */ |
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FLOW_AUTO /* autobuffer mode */ |
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); |
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} |
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void EnableDMA(void) |
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{ |
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*pDMA0_CONFIG |= DMAEN; |
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bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN); |
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} |
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void DisableDMA(void) |
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{ |
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*pDMA0_CONFIG &= ~DMAEN; |
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bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN); |
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} |
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/* Init TIMER0 as Frame Sync 1 generator */ |
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void InitTIMER0(void) |
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{ |
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*pTIMER_DISABLE |= TIMDIS0; /* disable Timer */ |
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bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */ |
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SSYNC(); |
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*pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */ |
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bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */ |
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SSYNC(); |
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*pTIMER0_PERIOD = H_PERIOD; |
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bfin_write_TIMER0_PERIOD(H_PERIOD); |
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SSYNC(); |
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*pTIMER0_WIDTH = H_PULSE; |
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bfin_write_TIMER0_WIDTH(H_PULSE); |
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SSYNC(); |
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*pTIMER0_CONFIG = PWM_OUT | |
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bfin_write_TIMER0_CONFIG( |
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PWM_OUT | |
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PERIOD_CNT | |
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TIN_SEL | |
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CLK_SEL | |
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EMU_RUN; |
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EMU_RUN |
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); |
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SSYNC(); |
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} |
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void EnableTIMER0(void) |
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{ |
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*pTIMER_ENABLE |= TIMEN0; |
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bfin_write_TIMER_ENABLE(TIMEN0); |
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SSYNC(); |
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} |
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void DisableTIMER0(void) |
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{ |
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*pTIMER_DISABLE |= TIMDIS0; |
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bfin_write_TIMER_DISABLE(TIMDIS0); |
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SSYNC(); |
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} |
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void InitTIMER1(void) |
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{ |
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*pTIMER_DISABLE |= TIMDIS1; /* disable Timer */ |
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bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */ |
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SSYNC(); |
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*pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */ |
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bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */ |
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SSYNC(); |
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*pTIMER1_PERIOD = V_PERIOD; |
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bfin_write_TIMER1_PERIOD(V_PERIOD); |
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SSYNC(); |
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*pTIMER1_WIDTH = V_PULSE; |
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bfin_write_TIMER1_WIDTH(V_PULSE); |
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SSYNC(); |
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*pTIMER1_CONFIG = PWM_OUT | |
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bfin_write_TIMER1_CONFIG( |
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PWM_OUT | |
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PERIOD_CNT | |
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TIN_SEL | |
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CLK_SEL | |
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EMU_RUN; |
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EMU_RUN |
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); |
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SSYNC(); |
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} |
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void EnableTIMER1(void) |
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{ |
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*pTIMER_ENABLE |= TIMEN1; |
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bfin_write_TIMER_ENABLE(TIMEN1); |
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SSYNC(); |
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} |
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void DisableTIMER1(void) |
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{ |
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*pTIMER_DISABLE |= TIMDIS1; |
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bfin_write_TIMER_DISABLE(TIMDIS1); |
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SSYNC(); |
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} |
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void EnableTIMER12(void) |
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{ |
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*pTIMER_ENABLE |= TIMEN1 | TIMEN0; |
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bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0); |
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SSYNC(); |
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} |
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