This is not used in U-Boot anymore. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>master
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/*
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* (C) Copyright 1997-2002 ELTEC Elektronik AG |
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* Frank Gottschling <fgottschling@eltec.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* smiLynxEM.c |
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* |
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* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator |
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* |
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* modification history |
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* -------------------- |
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* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>. |
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* |
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* 18-03-2004 - Unify videomodes handling with the ct69000 |
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* - The video output can be set via the variable "videoout" |
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* in the environment. |
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* videoout=1 output on LCD |
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* videoout=2 output on CRT (default value) |
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* <p.aubert@staubli.com> |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <video_fb.h> |
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#include "videomodes.h" |
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/*
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* Export Graphic Device |
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*/ |
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GraphicDevice smi; |
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/*
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* SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external |
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*/ |
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#define VIDEO_MEM_SIZE 0x400000 |
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/*
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* ISA mapped regs |
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*/ |
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#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ |
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#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ |
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#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ |
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#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ |
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#define SMI_ISR1 (pGD->isaBase + 0x03ca) |
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#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ |
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#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ |
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#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ |
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#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ |
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#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ |
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#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ |
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#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ |
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#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */ |
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/*
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* Video processor control |
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*/ |
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typedef struct { |
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unsigned int control; |
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unsigned int colorKey; |
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unsigned int colorKeyMask; |
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unsigned int start; |
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unsigned short offset; |
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unsigned short width; |
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unsigned int fifoPrio; |
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unsigned int fifoERL; |
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unsigned int YUVtoRGB; |
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} SmiVideoProc; |
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/*
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* Video window control |
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*/ |
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typedef struct { |
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unsigned short top; |
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unsigned short left; |
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unsigned short bottom; |
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unsigned short right; |
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unsigned int srcStart; |
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unsigned short width; |
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unsigned short offset; |
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unsigned char hStretch; |
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unsigned char vStretch; |
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} SmiVideoWin; |
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/*
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* Capture port control |
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*/ |
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typedef struct { |
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unsigned int control; |
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unsigned short topClip; |
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unsigned short leftClip; |
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unsigned short srcHeight; |
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unsigned short srcWidth; |
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unsigned int srcBufStart1; |
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unsigned int srcBufStart2; |
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unsigned short srcOffset; |
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unsigned short fifoControl; |
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} SmiCapturePort; |
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/*
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* Register values for common video modes |
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*/ |
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static char SMI_SCR[] = { |
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/* all modes */ |
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0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90, |
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0x17, 0x20, 0x18, 0xb1, 0x19, 0x00, |
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}; |
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static char SMI_EXT_CRT[] = { |
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0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, |
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0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, |
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}; |
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static char SMI_ATTR [] = { |
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0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, |
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0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b, |
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0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00, |
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0x12, 0x0f, 0x13, 0x00, 0x14, 0x00, |
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}; |
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static char SMI_GCR[18] = { |
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0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40, |
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0x06, 0x05, 0x07, 0x0f, 0x08, 0xff, |
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}; |
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static char SMI_SEQR[] = { |
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0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03, |
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}; |
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static char SMI_PCR [] = { |
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0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, |
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}; |
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static char SMI_MCR[] = { |
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0x60, 0x01, 0x61, 0x00, |
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}; |
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static char SMI_HCR[] = { |
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0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00, |
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0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00, |
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}; |
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/*******************************************************************************
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* |
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* Write SMI ISA register |
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*/ |
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static void smiWrite (unsigned short index, char reg, char val) |
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{ |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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out8 ((pGD->isaBase + index), reg); |
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out8 ((pGD->isaBase + index + 1), val); |
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} |
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/*******************************************************************************
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* |
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* Write a table of SMI ISA register |
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*/ |
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static void smiLoadRegs ( |
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unsigned int iReg, |
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unsigned int dReg, |
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char *regTab, |
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unsigned int tabSize |
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) |
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{ |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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register int i; |
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for (i=0; i<tabSize; i+=2) { |
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if (iReg == SMI_INDX_ATTR) { |
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/* Reset the Flip Flop */ |
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in8 (SMI_ISR1); |
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out8 (iReg, regTab[i]); |
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out8 (iReg, regTab[i+1]); |
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} else { |
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out8 (iReg, regTab[i]); |
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out8 (dReg, regTab[i+1]); |
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} |
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} |
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} |
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/*******************************************************************************
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* |
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* Init capture port registers |
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*/ |
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static void smiInitCapturePort (void) |
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{ |
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SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 }; |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP; |
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out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip)); |
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out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth)); |
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out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8); |
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out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8); |
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out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8); |
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out32r ((pGD->cprBase + 0x0018), pCP->fifoControl); |
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out32r ((pGD->cprBase + 0x0000), pCP->control); |
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} |
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/*******************************************************************************
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* |
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* Init video processor registers |
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*/ |
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static void smiInitVideoProcessor (void) |
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{ |
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SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed }; |
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SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 }; |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP; |
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register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW; |
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pVP->width = pGD->plnSizeX * pGD->gdfBytesPP; |
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pVP->control |= pGD->gdfIndex << 16; |
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pVWin->bottom = pGD->winSizeY - 1; |
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pVWin->right = pGD->winSizeX - 1; |
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pVWin->width = pVP->width; |
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/* color key */ |
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out32r ((pGD->vprBase + 0x0004), pVP->colorKey); |
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/* color key mask */ |
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out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask); |
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/* data src start adrs */ |
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out32r ((pGD->vprBase + 0x000c), pVP->start / 8); |
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/* data width and offset */ |
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out32r ((pGD->vprBase + 0x0010), |
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((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | |
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(pGD->plnSizeX / 8 * pGD->gdfBytesPP)); |
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/* video window 1 */ |
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out32r ((pGD->vprBase + 0x0014), |
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((pVWin->top << 16) | pVWin->left)); |
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out32r ((pGD->vprBase + 0x0018), |
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((pVWin->bottom << 16) | pVWin->right)); |
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out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); |
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out32r ((pGD->vprBase + 0x0020), |
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(((pVWin->offset / 8) << 16) | (pVWin->width / 8))); |
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out32r ((pGD->vprBase + 0x0024), |
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(((pVWin->hStretch) << 8) | pVWin->vStretch)); |
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/* video window 2 */ |
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out32r ((pGD->vprBase + 0x0028), |
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((pVWin->top << 16) | pVWin->left)); |
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out32r ((pGD->vprBase + 0x002c), |
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((pVWin->bottom << 16) | pVWin->right)); |
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out32r ((pGD->vprBase + 0x0030), |
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pVWin->srcStart / 8); |
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out32r ((pGD->vprBase + 0x0034), |
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(((pVWin->offset / 8) << 16) | (pVWin->width / 8))); |
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out32r ((pGD->vprBase + 0x0038), |
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(((pVWin->hStretch) << 8) | pVWin->vStretch)); |
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/* fifo prio control */ |
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out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); |
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/* fifo empty request levell */ |
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out32r ((pGD->vprBase + 0x0058), pVP->fifoERL); |
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/* conversion constant */ |
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out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB); |
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/* vpr control word */ |
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out32r ((pGD->vprBase + 0x0000), pVP->control); |
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} |
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/******************************************************************************
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* |
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* Init drawing engine registers |
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*/ |
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static void smiInitDrawingEngine (void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&smi; |
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unsigned int val; |
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/* don't start now */ |
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out32r ((pGD->dprBase + 0x000c), 0x000f0000); |
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/* set rop2 to copypen */ |
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val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c)); |
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out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c)); |
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/* set clip rect */ |
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out32r ((pGD->dprBase + 0x002c), 0); |
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out32r ((pGD->dprBase + 0x0030), |
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((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); |
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/* src row pitch */ |
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val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); |
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out32r ((pGD->dprBase + 0x0010), |
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(val | pGD->plnSizeX * pGD->gdfBytesPP)); |
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/* dst row pitch */ |
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val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); |
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out32r ((pGD->dprBase + 0x0010), |
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(((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); |
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/* window width src/dst */ |
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out32r ((pGD->dprBase + 0x003c), |
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(((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | |
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(pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); |
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out16r ((pGD->dprBase + 0x001e), 0x0000); |
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/* src base adrs */ |
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out32r ((pGD->dprBase + 0x0040), |
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(((pGD->frameAdrs/8) & 0x000fffff))); |
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/* dst base adrs */ |
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out32r ((pGD->dprBase + 0x0044), |
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(((pGD->frameAdrs/8) & 0x000fffff))); |
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/* foreground color */ |
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out32r ((pGD->dprBase + 0x0014), pGD->fg); |
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/* background color */ |
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out32r ((pGD->dprBase + 0x0018), pGD->bg); |
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/* xcolor */ |
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out32r ((pGD->dprBase + 0x0020), 0x00ffffff); |
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/* xcolor mask */ |
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out32r ((pGD->dprBase + 0x0024), 0x00ffffff); |
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/* bit mask */ |
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out32r ((pGD->dprBase + 0x0028), 0x00ffffff); |
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/* load mono pattern */ |
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out32r ((pGD->dprBase + 0x0034), 0); |
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out32r ((pGD->dprBase + 0x0038), 0); |
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} |
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static struct pci_device_id supported[] = { |
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{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 }, |
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{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 }, |
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{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 }, |
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{ } |
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}; |
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/*****************************************************************************/ |
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static void smiLoadMsr (struct ctfb_res_modes *mode) |
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{ |
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unsigned char h_synch_high, v_synch_high; |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ |
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v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ |
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out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29)); |
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/* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
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* Selects the upper 64KB page.Bit5=1 |
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* CLK2 (left reserved in standard VGA) Bit3|2=1|0 |
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* Disables CPU access to frame buffer. Bit1=0 |
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* Sets the I/O address decode for ST01, FCR, and all CR registers |
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* to the 3Dx I/O address range (CGA emulation). Bit0=1 |
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*/ |
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} |
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/*****************************************************************************/ |
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static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel) |
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{ |
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unsigned char cr[0x7a]; |
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int i; |
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unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */ |
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unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */ |
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unsigned int bpp, wd, dblscan, interlaced; |
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const int LineCompare = 0x3ff; |
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unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ |
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register GraphicDevice *pGD = (GraphicDevice *)&smi; |
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/* Horizontal */ |
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hd = (var->xres) / 8; /* HDisp. */ |
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hs = (var->xres + var->right_margin) / 8; /* HsStrt */ |
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he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ |
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ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ |
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/* Blank */ |
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hbs = hd; |
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hbe = 0; /* Blank end at 0 */ |
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/* Vertical */ |
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vd = var->yres; /* VDisplay */ |
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vs = var->yres + var->lower_margin; /* VSyncStart */ |
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ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ |
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vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ |
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vbs = vd; |
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vbe = 0; |
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bpp = bits_per_pixel; |
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dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; |
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interlaced = var->vmode & FB_VMODE_INTERLACED; |
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if (bpp == 15) |
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bpp = 16; |
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wd = var->xres * bpp / 64; /* double words per line */ |
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if (interlaced) { /* we divide all vertical timings, exept vd */ |
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vs >>= 1; |
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vbs >>= 1; |
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ve >>= 1; |
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vt >>= 1; |
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} |
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memset (cr, 0, sizeof (cr)); |
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cr[0x00] = ht - 5; |
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cr[0x01] = hd - 1; |
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cr[0x02] = hbs - 1; |
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cr[0x03] = (hbe & 0x1F); |
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cr[0x04] = hs; |
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cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); |
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cr[0x06] = (vt - 2) & 0xFF; |
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cr[0x07] = (((vt - 2) & 0x100) >> 8) |
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| (((vd - 1) & 0x100) >> 7) |
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| ((vs & 0x100) >> 6) |
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| (((vbs - 1) & 0x100) >> 5) |
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| ((LineCompare & 0x100) >> 4) |
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| (((vt - 2) & 0x200) >> 4) |
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| (((vd - 1) & 0x200) >> 3) |
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| ((vs & 0x200) >> 2); |
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cr[0x30] = ((vt - 2) & 0x400) >> 7 |
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| (((vd - 1) & 0x400) >> 8) |
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| (((vbs - 1) & 0x400) >> 9) |
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| ((vs & 0x400) >> 10) |
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| (interlaced) ? 0x80 : 0; |
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cr[0x08] = 0x00; |
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cr[0x09] = (dblscan << 7) |
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| ((LineCompare & 0x200) >> 3) |
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| (((vbs - 1) & 0x200) >> 4) |
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| (TextScanLines - 1); |
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cr[0x10] = vs & 0xff; /* VSyncPulseStart */ |
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cr[0x11] = (ve & 0x0f); |
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cr[0x12] = (vd - 1) & 0xff; /* LineCount */ |
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cr[0x13] = wd & 0xff; |
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cr[0x14] = 0x40; |
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cr[0x15] = (vbs - 1) & 0xff; |
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cr[0x16] = vbe & 0xff; |
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cr[0x17] = 0xe3; /* but it does not work */ |
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cr[0x18] = 0xff & LineCompare; |
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cr[0x22] = 0x00; /* todo? */ |
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/* now set the registers */ |
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for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */ |
||||
smiWrite (SMI_INDX_D4, i, cr[i]); |
||||
} |
||||
i = 0x22; /*CR22 */ |
||||
smiWrite (SMI_INDX_D4, i, cr[i]); |
||||
i = 0x30; /*CR30 */ |
||||
smiWrite (SMI_INDX_D4, i, cr[i]); |
||||
} |
||||
|
||||
/*****************************************************************************/ |
||||
#define REF_FREQ 14318180 |
||||
#define PMIN 1 |
||||
#define PMAX 255 |
||||
#define QMIN 1 |
||||
#define QMAX 63 |
||||
|
||||
static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq) |
||||
{ |
||||
unsigned int n = QMIN, m = 0; |
||||
long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1; |
||||
long long int D = 0x7ffffffffffffffLL; |
||||
|
||||
for (n = QMIN; n <= QMAX; n++) { |
||||
m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */ |
||||
L = P * n - m * Q; |
||||
while (L > 0 && m < PMAX) { |
||||
L -= REF_FREQ; /* difference is greater as 0 subtract fref */ |
||||
m++; /* and increment m */ |
||||
} |
||||
/* difference is less or equal than 0 or m > maximum */ |
||||
if (m > PMAX) |
||||
break; /* no solution: if we increase n we get the same situation */ |
||||
/* L is <= 0 now */ |
||||
if (-L > H && m > PMIN) { /* if difference > the half fref */ |
||||
L += REF_FREQ; /* we take the situation before */ |
||||
m--; /* because its closer to 0 */ |
||||
} |
||||
L = (L < 0) ? -L : +L; /* absolute value */ |
||||
if (D < L) /* if last difference was better take next n */ |
||||
continue; |
||||
D = L; |
||||
*pp = m; |
||||
*pq = n; /* keep improved data */ |
||||
if (D == 0) |
||||
break; /* best result we can get */ |
||||
} |
||||
return (unsigned int) (0xffffffff & D); |
||||
} |
||||
|
||||
/*****************************************************************************/ |
||||
static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id) |
||||
{ |
||||
unsigned int p = 0; |
||||
unsigned int q = 0; |
||||
long long freq; |
||||
register GraphicDevice *pGD = (GraphicDevice *)&smi; |
||||
|
||||
smiWrite (SMI_INDX_C4, 0x65, 0); |
||||
smiWrite (SMI_INDX_C4, 0x66, 0); |
||||
smiWrite (SMI_INDX_C4, 0x68, 0x50); |
||||
if (device_id == PCI_DEVICE_ID_SMI_810) { |
||||
smiWrite (SMI_INDX_C4, 0x69, 0x3); |
||||
} else { |
||||
smiWrite (SMI_INDX_C4, 0x69, 0x0); |
||||
} |
||||
|
||||
/* Memory clock */ |
||||
switch (device_id) { |
||||
case PCI_DEVICE_ID_SMI_710 : |
||||
smiWrite (SMI_INDX_C4, 0x6a, 0x75); |
||||
break; |
||||
case PCI_DEVICE_ID_SMI_712 : |
||||
smiWrite (SMI_INDX_C4, 0x6a, 0x80); |
||||
break; |
||||
default : |
||||
smiWrite (SMI_INDX_C4, 0x6a, 0x53); |
||||
break; |
||||
} |
||||
smiWrite (SMI_INDX_C4, 0x6b, 0x15); |
||||
|
||||
/* VCLK */ |
||||
freq = 1000000000000LL / var -> pixclock; |
||||
|
||||
FindPQ ((unsigned int)freq, &p, &q); |
||||
|
||||
smiWrite (SMI_INDX_C4, 0x6c, p); |
||||
smiWrite (SMI_INDX_C4, 0x6d, q); |
||||
|
||||
} |
||||
|
||||
/*******************************************************************************
|
||||
* |
||||
* Init video chip with common Linux graphic modes (lilo) |
||||
*/ |
||||
void *video_hw_init (void) |
||||
{ |
||||
GraphicDevice *pGD = (GraphicDevice *)&smi; |
||||
unsigned short device_id; |
||||
pci_dev_t devbusfn; |
||||
int videomode; |
||||
unsigned long t1, hsynch, vsynch; |
||||
unsigned int pci_mem_base, *vm; |
||||
char *penv; |
||||
int tmp, i, bits_per_pixel; |
||||
struct ctfb_res_modes *res_mode; |
||||
struct ctfb_res_modes var_mode; |
||||
unsigned char videoout; |
||||
|
||||
/* Search for video chip */ |
||||
printf("Video: "); |
||||
|
||||
if ((devbusfn = pci_find_devices(supported, 0)) < 0) |
||||
{ |
||||
printf ("Controller not found !\n"); |
||||
return (NULL); |
||||
} |
||||
|
||||
/* PCI setup */ |
||||
pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
||||
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); |
||||
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); |
||||
pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); |
||||
|
||||
tmp = 0; |
||||
|
||||
videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; |
||||
/* get video mode via environment */ |
||||
if ((penv = getenv ("videomode")) != NULL) { |
||||
/* deceide if it is a string */ |
||||
if (penv[0] <= '9') { |
||||
videomode = (int) simple_strtoul (penv, NULL, 16); |
||||
tmp = 1; |
||||
} |
||||
} else { |
||||
tmp = 1; |
||||
} |
||||
if (tmp) { |
||||
/* parameter are vesa modes */ |
||||
/* search params */ |
||||
for (i = 0; i < VESA_MODES_COUNT; i++) { |
||||
if (vesa_modes[i].vesanr == videomode) |
||||
break; |
||||
} |
||||
if (i == VESA_MODES_COUNT) { |
||||
printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); |
||||
i = 0; |
||||
} |
||||
res_mode = |
||||
(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. |
||||
resindex]; |
||||
bits_per_pixel = vesa_modes[i].bits_per_pixel; |
||||
} else { |
||||
|
||||
res_mode = (struct ctfb_res_modes *) &var_mode; |
||||
bits_per_pixel = video_get_params (res_mode, penv); |
||||
} |
||||
|
||||
/* calculate hsynch and vsynch freq (info only) */ |
||||
t1 = (res_mode->left_margin + res_mode->xres + |
||||
res_mode->right_margin + res_mode->hsync_len) / 8; |
||||
t1 *= 8; |
||||
t1 *= res_mode->pixclock; |
||||
t1 /= 1000; |
||||
hsynch = 1000000000L / t1; |
||||
t1 *= |
||||
(res_mode->upper_margin + res_mode->yres + |
||||
res_mode->lower_margin + res_mode->vsync_len); |
||||
t1 /= 1000; |
||||
vsynch = 1000000000L / t1; |
||||
|
||||
/* fill in Graphic device struct */ |
||||
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, |
||||
res_mode->yres, bits_per_pixel, (hsynch / 1000), |
||||
(vsynch / 1000)); |
||||
printf ("%s\n", pGD->modeIdent); |
||||
pGD->winSizeX = res_mode->xres; |
||||
pGD->winSizeY = res_mode->yres; |
||||
pGD->plnSizeX = res_mode->xres; |
||||
pGD->plnSizeY = res_mode->yres; |
||||
switch (bits_per_pixel) { |
||||
case 8: |
||||
pGD->gdfBytesPP = 1; |
||||
pGD->gdfIndex = GDF__8BIT_INDEX; |
||||
break; |
||||
case 15: |
||||
pGD->gdfBytesPP = 2; |
||||
pGD->gdfIndex = GDF_15BIT_555RGB; |
||||
break; |
||||
case 16: |
||||
pGD->gdfBytesPP = 2; |
||||
pGD->gdfIndex = GDF_16BIT_565RGB; |
||||
break; |
||||
case 24: |
||||
pGD->gdfBytesPP = 3; |
||||
pGD->gdfIndex = GDF_24BIT_888RGB; |
||||
break; |
||||
} |
||||
|
||||
pGD->isaBase = CONFIG_SYS_ISA_IO; |
||||
pGD->pciBase = pci_mem_base; |
||||
pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); |
||||
pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); |
||||
pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000); |
||||
pGD->frameAdrs = pci_mem_base; |
||||
pGD->memSize = VIDEO_MEM_SIZE; |
||||
|
||||
/* Set up hardware : select color mode,
|
||||
set Register base to isa 3dx for 3?x regs*/ |
||||
out8 (SMI_MISC_REG, 0x01); |
||||
|
||||
/* Turn off display */ |
||||
smiWrite (SMI_INDX_C4, 0x01, 0x20); |
||||
|
||||
/* Unlock ext. crt regs */ |
||||
out8 (SMI_LOCK_REG, 0x40); |
||||
|
||||
/* Unlock crt regs 0-7 */ |
||||
smiWrite (SMI_INDX_D4, 0x11, 0x0e); |
||||
|
||||
/* Sytem Control Register */ |
||||
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR)); |
||||
|
||||
/* extented CRT Register */ |
||||
smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT)); |
||||
|
||||
/* Attributes controller registers */ |
||||
smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR)); |
||||
|
||||
/* Graphics Controller Register */ |
||||
smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR)); |
||||
|
||||
/* Sequencer Register */ |
||||
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR)); |
||||
|
||||
/* Power Control Register */ |
||||
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR)); |
||||
|
||||
/* Memory Control Register */ |
||||
/* Register MSR62 is a power on configurable register. We don't */ |
||||
/* modify it */ |
||||
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR)); |
||||
|
||||
/* Set misc output register */ |
||||
smiLoadMsr (res_mode); |
||||
|
||||
/* Set CRT and Clock control registers */ |
||||
smiLoadCrt (res_mode, bits_per_pixel); |
||||
|
||||
smiLoadCcr (res_mode, device_id); |
||||
|
||||
/* Hardware Cusor Register */ |
||||
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR)); |
||||
|
||||
/* Enable Display */ |
||||
videoout = 2; /* Default output is CRT */ |
||||
if ((penv = getenv ("videoout")) != NULL) { |
||||
/* deceide if it is a string */ |
||||
videoout = (int) simple_strtoul (penv, NULL, 16); |
||||
} |
||||
smiWrite (SMI_INDX_C4, 0x31, videoout); |
||||
|
||||
/* Video processor default setup */ |
||||
smiInitVideoProcessor (); |
||||
|
||||
/* Capture port default setup */ |
||||
smiInitCapturePort (); |
||||
|
||||
/* Drawing engine default setup */ |
||||
smiInitDrawingEngine (); |
||||
|
||||
/* Turn on display */ |
||||
smiWrite (0x3c4, 0x01, 0x01); |
||||
|
||||
/* Clear video memory */ |
||||
i = pGD->memSize/4; |
||||
vm = (unsigned int *)pGD->pciBase; |
||||
while(i--) |
||||
*vm++ = 0; |
||||
return ((void*)&smi); |
||||
} |
||||
|
||||
/*******************************************************************************
|
||||
* |
||||
* Drawing engine fill on screen region |
||||
*/ |
||||
void video_hw_rectfill ( |
||||
unsigned int bpp, /* bytes per pixel */ |
||||
unsigned int dst_x, /* dest pos x */ |
||||
unsigned int dst_y, /* dest pos y */ |
||||
unsigned int dim_x, /* frame width */ |
||||
unsigned int dim_y, /* frame height */ |
||||
unsigned int color /* fill color */ |
||||
) |
||||
{ |
||||
register GraphicDevice *pGD = (GraphicDevice *)&smi; |
||||
register unsigned int control; |
||||
|
||||
dim_x *= bpp; |
||||
|
||||
out32r ((pGD->dprBase + 0x0014), color); |
||||
out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); |
||||
out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); |
||||
|
||||
control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c)); |
||||
|
||||
control |= 0x80010000; |
||||
|
||||
out32r ((pGD->dprBase + 0x000c), control); |
||||
|
||||
/* Wait for drawing processor */ |
||||
do |
||||
{ |
||||
out8 ((pGD->isaBase + 0x3c4), 0x16); |
||||
} while (in8 (pGD->isaBase + 0x3c5) & 0x08); |
||||
} |
||||
|
||||
/*******************************************************************************
|
||||
* |
||||
* Drawing engine bitblt with screen region |
||||
*/ |
||||
void video_hw_bitblt ( |
||||
unsigned int bpp, /* bytes per pixel */ |
||||
unsigned int src_x, /* source pos x */ |
||||
unsigned int src_y, /* source pos y */ |
||||
unsigned int dst_x, /* dest pos x */ |
||||
unsigned int dst_y, /* dest pos y */ |
||||
unsigned int dim_x, /* frame width */ |
||||
unsigned int dim_y /* frame height */ |
||||
) |
||||
{ |
||||
register GraphicDevice *pGD = (GraphicDevice *)&smi; |
||||
register unsigned int control; |
||||
|
||||
dim_x *= bpp; |
||||
|
||||
if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x))) |
||||
{ |
||||
out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1))); |
||||
out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1))); |
||||
control = 0x88000000; |
||||
} else { |
||||
out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y)); |
||||
out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); |
||||
control = 0x80000000; |
||||
} |
||||
|
||||
out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); |
||||
control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c))); |
||||
out32r ((pGD->dprBase + 0x000c), control); |
||||
|
||||
/* Wait for drawing processor */ |
||||
do |
||||
{ |
||||
out8 ((pGD->isaBase + 0x3c4), 0x16); |
||||
} while (in8 (pGD->isaBase + 0x3c5) & 0x08); |
||||
} |
||||
|
||||
/*******************************************************************************
|
||||
* |
||||
* Set a RGB color in the LUT (8 bit index) |
||||
*/ |
||||
void video_set_lut ( |
||||
unsigned int index, /* color number */ |
||||
unsigned char r, /* red */ |
||||
unsigned char g, /* green */ |
||||
unsigned char b /* blue */ |
||||
) |
||||
{ |
||||
register GraphicDevice *pGD = (GraphicDevice *)&smi; |
||||
|
||||
out8 (SMI_LUT_MASK, 0xff); |
||||
|
||||
out8 (SMI_LUT_START, (char)index); |
||||
|
||||
out8 (SMI_LUT_RGB, r>>2); /* red */ |
||||
udelay (10); |
||||
out8 (SMI_LUT_RGB, g>>2); /* green */ |
||||
udelay (10); |
||||
out8 (SMI_LUT_RGB, b>>2); /* blue */ |
||||
udelay (10); |
||||
} |
Loading…
Reference in new issue