clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

drivers/clk/clk_stm32f.c

@@ -59,7 +59,7 @@
 #define RCC_PLLCFGR_PLLSAIP_MASK	GENMASK(17, 16)
 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT	6
 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT	16
-#define RCC_PLLSAICFGR_PLLSAIP_4	BIT(17)
+#define RCC_PLLSAICFGR_PLLSAIP_4	BIT(16)
 #define RCC_PLLSAICFGR_PLLSAIQ_4	BIT(26)
 #define RCC_PLLSAICFGR_PLLSAIR_2	BIT(29)