Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
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/*
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* (C) Copyright 2007 |
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
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* |
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* Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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/*
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* Jump to P2 area. |
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* When handling TLB or caches, we need to do it from P2 area. |
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*/ |
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#define jump_to_P2() \ |
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"or %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy) \
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: "r" (0x20000000)); \
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} while (0) |
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/*
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* Back to P1 area. |
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*/ |
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#define back_to_P1() \ |
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"nop;nop;nop;nop;nop;nop;nop\n\t" \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0) |
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#define CACHE_VALID 1 |
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#define CACHE_UPDATED 2 |
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static inline void cache_wback_all(void) |
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{ |
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unsigned long addr, data, i, j; |
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jump_to_P2(); |
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for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { |
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for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { |
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addr = CACHE_OC_ADDRESS_ARRAY |
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| (j << CACHE_OC_WAY_SHIFT) |
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| (i << CACHE_OC_ENTRY_SHIFT); |
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data = inl(addr); |
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if (data & CACHE_UPDATED) { |
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data &= ~CACHE_UPDATED; |
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outl(data, addr); |
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} |
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} |
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} |
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back_to_P1(); |
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} |
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#define CACHE_ENABLE 0 |
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#define CACHE_DISABLE 1 |
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int cache_control(unsigned int cmd) |
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{ |
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unsigned long ccr; |
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jump_to_P2(); |
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ccr = inl(CCR); |
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if (ccr & CCR_CACHE_ENABLE) |
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cache_wback_all(); |
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if (cmd == CACHE_DISABLE) |
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outl(CCR_CACHE_STOP, CCR); |
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else |
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outl(CCR_CACHE_INIT, CCR); |
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back_to_P1(); |
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return 0; |
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} |
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