Change initdram() return type to phys_size_t

This patch changes the return type of initdram() from long int to phys_size_t.
This is required for a couple of reasons: long int limits the amount of dram
to 2GB, and u-boot in general is moving over to phys_size_t to represent the
size of physical memory.  phys_size_t is defined as an unsigned long on almost
all current platforms.

This patch *only* changes the return type of the initdram function (in
include/common.h, as well as in each board's implementation of initdram).  It
does not actually modify the code inside the function on any of the platforms;
platforms which wish to support more than 2GB of DRAM will need to modify
their initdram() function code.

Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc
MPC8641HPCN.

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
master
Becky Bruce 16 years ago committed by Wolfgang Denk
parent 391fd93ab2
commit 9973e3c614
  1. 2
      board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
  2. 4
      board/LEOX/elpt860/elpt860.c
  3. 2
      board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
  4. 2
      board/Marvell/db64360/sdram_init.c
  5. 2
      board/Marvell/db64460/sdram_init.c
  6. 2
      board/RPXClassic/RPXClassic.c
  7. 2
      board/RPXlite/RPXlite.c
  8. 2
      board/RPXlite_dw/RPXlite_dw.c
  9. 2
      board/RRvision/RRvision.c
  10. 2
      board/a3000/a3000.c
  11. 2
      board/adder/adder.c
  12. 2
      board/ads5121/ads5121.c
  13. 2
      board/alaska/alaska.c
  14. 2
      board/altera/dk1c20/dk1c20.c
  15. 2
      board/altera/dk1s10/dk1s10.c
  16. 2
      board/altera/ep1c20/ep1c20.c
  17. 2
      board/altera/ep1s10/ep1s10.c
  18. 2
      board/altera/ep1s40/ep1s40.c
  19. 2
      board/amcc/acadia/memory.c
  20. 2
      board/amcc/bamboo/bamboo.c
  21. 2
      board/amcc/bubinga/bubinga.c
  22. 2
      board/amcc/canyonlands/canyonlands.c
  23. 2
      board/amcc/ebony/ebony.c
  24. 2
      board/amcc/ocotea/ocotea.c
  25. 2
      board/amcc/sequoia/sdram.c
  26. 4
      board/amcc/taihu/taihu.c
  27. 2
      board/amcc/walnut/walnut.c
  28. 2
      board/amcc/yosemite/yosemite.c
  29. 2
      board/amirix/ap1000/ap1000.c
  30. 2
      board/atc/atc.c
  31. 2
      board/atmel/atngw100/atngw100.c
  32. 2
      board/atmel/atstk1000/atstk1000.c
  33. 2
      board/atum8548/atum8548.c
  34. 2
      board/barco/barco.c
  35. 2
      board/barco/barco_svc.h
  36. 4
      board/bc3450/bc3450.c
  37. 2
      board/bf533-ezkit/bf533-ezkit.c
  38. 2
      board/bf533-stamp/bf533-stamp.c
  39. 2
      board/bf537-stamp/bf537-stamp.c
  40. 2
      board/bf561-ezkit/bf561-ezkit.c
  41. 2
      board/bmw/bmw.c
  42. 2
      board/c2mon/c2mon.c
  43. 4
      board/canmb/canmb.c
  44. 2
      board/cm5200/cm5200.c
  45. 2
      board/cmi/cmi.c
  46. 2
      board/cobra5272/cobra5272.c
  47. 2
      board/cogent/mb.c
  48. 2
      board/cpc45/cpc45.c
  49. 2
      board/cpu86/cpu86.c
  50. 2
      board/cpu87/cpu87.c
  51. 2
      board/cray/L1/L1.c
  52. 2
      board/csb272/csb272.c
  53. 2
      board/csb472/csb472.c
  54. 2
      board/cu824/cu824.c
  55. 2
      board/dave/PPChameleonEVB/PPChameleonEVB.c
  56. 2
      board/dbau1x00/dbau1x00.c
  57. 2
      board/eXalion/eXalion.c
  58. 2
      board/eltec/bab7xx/bab7xx.c
  59. 2
      board/eltec/elppc/elppc.c
  60. 2
      board/eltec/mhpc/mhpc.c
  61. 2
      board/emk/top5200/top5200.c
  62. 2
      board/emk/top860/top860.c
  63. 2
      board/ep8248/ep8248.c
  64. 2
      board/ep8260/ep8260.c
  65. 2
      board/ep82xxm/ep82xxm.c
  66. 2
      board/ep88x/ep88x.c
  67. 2
      board/eric/eric.c
  68. 2
      board/esd/adciop/adciop.c
  69. 2
      board/esd/apc405/apc405.c
  70. 2
      board/esd/ash405/ash405.c
  71. 2
      board/esd/cms700/cms700.c
  72. 2
      board/esd/cpci2dp/cpci2dp.c
  73. 2
      board/esd/cpci405/cpci405.c
  74. 2
      board/esd/cpci5200/cpci5200.c
  75. 2
      board/esd/cpci750/sdram_init.c
  76. 2
      board/esd/cpciiser4/cpciiser4.c
  77. 2
      board/esd/dasa_sim/dasa_sim.c
  78. 2
      board/esd/dp405/dp405.c
  79. 2
      board/esd/du405/du405.c
  80. 2
      board/esd/hh405/hh405.c
  81. 2
      board/esd/hub405/hub405.c
  82. 2
      board/esd/mecp5200/mecp5200.c
  83. 2
      board/esd/ocrtc/ocrtc.c
  84. 2
      board/esd/pci405/pci405.c
  85. 2
      board/esd/pf5200/pf5200.c
  86. 2
      board/esd/plu405/plu405.c
  87. 2
      board/esd/pmc405/pmc405.c
  88. 2
      board/esd/pmc440/sdram.c
  89. 2
      board/esd/tasreg/tasreg.c
  90. 2
      board/esd/voh405/voh405.c
  91. 2
      board/esd/vom405/vom405.c
  92. 2
      board/esd/wuh405/wuh405.c
  93. 2
      board/esteem192e/esteem192e.c
  94. 2
      board/etin/debris/debris.c
  95. 2
      board/etin/kvme080/kvme080.c
  96. 2
      board/etx094/etx094.c
  97. 2
      board/evb64260/sdram_init.c
  98. 2
      board/exbitgen/exbitgen.c
  99. 2
      board/fads/fads.c
  100. 2
      board/flagadm/flagadm.c
  101. Some files were not shown because too many files have changed in this diff Show More

@ -39,7 +39,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int size,i;

@ -35,7 +35,7 @@
** ------
** int board_early_init_f(void)
** int checkboard(void)
** long int initdram(int board_type)
** phys_size_t initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
** void reset_phy(void)
@ -179,7 +179,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -81,7 +81,7 @@ int checkboard (void)
return 0;
}
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
return articiaS_ram_init ();
}

@ -1728,7 +1728,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };

@ -1737,7 +1737,7 @@ long int dram_size (long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int s0 = 0, s1 = 0;
int checkbank[4] = {[0 ... 3] = 0 };

@ -165,7 +165,7 @@ void rpxclassic_init (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -102,7 +102,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -104,7 +104,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -110,7 +110,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -38,7 +38,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;

@ -65,7 +65,7 @@ static uint sdram_table[] = {
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
};
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;

@ -112,7 +112,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
u32 msize = 0;

@ -131,7 +131,7 @@ void setupBat (ulong size)
mtspr (DBAT7U, batu);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong size;

@ -50,7 +50,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

@ -54,7 +54,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

@ -34,7 +34,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

@ -29,7 +29,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (0);
}

@ -59,7 +59,7 @@ static void cram_bcr_write(u32 wr_val)
}
#endif
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_NAND_SPL)
u32 reg;

@ -453,7 +453,7 @@ int checkboard(void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
long dram_size;

@ -70,7 +70,7 @@ int checkboard(void)
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long int ret;

@ -205,7 +205,7 @@ u32 ddr_clktr(u32 default_val) {
* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
* code.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return CFG_MBYTES_SDRAM << 20;
}

@ -104,7 +104,7 @@ int checkboard(void)
return (0);
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long dram_size = 0;

@ -201,7 +201,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long dram_size = 0;

@ -52,7 +52,7 @@ extern void denali_core_search_data_eye(void);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)

@ -78,10 +78,10 @@ int checkboard(void)
}
/*************************************************************************
* long int initdram
* phys_size_t initdram
*
************************************************************************/
long int initdram(int board)
phys_size_t initdram(int board)
{
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
}

@ -89,7 +89,7 @@ int checkboard(void)
* initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
* the necessary info for SDRAM controller configuration
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return spd_sdram();
}

@ -281,7 +281,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
*tr1_value = (first_good + last_bad) / 2;
}
long int initdram(int board)
phys_size_t initdram(int board)
{
register uint reg;
int tr1_bank1, tr1_bank2;

@ -133,7 +133,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
char *s = getenv ("dramsize");

@ -340,7 +340,7 @@ int misc_init_r(void)
return (0);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;

@ -64,7 +64,7 @@ int board_early_init_f(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;

@ -90,7 +90,7 @@ int board_early_init_f(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
unsigned long expected_size;
unsigned long actual_size;

@ -98,7 +98,7 @@ long int fixed_sdram (void)
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
long int
phys_size_t
initdram(int board_type)
{
long dram_size = 0;

@ -83,7 +83,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long size;
long new_bank0_end;

@ -59,7 +59,7 @@ typedef struct SBootInfo {
/* barcohydra.c */
int checkboard(void);
long int initdram(int board_type);
phys_size_t initdram(int board_type);
void pci_init_board(void);
void check_flash(void);
int write_flash(char *addr, char value);

@ -104,7 +104,7 @@ static void sdram_start (int hi_addr)
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
@ -205,7 +205,7 @@ long int initdram (int board_type)
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT

@ -39,7 +39,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;

@ -48,7 +48,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
printf("SDRAM attributes:\n");

@ -97,7 +97,7 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
}
#endif /* CONFIG_BFIN_IDE */
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;

@ -39,7 +39,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
#ifdef DEBUG
int brate;

@ -51,7 +51,7 @@ int checkboard(void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return 64*1024*1024;
}

@ -108,7 +108,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -82,7 +82,7 @@ static void sdram_start (int hi_addr)
*/
#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
ulong dramsize2 = 0;
@ -185,7 +185,7 @@ long int initdram (int board_type)
#elif defined(CONFIG_MGT5100)
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT

@ -114,7 +114,7 @@ static mem_conf_t* get_mem_config(int board_type)
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT

@ -62,7 +62,7 @@ int checkboard(void)
/*
* Get RAM size.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */
}

@ -32,7 +32,7 @@ int checkboard (void)
return 0;
};
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);

@ -233,7 +233,7 @@ int misc_init_f (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#ifdef CONFIG_CMA111
return (32L * 1024L * 1024L);

@ -61,7 +61,7 @@ int checkboard(void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int m, row, col, bank, i, ref;
unsigned long start, end;

@ -273,7 +273,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
return (size);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;

@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
return (size);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;

@ -170,7 +170,7 @@ int misc_init_r (void)
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (L1_MEMSIZE);
}

@ -120,7 +120,7 @@ int checkboard(void)
* configured by initialization code
*
*/
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;

@ -88,7 +88,7 @@ int checkboard(void)
* configured by initialization code
*
*/
long initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong tot_size;
ulong bank_size;

@ -45,7 +45,7 @@ int checkboard (void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
long size;
long new_bank0_end;

@ -203,7 +203,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -27,7 +27,7 @@
#include <asm/mipsregs.h>
#include <asm/io.h>
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
/* Sdram is setup by assembler code */
/* If memory could be changed, we should return the true value here */

@ -52,7 +52,7 @@ int checkflash (void)
return (0);
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int i, cnt;
volatile uchar *base = CFG_SDRAM_BASE;

@ -162,7 +162,7 @@ long int dram_size (int board_type)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}

@ -104,7 +104,7 @@ long int dram_size (int board_type)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return dram_size (board_type);
}

@ -251,7 +251,7 @@ int misc_init_r (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -32,7 +32,7 @@
* initialize SDRAM/DDRAM controller.
* TBD: get data from I2C EEPROM
*****************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT

@ -76,7 +76,7 @@ int checkboard (void)
/*****************************************************************************
* Initialize DRAM controller
*****************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -208,7 +208,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
vu_char *bcsr = (vu_char *)CFG_BCSR;
long int msize = 16L << (bcsr[2] & 3);

@ -243,7 +243,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;

@ -219,7 +219,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
/* Size in MB of SDRAM populated on board*/
long int msize = 256;

@ -86,7 +86,7 @@ int board_early_init_f (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
long int msize;
volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;

@ -121,7 +121,7 @@ int checkboard (void)
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#ifndef CONFIG_ERIC
int i;

@ -79,7 +79,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}

@ -423,7 +423,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -207,7 +207,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -141,7 +141,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -117,7 +117,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -495,7 +495,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -84,7 +84,7 @@ static void sdram_start(int hi_addr)
* is something else than 0x00000000.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;

@ -1602,7 +1602,7 @@ dram_size(long int *base, long int maxsize)
/* ppcboot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int
phys_size_t
initdram(int board_type)
{
int s0 = 0, s1 = 0;

@ -186,7 +186,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}

@ -206,7 +206,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}

@ -122,7 +122,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -200,7 +200,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}

@ -644,7 +644,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -229,7 +229,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -84,7 +84,7 @@ static void sdram_start(int hi_addr)
* is something else than 0x00000000.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;

@ -101,7 +101,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -358,7 +358,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -84,7 +84,7 @@ static void sdram_start(int hi_addr)
* is something else than 0x00000000.
*/
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
ulong dramsize = 0;
ulong test1, test2;

@ -232,7 +232,7 @@ int checkboard (void)
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -157,7 +157,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -50,7 +50,7 @@ extern void denali_core_search_data_eye(void);
* initdram -- 440EPx's DDR controller is a DENALI Core
*
************************************************************************/
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
#if !defined(CONFIG_NAND_SPL)

@ -77,7 +77,7 @@ int checkboard (void) {
};
long int initdram (int board_type) {
phys_size_t initdram (int board_type) {
unsigned long junk = 0xa5a59696;
/*

@ -305,7 +305,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -129,7 +129,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -205,7 +205,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
unsigned long val;

@ -101,7 +101,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -53,7 +53,7 @@ int checkflash (void)
}
#endif
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
int m, row, col, bank, i;
unsigned long start, end;

@ -93,7 +93,7 @@ unsigned long setdram(int m, int row, int col, int bank)
return (1 << (col + row + 3) ) * bank * m;
}
long int initdram(int board_type)
phys_size_t initdram(int board_type)
{
unsigned int msr;
long int size = 0;

@ -125,7 +125,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

@ -524,7 +524,7 @@ static long int dram_size (long int *base, long int maxsize)
/* U-Boot interface function to SDRAM init - this is where all the
* controlling logic happens */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
ulong checkbank[4] = {[0 ... 3] = 0 };
int bank_no;

@ -71,7 +71,7 @@ int checkboard (void)
}
/* ************************************************************************ */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
/* ------------------------------------------------------------------------ --
* Purpose : Determines size of mounted DRAM.
* Remarks : Size is determined by reading SDRAM configuration registers as

@ -600,7 +600,7 @@ static int initsdram(uint base, uint *noMbytes)
/* ========================================================================= */
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
uint sdramsz = 0; /* size of sdram in Mbytes */
uint base = 0; /* base of dram in bytes */

@ -96,7 +96,7 @@ int checkboard (void)
return 0;
}
long int initdram (int board_type)
phys_size_t initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;

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